DETAILED ACTION
1. This action is in response to the amendment filed on 4/20/26.
Notice of Pre-AIA or AIA Status
2. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
3. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
4. Claims 1 and 7 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lazaro et al. (US 20190058385).
Regarding claim 7: Lazaro et al. disclose (i.e. figure 1 and 5) controller comprising:
flying capacitor (CFLY) voltage management circuitry (i.e. circuitry of 101) having a first control output (i.e. output of circuitry 101 for voltage VFLY) and first and second sense inputs (i.e. +/- inputs VFLY), the first sense input (i.e. input + VFLY) coupled to a first CFLY terminal (i.e. + terminal VFLY), the second sense input (i.e. input - VFLY) coupled to a second CFLY terminal (i.e. - terminal VFLY), the CFLY voltage management circuitry (i.e. circuitry of 101) capable of
providing a feedback signal (i.e. signal of 152) at the first control output (i.e. output of circuitry 101) responsive to a voltage across (i.e. VFLY) the first and second sense inputs (i.e. +/- inputs VFLY);
multi-mode control circuitry (i.e. circuitry of 140) having inputs (i.e. inputs for VFLY) and outputs (i.e. outputs of 140) and the multi-mode control circuitry capable of:
receiving the feedback signal (i.e. signal of 152) at the inputs (i.e. inputs for VFLY);
receiving a current sense signal (i.e. signal IFB) at the inputs (i.e. input for IFB);
in a first mode (i.e. mode having first and second state), providing switch control signals (i.e. signals of 158) at the outputs (i.e. output of 140) to switch between a first state (i.e. first state of 521) and a second state (i.e. second state of 522) responsive to the current sense signal (i.e. signal IFB), in which in the first state (i.e. first state of 522), the first CFLY terminal (i.e. + terminal) is disconnected from a power input (i.e. Vin)(i.e. Q1 off) and power output (i.e. Vout) (i.e. Q3 off), and in the second state (i.e. second state of 523), the second CFLY terminal (i.e. - terminal) is disconnected from the power input (i.e. Vin) (i.e. Q1 off) and the power output (i.e. Vout) (i.e. Q4 off);
in a second mode (i.e. second mode having third state), providing the switch control signals (i.e. output of 158) at the outputs (i.e. outputs of 140) to switch among the first state (i.e. first state of 522), the second state (i.e. second state of 523), and a third state (i.e. third state of 521) responsive to the current sense signal (i.e. signal IFB) and the feedback signal (i.e. signal of 152), in which in the third state (i.e. third state of 521), the first terminal (i.e. + terminal) is connected to the power input (i.e. Vin) (i.e. Q1 on) and the second terminal (i.e. - terminal) is connected to the power output (i.e. Vout) (i.e. Q4 on) or to a ground (i.e. ground).
Regarding claim 1: the method steps will be met during the normal operation of the apparatus described above. (Examiner notes: For method claims, note that under MPEP 2112.02, the principles of inherency, if a prior art device, in its normal and usual operation, would necessarily perform the method claimed, then the method claimed will be considered to be anticipated by the prior art device. When the prior art device is the same as a device described in the specification for carrying out the claimed method, it can be assumed the device will inherently perform the claimed process. In re King, 801 F.2d 1324, 231 USPQ 136 (Fed. Cir. 1986). Therefore, the previous rejections based on the apparatus will not be repeated).
Claim Rejections - 35 USC § 103
5. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
6. Claims 2-6 are rejected under 35 U.S.C. 103 as being unpatentable over Lazaro et al. (US 20190058385) in view of Assaad et al. (US 9866113).
Regarding claim 2: Lazaro et al. disclose the limitation of the claim(s) as discussed above, but does not specifically disclose receiving a peak current reference signal; receiving a current slope signal; and providing the switch control signals in the second mode responsive to the peak current reference signal, the current sense signal, the feedback signal, and the current slope signal.
Assad et al. disclose a converter (i.e. figure 4) receiving a peak current reference signal (i.e. signal to + terminal of 218); receiving a current slope signal (i.e. from 210); and providing the switch control signals (i.e. signals of 160) in the second mode responsive to the peak current reference signal (i.e. signal to + terminal of 218), the current sense signal (i.e. output current sensing), the feedback signal (i.e. signal from 226), and the current slop signal (i.e. from 210).
Therefore, it would have been obvious to one with ordinary skill in the art before the earliest effective filing date to modify the circuit of Lazaro et al.’s invention with the converter as disclose by Assad et al. for flying capacitor balancing in multilevel DC-DC converters.
Regarding claim 3: Lazaro et al. disclose the limitation of the claim(s) as discussed above, but does not specifically disclose receiving a first clock signal; receiving a second clock signal; and providing the switch control signals in the second mode responsive to the peak current reference signal, the current sense signal, the feedback signal, the current slope signal, the first clock signal, and the second clock signal.
Assad et al. disclose a converter (i.e. figure 4) receiving a first clock signal (i.e. 256A); receiving a second clock signal (i.e. 256B); and providing switch control signals (i.e. signals of 160) in the second mode responsive to the peak current reference signal (i.e. signal to + terminal of 218), the current sense signal (i.e. output current sensing), the feedback signal (i.e. signal from 226), the current slope signal (i.e. from 210), the first clock signal (i.e. 256A), and the second clock signal (i.e. 256B).
Therefore, it would have been obvious to one with ordinary skill in the art before the earliest effective filing date to modify the circuit of Lazaro et al.’s invention with the converter as disclose by Assad et al. for flying capacitor balancing in multilevel DC-DC converters.
Regarding claim 4: Lazaro et al. disclose the limitation of the claim(s) as discussed above, but does not specifically disclose triggering a CFLY voltage correction responsive to the first clock signal, the second clock signal, and the feedback signal.
Assad et al. disclose a converter (i.e. figure 4) triggering (i.e. by 256A) a CFLY voltage correction responsive to the first clock signal (i.e. 256A), the second clock signal (i.e. 256B), and the feedback signal (i.e. signal from 226).
Therefore, it would have been obvious to one with ordinary skill in the art before the earliest effective filing date to modify the circuit of Lazaro et al.’s invention with the converter as disclose by Assad et al. for flying capacitor balancing in multilevel DC-DC converters.
Regarding claim 5: Lazaro et al. disclose the limitation of the claim(s) as discussed above, but does not specifically disclose receiving a voltage compensation signal; and providing the switch control signals in the second mode responsive to the peak current reference signal, the current sense signal, the feedback signal, the current slope signal, and the voltage compensation signal.
Assad et al. disclose a converter (i.e. figure 4) receiving a voltage compensation signal (i.e. signal input to 224A from 230A and 222); and providing the switch control signals (i.e. signals of 160) in the second mode (i.e. mode by peak current loop) responsive to the peak current reference signal (i.e. signal to + terminal of 218), the current sense signal (i.e. output current sensing), the feedback signal (i.e. signal from 226), the current slope signa (i.e. from 210)l, and the voltage compensation signal (i.e. signal input to 224A from 230A and 222).
Therefore, it would have been obvious to one with ordinary skill in the art before the earliest effective filing date to modify the circuit of Lazaro et al.’s invention with the converter as disclose by Assad et al. for flying capacitor balancing in multilevel DC-DC converters.
Regarding claim 6: Lazaro et al. disclose the limitation of the claim(s) as discussed above, but does not specifically disclose triggering a CFLY voltage correction responsive to the current sense signal, the current slope signal, the voltage compensation signal, and the feedback signal.
Assad et al. disclose a converter (i.e. figure 4) triggering a CFLY voltage correction responsive to the current sense signal (i.e. output current sensing), the current slope signal (i.e. from 210), the voltage compensation signal (i.e. signal input to 224A from 230A and 222), and the feedback signal (i.e. signal from 226).
Therefore, it would have been obvious to one with ordinary skill in the art before the earliest effective filing date to modify the circuit of Lazaro et al.’s invention with the converter as disclose by Assad et al. for flying capacitor balancing in multilevel DC-DC converters.
7. Claims 8 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Lazaro et al. (US 20190058385) in view of Bonnano et al. (US 10686370).
Regarding claim 8: Lazaro et al. disclose the limitation of the claim(s) as discussed above, but does not specifically disclose a valley current sense circuit having an input and an output capable of: receiving a first high-side switch control signal of the switch control signals at the input of the valley current sense circuit; and proving a valley current sense signal at the output of the valley current sense circuit responsive to the first high-side switch control signal, wherein the multi-mode control circuitry is capable of providing the switch control signals responsive to the valley current sense signal.
Bonnano et al. a converter (i.e. figure 2A) comprising a valley current sense circuit (i.e. circuit of 200) having an input and an output capable of:
receiving a first high-side switch control signal (i.e. signal A2 to 212) of the switch control signals (i.e. A1, A2, B1, B2) at the input of the valley current sense circuit (i.e. circuit of 200); and proving a valley current sense signal (i.e. output of 232 and/or 24342) at the output of the valley current sense circuit (i.e. circuit of 200) responsive to the first high-side switch control signal (i.e. signal A2 to 212), wherein the multi-mode control circuitry is capable of providing the switch control signals (i.e. A1, A2, B1, B2) responsive to the valley current sense signal (i.e. output of 232 and/or 24342).
Therefore, it would have been obvious to one with ordinary skill in the art before the earliest effective filing date to modify the circuit of Lazaro et al.’s invention with the converter as disclose by Bonnano et al. to provide stability of the power converter.
Regarding claim 11: Lazaro et al. disclose the limitation of the claim(s) as discussed above, but does not specifically disclose a peak current sense circuit capable of receiving a first low-side switch control signal of the switch control; and providing the current sense signal responsive to the first low-side switch control signal.
Bonnano et al. a converter (i.e. figure 2A) comprising a peak current sense circuit (i.e. circuit of 200) capable of receiving a first low-side switch control signal (i.e. A2) of the switch control; and providing the current sense signal (i.e. output of 232 and/or 24342) responsive to the first low-side switch control signal (i.e. A2).
Therefore, it would have been obvious to one with ordinary skill in the art before the earliest effective filing date to modify the circuit of Lazaro et al.’s invention with the converter as disclose by Bonnano et al. to provide stability of the power converter.
8. Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Lazaro et al. (US 20190058385) in view of Yang et al. (US 20240235388).
Regarding claim 12: Assaad et al. disclose (i.e. figure 4) the multi-mode control circuitry includes peak current limit control circuitry that includes:
a comparator (i.e. 218) having an inverting input, a non-inverting input and a comparator output, the inverting input coupled (i.e. electrically coupled) to one of the inputs (i.e. + input terminal of 218) of the multi-mode control circuitry, the non-inverting input coupled (i.e. electrically coupled) to another one of the inputs (i.e. input of 210) of the multi-mode control circuitry;
a first SR latch (i.e. 252A) having a first S input, a first R input, and a first Q output, the first R input coupled (i.e. electrically coupled) to the comparator output (i.e. output of 218), the first Q output coupled (i.e. electrically coupled) to a fourth output of the outputs (i.e. output 1-D180);
a second SR latch (i.e. 252B) having a second S input, a second R input, and a second Q output, the second R input coupled (i.e. electrically coupled) to the comparator output (i.e. output of 218), the second Q output coupled (i.e. electrically coupled) to a third output of the outputs (i.e. output D180),
but does not specifically disclose a first inverter having a first inverter input and a first inverter output, the first inverter input coupled to the first Q output, and the first inverter output coupled to a first output of the outputs; and a second inverter having a second inverter input and a second inverter output, the second inverter input coupled to the second Q output, and the second inverter output coupled to a second output of the outputs.
Yang et al. disclose a power converter (i.e. figure 2) comprising a first inverter (i.e. 280) having a first inverter input and a first inverter output, the first inverter input coupled (i.e. electrically coupled) to the first Q output (i.e. output of 292), and the first inverter output coupled (i.e. electrically coupled) to the first output of the outputs (i.e. output of circuitry for 240); and a second inverter (i.e. 282) having a second inverter input and a second inverter output, the second inverter input coupled (i.e. electrically coupled) to the second Q output (i.e. output of 298), and the second inverter output coupled (i.e. electrically coupled) to the second output of the outputs (i.e. from 300).
Therefore, it would have been obvious to one with ordinary skill in the art before the earliest effective filing date to modify the circuit of Assaad et al.’s invention with the converter as disclose by Yang et al. to provide protection with regard to under and over voltage.
9. Claims 13 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Lazaro et al. (US 20190058385) in view of Yang et al. (US 20240235388) and further in view of Assaad et al. (US 9866113).
Regarding claim 13: Lazaro et al. disclose the limitation of the claim(s) as discussed above, but does not specifically disclose the peak current limit control circuitry capable of: receiving a peak current reference signal: receiving a current slope signal; receiving a first clock signal; receiving a second clock signal ; and providing the switch control signals responsive to the peak current reference signal, the current sense signal, the feedback signal, the current slope signal, the first clock signal, and the second clock signal.
Assad et al. disclose a converter (i.e. figure 4) wherein the peak current limit control circuitry has a fourth control input and first and second clock inputs (i.e. from 256A, 256B), the peak current limit control circuitry capable of: receiving a peak current reference signal (i.e. signal to + terminal of 218) receiving a current slope signal (i.e. from 210) at the fourth control input; receive a first clock signal (i.e. from 256A) at the first clock input; capable of a second clock signal (i.e. from 256B) at the second clock input; and providing switch control signals (i.e. signals of 160) at the second control output, the third control output, the fourth control output, and the fifth control output responsive to the peak current reference signal (i.e. signal to + terminal of 218), the current sense signal (i.e. output current sensing), the CFLY voltage error feedback signal (i.e. signal from 226), the current slope signal (i.e. from 210), the first clock signal (i.e. from 256A), and the second clock signal (i.e. from 256B).
Therefore, it would have been obvious to one with ordinary skill in the art before the earliest effective filing date to modify the circuit of Lazaro et al.’s invention with the converter as disclose by Assad et al. for flying capacitor balancing in multilevel DC-DC converters.
Regarding claim 15: Lazaro et al. disclose the limitation of the claim(s) as discussed above, but does not specifically disclose the peak current limit control circuitry capable of: receiving a peak current reference signal: receiving a current slope signal; receiving a voltage compensation signal; and providing the switch control signals responsive to the peak current reference signal, the current sense signal, the feedback signal, the current slope signal, and the voltage compensation signal.
Assad et al. disclose a converter (i.e. figure 4) receiving a peak current reference signal (i.e. signal to + terminal of 218);
receiving a current slope signal (i.e. from 210); receiving a voltage compensation signal (i.e. signal input to 224A from 230A and 222); and
providing the switch control signals (i.e. signals of 160) responsive to the peak current reference signal (i.e. signal to + terminal of 218), the current sense signal (i.e. output current sensing), the feedback signal (i.e. signal from 226), the current slope signal (i.e. from 210), and the voltage compensation signal (i.e. signal input to 224A from 230A and 222).
Therefore, it would have been obvious to one with ordinary skill in the art before the earliest effective filing date to modify the circuit of Lazaro et al.’s invention with the converter as disclose by Assad et al. for flying capacitor balancing in multilevel DC-DC converters.
Allowable Subject Matter
10. Claims 9, 14, 16, and 22-25 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
11. Applicant's arguments filed 4/20/26 have been fully considered but they are not persuasive.
Applicant argues that Lazaro fails to disclose “operates in the claimed states in a first and second mode as recited in claims 1 and 7 and switching between two operation modes in which one mode is a two-state mode, and another mode is a three-state mode.”
The Examiner disagrees, because Lazaro discloses (i.e. figures 1 and 5, equivalent show in parentheses) in a first mode (i.e. mode having first and second state), … in which in the first state (i.e. first state of 522), the first CFLY terminal (i.e. + terminal) is disconnected from a power input (i.e. Vin)(i.e. Q1 off) and power output (i.e. Vout) (i.e. Q3 off), and in the second state (i.e. second state of 523), the second CFLY terminal (i.e. - terminal) is disconnected from the power input (i.e. Vin) (i.e. Q1 off) and the power output (i.e. Vout) (i.e. Q4 off);
in a second mode (i.e. second mode having third state), …in which in the third state (i.e. third state of 521), the first terminal (i.e. + terminal) is connected to the power input (i.e. Vin) (i.e. Q1 on) and the second terminal (i.e. - terminal) is connected to the power output (i.e. Vout) (i.e. Q4 on) or to a ground (i.e. ground).
Conclusion
12. THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
13. Any inquiry concerning this communication or earlier communications from the examiner should be directed to NGUYEN TRAN whose telephone number is (571)270-1269. The examiner can normally be reached Flex: M-F 8-7.
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/Nguyen Tran/ Primary Examiner, Art Unit 2838
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