DETAILED ACTION
Claims 1-20 are pending.
Notice of Pre-AIA or AIA Status
This Office Action is sent in response to Applicant’s Communication received on 02/09/2026 for application number 18/162,669.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 1, 2, 6, 8 is rejected under 35 U.S.C. 103 as being unpatentable over Rachakonda et al. (US 2022/0075440 A1) in view of Kim et al. (US 11264076 B2) /(US 2020/0211616 A1).
Regarding claim 1, Rachakonda teaches an apparatus (system of Figure 1), comprising:
a light modulator configured to modulate light to display frames of images based on display image data (“A frame may refer to a single image to be displayed on the display at a certain point in time. The data representing the frame (e.g. pixel colors in red-green-blue (RGB) format or luminance-chrominance format (YUV), or any other representation) may be stored in memory 12 and read and processed by the display controller 34 to drive the display 42” par 0030) [this defines a frame as an image and display image data as pixel colors which drive the display (light modulator)];
a controller coupled to the light modulator (Figure 1, display controller 34 is coupled to display 42) and configured to:
obtain a sequence of image data to be displayed by the light modulator (“The frames 38 may be “prerendered” in the sense that the frames 38 are rendered in preparation for powering down the CPUs 30, the GPUs, and other components in the SOC 10 while keeping the display controller 34 and the memory controller 22 powered to permit the display controller 34 to read the frames 38 and display the frames on the display 42.” Par 0028) [reading the frames corresponds to obtaining a sequence of image data];
produce the display image data based on the sequence of image data (“if there is dynamic content to be rendered (decision block 124, “yes” leg), the processor 36 may be configured to access the dynamic content and the next frame from the memory 12, and render the dynamic content into the next frame (block 126).” Par 0072 and Figure 5) [this shows a processor rendering (producing) new image data by combining dynamic content with the next frame (from image data sequence)];
transmit the display image data to the light modulator (“The processor 36 may process the current frame and transmit the processed frame to the display 42 for display (reference numeral 122).” Par 0071);
predict one or more gaps in the display image data and a time length of each gap based on a pattern of the sequence of image data (“The processor 36 in the display controller 34 may be configured to determine that the next frame time (e.g. the time that the next frame is to be displayed) is greater than a threshold amount (reference numeral 88)” par 0065 and “When the display controller 34 has completed the display of a frame, the display controller 34 may detect a sleep state for the display controller 34 responsive to the delay to the next frame being large enough to make transition to a lower power state worthwhile (e.g. the power saved will outweigh power expending to shut down the display controller 34, power the display controller 34 back up again, and restore state to the display controller 34).” Par 0056 and Figure 2) [the delay to the next frame corresponds to the gap; checking if the gap is large enough corresponds to predicting the time length and gap based on the frame sequence and display time (pattern)];
determine, based on the prediction, a number of sleep modes, of a set of sleep modes, to sequentially enter, in which each sleep mode of the number of sleep modes is configured to reduce power usage by the controller, the light modulator, or an interface between the controller and the light modulator compared to a normal operation mode, wherein the number of sleep modes determined to be sequentially entered is an integer of two or greater (“The processor 36 in the display controller 34 may be configured to determine that the next frame time (e.g. the time that the next frame is to be displayed) is greater than a threshold amount (reference numeral 88)” par 0065 and “If the next frame is greater than the threshold, the processor 36 in the display controller 34 may also signal the PMGR 32 to transition to the sleep 3 state 56.” Par 0066 and Figure 2) [this shows the determination of a sleep mode (sleep 3 state 56) is based on a prediction (if the “next frame time is greater than a threshold”)] (“When the display controller 34 has completed the display of a frame, the display controller 34 may detect a sleep state for the display controller 34 responsive to the delay to the next frame being large enough to make transition to a lower power state worthwhile… If such an event is detected, the state machine may transition to the sleep 2 state 54 (“disp sleep” arc in FIG. 2).” par 0056 and “The always-on component 16 may determine that access to memory 12 is not expected to be needed for a period of time, and may cause a transition to the sleep 3 state 56 (“mem sleep” arc in FIG. 2).” Par 0057) [this shows a process that sequentially enters a number of sleep modes (sleep 2 and 3) from a set of available modes based on different conditions] (“In the sleep 2 state 54, the power domain 28 is powered down… In the sleep 3 state 56, the power domain 24 is powered but the power domains 28 and 26 are powered down” par 0057) (“Accordingly, a series of transitions between the sleep 1 state 52 and the sleep 3 state 56 (either through the sleep 2 state 54, or directly between the states 52 and 56, in various embodiments) may be made during the time that the CPUs 30 are powered down to allow the frames to be displayed” par 0068) [this explicitly shows the number of sleep modes determined to be sequentially entered is two or greater];
wherein each of the one or more extended sleep modes has a lower power usage than the lowest power usage sleep mode (“the LPM state 64 may be lower power than the sleep 3 state 56, and the off state 58 may be the lowest power state.” Par 0058) [LPM state (extended sleep mode) has lower power usage than the lower power usage sleep mode of the other set (sleep 3 state 56)].
However, Rachakonda does not explicitly teach determine whether to enter one or more extended sleep modes, from a lowest power usage sleep mode of the number of sleep modes, based on detection of an extended sleep mode signal in the sequence of image data; and return to the normal operation mode in a reverse order with respect to an order in which the two or more sleep modes and the one or more extended sleep modes were entered.
In the analogous art, Kim teaches determine whether to enter one or more extended sleep modes, from a lowest power usage sleep mode of the number of sleep modes, based on detection of an extended sleep mode signal in the sequence of image data (“The deep sleep mode and the normal power down mode may be set through specific bits of the command/address signal CA<0:N>.” par 0071) [this shows hierarchy of sleep states; entry into the extended mode (deep sleep) from a base (normal power down) is controlled by specific signal bits]; and
return to the normal operation mode in a reverse order with respect to an order in which the two or more sleep modes and the one or more extended sleep modes were entered (“When the chip select signal CS is toggled in a state where the semiconductor apparatus 100 has entered the deep sleep mode, the power control signal generation circuit 220 may recognize a deep sleep mode exit command DSX, ” par 0077 and “While the semiconductor apparatus 100 operates in the normal power down mode, the processor 30 may toggle the chip select signal CS to command the semiconductor apparatus 100 to exit from the normal power down mode.” Par 0076 and paragraphs 75-78) [this is a sequential wakeup process where the system first transitions from a deep sleep mode to a normal power mode before it can exit to normal operation (reverse order)].
It would have been obvious to a person having ordinary skill in the art, having the teachings of Rachakonda and Kim before him before the effective filing date of the claimed invention, to have modified Rachakonda to incorporate the teachings of Kim to enter the appropriate sleep mode based on the control signals in the image data and ensure appropriate power conservation.
Regarding claim 2, Rachakonda and Kim teach the apparatus of claim 1. Kim further teaches wherein the one or more extended sleep modes include a powered down mode and a clocks down mode that has a lower power usage than the powered down mode, wherein the extended sleep mode signal is a control signal to power down the controller or to power down clocks (“The power down mode may include a normal power down mode and a deep sleep mode (or deep power down mode)…The portable electronic device employs a power gating technique for preventing unnecessary power supply to function blocks in the power down mode.” Col. 1, ll. 34-44 and “The deep sleep mode needs to guarantee a longer power down interval than the normal power down mode.” Col. 1, ll. 36-37 and “The power control circuit 200 may recognize an entry into the deep sleep mode according to the chip select signal CS and the command/address signal CA<0:N>.” col. 4, ll. 59-61) [the longer power down interval corresponds to lower average power consumption; the normal power down mode corresponds to the powered down mode and the deep sleep mode involved additional power saving including controlling the oscillator, which corresponds to the clocks down mode with lower power usage], and wherein the controller is further configured to:
enter the powered down mode by switching off drivers or circuits of the controller if the control signal to power down is detected in the sequence of image data; and enter the clocks down mode by switching off clocks of the controller if the control signal to power down clocks is detected in the sequence of image data (“The deep sleep mode and the normal power down mode may be set through specific bits of the command/address signal CA<0:N>.” col. 5, ll. 20-22 and “The portable electronic device employs a power gating technique for preventing unnecessary power supply to function blocks in the power down mode.” Col. 1, ll. 37-40 and “Since the detection signal PP_DET is at a low level, the oscillator 250 may not operate.” Col. 8, ll. 25-26) [the command/address signal corresponds to the control signal; the semiconductor apparatus corresponds to the controller in this case; the oscillator is a clock source, which maps to switching off clocks of the controller; the power gating technique stops supply power to the logic gates, which maps to switching off drivers/ circuits (as they are comprises of logic gates and function blocks; under BRI, the command /address signal would be part of the input stream processed by the controller].
Regarding claim 6, Rachakonda and Kim teach the apparatus of claim 1. Rachakonda further teaches wherein the controller is further configured to sequentially enter the number of sleep modes and the one or more extended sleep mode based on a time to cycle down from the normal operation mode to the deepest extended sleep mode, of the one or more extended sleep modes, and cycle up from the deepest extended sleep mode to the normal operation mode (“the display controller 34 may detect a sleep state for the display controller 34 responsive to the delay to the next frame being large enough to make transition to a lower power state worthwhile (e.g. the power saved will outweigh power expending to shut down the display controller 34, power the display controller 34 back up again, and restore state to the display controller 34).” Par 0056 and “The threshold may be selected based on a variety of factors, including the display controller wake latency. That is, if the next frame time is not greater than the display controller wake latency, the display controller 34 may not actually power down.” Par 0065 and “The always-on component 16 may detect that the memory-only communication mode is to be restored, transitioning the state machine back to the sleep 2 state 54 (“mem wake” arc in FIG. 2). Similarly, the always-on component 16 may detect that the display controller 34 is to wake up, transition the state machine back to the sleep 1 state 52 (“disp wake” arc in FIG. 2). As with the above discussion, the state machine may support direct transitions between the sleep 3 state 56 and the sleep 1 state 52 and/or the awake state 50” Par 0057 and Figures 2-3) [this shows entering and exiting multiple sleep levels (sleep 3 being the deepest extended mode) by comparing the idle time to specific threshold and wake latencies required to cycle the system down/up].
Regarding claim 8, Rachakonda and Kim teach the apparatus of claim 1. Kim further teaches wherein the one or more extended sleep modes are programmable for different power usage based on configurable of parameters for enabling and disabling clocks, buffers, drivers, or circuits of the controller, the light modulator, or the interface (“The power down mode may include a normal power down mode and a deep sleep mode (or deep power down mode) … The portable electronic device employs a power gating technique for preventing unnecessary power supply to function blocks in the power down mode.” Col. 1, ll. 34-44 and “The deep sleep mode and the normal power down mode may be set through specific bits of the command/address signal CA<0:N>.” col. 5, ll. 20-22 and “Since the detection signal PP_DET is at a low level, the oscillator 250 may not operate. Thus, the level of the pumping voltage VPP may become lower than the first level.” Col. 8, ll. 25-27 and Figure 5) [this describes parameter levels (signals in Figure 5) for the oscillator and other components of the system].
Claims 3 and 4 are rejected under 35 U.S.C. 103 as being unpatentable over Rachakonda and Kim in view of Keppel et al. (US 2014/0189401 A1).
Regarding claim 3, Rachakonda and Kim teach the apparatus of claim 1. Rachakonda further teaches wherein the controller is further configured to:
enter the light sleep mode by switching off first clocks of the interface between the controller and the light modulator (“A component may also be inactive if it is clock gated. Clock gating may refer to techniques in which the clock to the digital circuitry in the component is temporarily “turned off,” preventing state from being captured from the digital circuitry in clocked storage devices such as flops, registers, etc.” par 0042) [clock gating is defined as switching off the clock to make a component inactive, which corresponds to light sleep mode].
Kim further teaches wherein the controller is further configured to:
enter the medium sleep mode by switching off first data buffers and associated second clocks for receiving the display image data at the light modulator (“The plurality of logic circuit blocks 510 may perform a power gating operation which stops supplying power supply to one or more of the logic gates” col. 4, ll. 45-47) [the peripheral circuit handles the input data including receiving image data in the context of a display system; the logic gates no longer have a power supply corresponding to a medium sleep mode]; and
enter the deep sleep mode by switching off second data buffers and associated third clocks at the controller (“the oscillator 250 may not operate.” Col. 8, ll. 26 and “power supply to the logic circuit blocks 510 may be removed.” Col. 7, ll. 53-54) [in deep sleep, the semiconductor apparatus (acting as the controller) stops the oscillator (a clock) and removes power supply from logic circuit blocks].
However, Rachakonda and Kim do not explicitly teach wherein the one or more sleep modes include a light sleep mode, a medium sleep mode that has a lower power usage than the light sleep mode, and a deep sleep mode that has lower power usage than the medium sleep mode.
In the analogous art, Keppel teaches wherein the one or more sleep modes include a light sleep mode, a medium sleep mode that has a lower power usage than the light sleep mode, and a deep sleep mode that has lower power usage than the medium sleep mode (“the sleep logic 130 may provide a “shallow” sleep mode, … the sleep logic 130 may provide a “deep” sleep mode, meaning a sleep mode which has a relatively high level of power savings, but which maintains a relatively low level of functionality, or which may require a relatively long time to restore full functionality. In some embodiments, the sleep logic 130 may also provide additional sleep modes having levels of functionality and/or power savings between those of the shallow sleep mode and the deep sleep mode (e.g., a “medium” sleep mode, a “medium-shallow” sleep mode, a “medium-deep” sleep mode, etc.).” par 0015).
It would have been obvious to a person having ordinary skill in the art, having the teachings of Rachakonda, Kim and Keppel before him before the effective filing date of the claimed invention, to have modified Rachakonda and Kim to incorporate the teachings of Keppel to include a tiered sleep modes in the apparatus, where each sleep mode has a lower power usage than the previous one, to allow various functional blocks to independently transition to different sleep modes without requiring system-wide power changes, enabling efficient power management.
Regarding claim 4, Rachakonda, Kim and Keppel teach the apparatus of claim 3. Keppel further teaches wherein the controller is further configured to wait in the deep sleep mode an amount of time based on the sequence of image data (“In one or more embodiments, the sleep logic 130 may include functionality to perform sleep transitions based on the stored transition programs. Specifically, in some embodiments, the sleep logic 130 may monitor any parameters or inputs specified in conditions of the transition programs, and may thus determine if a sleep transition is required. For example, the sleep logic 130 may monitor system events, voltage levels, bus signals, user inputs, network events, clocks/timers, etc.” par 0028) [the sleep logic (controller) monitors parameters, including bus signals (which in the context of a display system, carry image data].
Claims 5 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Rachakonda and Kim in view of Lo et al. (US 9,406,269 B2).
Regarding claim 5, Rachakonda and Kim teach the apparatus of claim 1. However, Rachakonda and Kim do not explicitly teach wherein the sequence of image data is a sequence of data that represents a frame to be displayed by the light modulator, and wherein the sequence of data includes one or more gaps in the data.
In the analogous art, Lo teaches wherein the sequence of image data is a sequence of data that represents a frame to be displayed by the light modulator, and wherein the sequence of data includes one or more gaps in the data (“The writing of data in the sequential manner of FIG. 15B is a repeating loop. In some instances there may short stalls initiated to permit the transition from one image data source to another but the display may continue operating in this fashion for hours or days.” Col. 26, ll. 19-23) [the short stall in sequential writing of the image data may correspond to gaps/interruptions in the flow of the display sequence].
It would have been obvious to a person having ordinary skill in the art, having the teachings of Rachakonda, Kim and Lo before him before the effective filing date of the claimed invention, to have modified Rachakonda and Kim to incorporate the teachings of Lo to include gaps in the display sequence data to ensure effective control of image data transmission, specifically for display systems with pulse width modulation and scrolling color, as it allows the display to transmit synchronization signals to synchronize with the signal source, preventing image distortion.
Regarding claim 7, Rachakonda and Kim teach the apparatus of claim 1. However, Rachakonda and Kim do not explicitly teach wherein the one or more gaps are produced by data compression in the sequence of data.
In the analogous art, Lo teaches wherein the one or more gaps are produced by data compression in the sequence of data (“there may short stalls initiated to permit the transition from one image data source to another” col. 26, ll. 20-21 and “the limiting bandwidth for writing data to the display device. The limiting bandwidth may occur in a controller at its interface to external memory, between the display controller and its display, or within the controller. The interface between the display controller and its external memory is often the bandwidth limiter” col. 14, ll. 41-46) [the bandwidth constraints are a factor in the data sequence, which is corresponds to data compression].
It would have been obvious to a person having ordinary skill in the art, having the teachings of Rachakonda, Kim and Lo before him before the effective filing date of the claimed invention, to have modified Rachakonda and Kim to incorporate the teachings of Lo because Rachakonda and Kim do not teach how the gaps in the data sequence are produced. Lo further explains what parameters are involved in the data sequence, such as the bandwidth constraints, which illustrates how the gaps in the sequence are produced.
Claims 9-11, 15 are rejected under 35 U.S.C. 103 as being unpatentable over Chow et al. (US 2024/0114150 A1) in view of Moon (US 2015/0009200 A1).
Regarding claim 9, Chow teaches a method comprising:
obtaining, by a controller from a processor, a sequence of image data to be displayed by a light modulator (“video rendered by a processor is provided to a display system in a stream of frames and displayed by a screen of the display system.” par 0010 and Figure 1);
predicting one or more gaps in the display image data and a time length of each gap based on a pattern of the sequence of image data (“The processing system can utilize these gaps in display processing during vertical blanking regions “ par 0011 and “based on one or more of the video playback information 310 or the display device information 312, the low-power mode controller 308 identifies/detects … when the vertical active region of a frame begins and ends.” Par 0032 and paragraph 10, 31) [the controller calculates the timing and duration of blanking gaps based on video’s pattern (Htotal, Vtotal, etc.) to schedule power transitions];
entering, based on the prediction, a number of sleep modes, of a set of sleep modes, in an order from higher to lower power usage, wherein the number of sleep modes entered is an integer of two or greater (“The low-power mode controller 308 … uses information, such as video playback information 310 and display device information 312, to determine whether to enable/disable the low-power management mode” par 0031 and “The idle and power-gated states can be referred to as sleep or low-power states, and multiple levels of low-power states can be implemented by a processing system. … while in the lowest (shallowest) power savings level of a low-power state, a component of a processing system consumes less power than when operating in the active state but consumes more power than the next higher (deeper) power savings level of a low-power state.” Par 0009 and paragraph 32) [the controller uses video frame pattern to detect gaps (active region ends), triggering the system to enter two or more hierarchical sleep modes that transition for shallow to deep states]; and
powering up including exiting the clocks down mode, entering the power down mode, exiting the power down mode, and continuing to enter and exit the number of sleep modes previously entered in a reverse order with respect to an order in which they were entered (“The power controller 132 … is also preconfigured with information identifying the sequence to place multiple components in the low-power state… the low-power mode controller 308 can inform the power controller 132 of which components to place in the low -power state and in what sequence.” Par 0032 and “the power controller 132 to transition each component out of the low-power state either at the same time or in a programmable sequence.” Par 0037 and “transitions any remaining components out of the low-power state that were not transitioned out of the low-power state” par 0043 and “the display processing device transitions the one or more components out of the low-power state and back into an active power state. Despite continuously powering multiple components on and off every frame, the display processing device is able to maintain continuous frame synchronization” par 0012 and Figures 5-7) [the programmable sequence describes the reverse traversal where the system exits lowest state, enters and exists intermediate states (power down) and returns to active mode, which repeats every frame].
However, Chow does not explicitly teach entering, based on whether in response to the sequence of image data includes including a first control signal to power down, a powered down mode after entering a lowest power usage sleep mode, of the number of sleep modes, wherein the powered down mode has a lower power usage than the lowest power usage sleep mode; entering, based on whether in response to the sequence of image data includes including a second control signal to power down clocks, a clocks down mode after entering the powered down mode, wherein the clocks down mode has a lower power usage than the powered down mode.
In the analogous art, Moon teaches entering, based on whether in response to the sequence of image data includes including a first control signal to power down, a powered down mode after entering a lowest power usage sleep mode, of the number of sleep modes, wherein the powered down mode has a lower power usage than the lowest power usage sleep mode (“When the sleep mode 400 is maintained … a clock-off mode command is inputted, the CPU 51 … enter the clock-off mode 500.” Par 0054 and Figure 11) [the clock-off mode command corresponds to first control signal, transitioning to clock off mode (powered down mode) after system already entered sleep mode, see Figure 11];
entering, based on whether in response to the sequence of image data includes including a second control signal to power down clocks, a clocks down mode after entering the powered down mode, wherein the clocks down mode has a lower power usage than the powered down mode (“When the clock-off mode 500 is maintained … a deep sleep mode command [second control signal] is received, the CPU 51 enters the deep sleep mode 600.” Par 0056 and Figures 6 and 11) [deep sleep mode corresponds to clocks down mode when both data and clock voltages are zero, lower than the clock-off mode].
It would have been obvious to a person having ordinary skill in the art, having the teachings of Chow and Moon before him before the effective filing date of the claimed invention, to have modified Chow to incorporate the teachings of Moon to include a clocks down and powered down mode to minimize power consumption in a sleep mode by efficiently managing the clock signal. (Moon, paragraphs 11, 16, 55)
Regarding claim 10, Chow and Moon teach the method of claim 9. Moon further teaches wherein:
entering the powered down mode includes switching off drivers or circuits of the controller (“voltage levels of the clock signal and the data is become 0 V, which may reduce power consumption of the set controller 50 and a driver IC (gate driver 20, data driver 30, and/or signal controller 40).” Par 0047 and “the oscillator 53 and the PLL are turned off … it is possible to minimize the power consumption of the oscillator 53 by deactivating the oscillator 53.” Par 0055) [entering the clock off mode (powered down mode) turns off the oscillator/PLL (drivers/circuits), setting voltages to 0V]; and
entering the clocks down mode includes switching off multiple clocks of the controller or by both switching off the clocks and shutting down multiple functions of the controller (“the oscillator 53 and the PLL are turned off … it is possible to minimize the power consumption of the oscillator 53 by deactivating the oscillator 53.” Par 0055 and Figure 6) [the oscillator and PLL (multiple clocks) are turned off in the clocks off mode].
Regarding claim 11, Chow and Moon teach the method of claim 10. Moon further teaches further comprising:
before entering the clocks down mode, waiting in the powered down mode a first amount of time based on the sequence of image data (“The CPU 51 proceeds to operation S60 when the clock-off mode time period (measured from when the clock-off mode is started) exceeds a second reference time period M.” par 0065 and Figure 11 and claim 2) [the system waits in the clocks down mode for a duration before entering deep sleep mode; these transitions occur within gaps of the video frame sequence]; and
waiting in the clocks down mode a second amount of time based on the sequence of image data or until detecting a signal indicating a next sequence of image data to be displayed (“The CPU 51 enters the deep sleep mode 600 when the sleep mode time period measured in the counter 54 exceeds the second reference time period, or no user event is inputted for the second reference time period, and maintains the deep sleep mode 600 when the sleep mode time period is equal to or smaller than the second reference time period.” Par 0060 and “the CPU 51 returns to the normal driving mode 300 when the user event is generated or the wake-up source is changed in the deep sleep mode 600.” Par 0057 and Figure 6) [the system waits in the deep sleep mode for a duration of the second reference time period to return to normal driving mode for next image sequence].
Regarding claim 15, Chow and Moon teach the method of claim 9, Chow further teaches wherein powering up includes remaining in the powered down mode for a length of time before entering the lowest power usage sleep mode (“the second trigger value 324-2 is configured to correspond to frame line or a duration of time subsequent to the frame line or duration of time corresponding to the first trigger value 324-1.” Par 0040 and “the power controller 132 to transition each component out of the low-power state either at the same time or in a programmable sequence.” Par 0037 and “transitions any remaining components out of the low-power state that were not transitioned out of the low-power state” par 0043) [components are reactivated in stages at specific events/triggers, requiring the system to remain in an intermediate state for a designated duration of time before transitioning into next mode].
Claims 12 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Chow and Moon in view of Kim.
Regarding claim 12, Chow and Moon teach the method of claim 10. However, Chow and Moon do not explicitly teach exiting the clocks down mode by restarting the clocks of the controller based on whether a third control signal to power up clocks is detected in the sequence of image data; and exiting the powered down mode by switching the drivers or circuits to standby based on whether a fourth control signal to power up is detected in the sequence of image data.
In the analogous art, Kim teaches the method further comprising:
exiting the clocks down mode by restarting the clocks of the controller based on whether a third control signal to power up clocks is detected in the sequence of image data (“the deep sleep mode exit command DSX, operate the semiconductor apparatus 100 in the normal power down mode, retain the power gating control signal PDE at a high level, and change the voltage control signal RPC to a low level.” Col. 8, ll. 10-14 and “Since the detection signal PP_DET is at a high level, the oscillator 250 may operate.” Col. 8, ll. 25-26); and
exiting the powered down mode by switching the drivers or circuits to standby based on whether a fourth control signal to power up is detected in the sequence of image data (“the normal power down mode exit command PDX, change the power gating control signal PDE to a low level, and retain the voltage control signal RPC at a low level. Since the power gating control signal PDE is at a low level, power supply to the logic circuit blocks 510 may be normally performed.” Col. 8, ll. 8, ll. 37-43).
It would have been obvious to a person having ordinary skill in the art, having the teachings of Chow, Moon and Kim before him before the effective filing date of the claimed invention, to have modified Chow and Moon to incorporate the teachings of Kim to determine to enter a clocks down mode to reduce the power consumption of the semiconductor apparatus. Entering this sleep mode, as taught in Kim, based on a delay in the display frames as taught in Chow will ensure that the components of the apparatus are only using the exact amount of power required. This also ensures both the memory and display components are managing power efficiently.
Regarding claim 13, Chow, Moon and Kim teach the method of claim 12. Chow further teaches further comprising before exiting the clocks down mode, waiting an amount of time based on the sequence of image data (“at a programmable duration of time before the start of the vertical active region of the next frame, the display processing device transitions the one or more components out of the low-power state” par 0012 and “At block 624, the counter controller 304 determines if the current counter value 322 corresponds to the first trigger value 324-1… which indicates that a specified number of lines 514 (or a specified amount of time) prior to the start of the active region 504 of a second video frame have occurred,” Par 0042).
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Chow, Moon and Kim in view of Keppel et al. (US 2014/0189401 A1).
Regarding claim 14, Chow, Moon and Kim teach the method of claim 12. However, Chow, Moon and Kim do not explicitly teach wherein the first control signal to power down indicates a start of an inactive display driver transmission segment in the sequence of image data, wherein the fourth control signal to power up indicates an end of the inactive display driver transmission segment, wherein the second control signal to power down clocks indicates a start of an image processing off period, and wherein the third control signal to power up clocks indicates an end of the image processing off period.
In the analogous art, Keppel teaches wherein the first control signal to power down indicates a start of an inactive display driver transmission segment in the sequence of image data (“For example, referring to FIG. 1A, the sleep logic 130 in each of the sleep blocks 120A-120N may monitor parameters associated with sleep transitions. Such parameters may include, e.g., a system event, a voltage level, a timing value, a user command, a digital signal, etc.” par 0048 and Figure 2a, ST1, ST3, ST5) [these parameters indicate an inactive segment], wherein the fourth control signal to power up indicates an end of the inactive display driver transmission segment (Figure 2a, sleep transition ST2, ST6 are transitions to awake mode; these transition occur when the parameters indicate end of an inactive segment), wherein the second control signal to power down clocks indicates a start of an image processing off period (Figure 2a, sleep transition ST3 and ST5 are transitions to deep sleep mode; these transitions occur when the parameters indicate start of image processing off segment), and wherein the third control signal to power up clocks indicates an end of the image processing off period (Figure 2a, sleep transition ST4 and ST2 are transitions to shallow sleep mode and then awake mode; these transitions occur when the parameters indicate end of image processing off segment).
It would have been obvious to a person having ordinary skill in the art, having the teachings of Chow, Moon, Kim and Keppel before him before the effective filing date of the claimed invention, to have modified Chow, Moon and Kim to incorporate the teachings of Keppel to include a tiered sleep modes in the apparatus and use the gap length to determine which power mode to enter, where each sleep mode has a lower power usage than the previous one, to allow various functional blocks to independently transition to different sleep modes without requiring system-wide power changes, enabling efficient power management.
Allowable Subject Matter
Claims 16-20 are allowed.
Response to Arguments
Applicant’s arguments, see pages 9-10, filed 09/15/2025, with respect to the rejection(s) of claim(s) 1, 9 and 16 under 35 U.S.C. 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. Claim 16 is allowed. However, upon further consideration, a new ground(s) of rejection is made in view of Rachakonda in view of Kim for claim 1. Kim teaches entering an extended sleep mode (deep) after a normal power down mode and teaches returning to normal operation in a reverse order with respect to an order in which the modes were entered. Examiner points to the updated mappings of claims 1.
Applicant’s arguments with respect to claim 9 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
No additional arguments were presented as to the remaining claims. As such, the rejection is maintained.
Conclusion
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/AYMAN FATIMA/Examiner, Art Unit 2176
/JAWEED A ABBASZADEH/Supervisory Patent Examiner, Art Unit 2176
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