DETAILED ACTION
Claim Rejections - 35 USC § 102
1. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
2. Claim(s) 1 – 5, 7 – 9, 11, 13, 17 - 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Matsuura (20130288401).
With regard to claim 1, Matsuura discloses a semiconductor device (for example, see fig. 2D or 3D), comprising:
a substrate (10) having a frontside (a top side) and a backside (a bottom side) opposite to each other;
a semiconductor layer (18) disposed on the frontside of the substrate (10);
a source electrode (22) disposed on the semiconductor layer (18);
a first metal layer (60) disposed on the source electrode (22);
an opening (referred to as “60A” by examiner’s annotation shown in fig. 3D below); wherein the opening 60A forming in a top surface of the first metal layer 60, wherein the opening (60A) is configured directly above the source electrode (22), and completely overlaps with the first metal layer (60) and the source electrode (22) in a top view (a cross-sectional view including a top view);
a backside via hole (64 as shown in fig. 3D below, or fig. 3C) extending from the backside of the substrate (10) to a bottom surface of the first metal layer (60), wherein the backside via hole (64) is laterally separated from the source electrode (22) by a non-zero distance; and
a backside metal layer (56; or 59) disposed on the backside of the substrate (10) and extending to cover a surface of the backside via hole (64);
a wire bonding (an interconnection line 36, is directly bonding to the metal layer 60, functions as a wire bonding. Although the applicant uses terms different to those of Matsuura to label/describe the claimed invention, this does not result in any structural difference between the claimed invention and the prior art. The use different terminology to describe the plurality of elements that constitute an integrated circuit as this is just a writing style and the way in which a structural limitation is expressed does not affect the configuration of the described elements.) is applied on the first metal layer (60) through the opening (60A).
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With regard to claim 2, Matsuura discloses the backside via hole (64) is physically separated from the source electrode (64) by a dielectric material (referred to as “32A” by examiner’s annotation shown in fig. 3D below; wherein the dielectric layer 32A is a portion of the protection layer 32).
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With regard to claim 3, Matsuura discloses the backside via hole (64) penetrates through the substrate (10), the semiconductor layer (18), and the dielectric material (32A) to contact the first metal layer (60).
With regard to claim 4, Matsuura discloses the backside metal layer (56) inherently conformally covers the surface of the backside via hole (64) to form a hollow space (opening) in the backside via hole (64).
With regard to claim 5, Matsuura discloses a filling material (a material of the layer 58 functioning as a filling material) partially filled into the hollow space (the opening of the via hole 64), so that the backside metal layer (56) wraps the filling material (at least a portion of the layer 58 forming in the via hole 64).
With regard to claim 7, Matsuura discloses the filling material (the material of the layer 58 functioning as the filling material) comprises a metal material.
With regard to claim 9, Matsuura discloses the filling material (58) has a bottom surface (referred to as “58A” by examiner’s annotation shown in fig. 3D below) higher than a lowest bottom surface (referred to as “56A” by examiner’s annotation shown in fig. 3D below) of the backside metal layer (56).
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With regard to claim 11, Matsuura discloses a top view shape of the backside via hole (64) having an inner diameter (for example, see paragraph [0029]), and inherently having a circle shape (because the circle shape having a diameter).
With regard to claim 13, Matsuura discloses a drain electrode (20) disposed on the semiconductor layer (18); and a gate electrode (28) disposed on the semiconductor layer (18) between the source electrode (22) and the drain electrode (20), wherein the source electrode (22), the gate electrode (28), and the drain electrode (20) are covered by a dielectric material (referred to as “32B” by examiner’s annotation shown in fig. 3D below) and physically separated from each other by the dielectric material (32B).
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With regard to claim 14, Matsuura discloses a second metal layer (34) disposed on (on the side or top) the first metal layer (60); and an air bridge (referred to as “38A” by examiner’s annotation shown in fig. 3D below) embedded between the first metal layer (60) and the second metal layer (34).
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With regard to claim 17, Matsuura discloses the source electrode (22) completely overlaps with the first metal layer (60) in a top view.
With regard to claim 18, Matsuura discloses the source electrode (22) does not overlap with the backside via hole (64) in a top view (a cross-sectional view including a top view).
With regard to claim 19, Matsuura discloses the backside metal layer (56, 58) comprises a sputtered layer (the metal layer 56 made by sputtering and functioning as a sputtered layer; for example, see paragraph [0048]) and an electroplating layer (a metal layer 58 made by electrolytic plating, functioning as an electroplating layer; for example, see paragraph [0048]) overlying the sputtered layer (56).
With regard to claim 20, Matsuura discloses the semiconductor layer (18) is a GaN layer (for example, see paragraph [0062]), Applicant’s claim 20 does not distinguish over Matsuura references regardless of the process used to form the semiconductor layer because only the final product is relevant, not the process of making such as “epitaxial”.
Note that a "product by process" claim is directed to the product per se, no matter how actually made, In re Hirao, 190 USPQ 15 at 17 (footnote 3). See also In re Brown, 173 USPQ 685; In re Luck, 177 USPQ 523; In re Wertheim, 191 USPQ 90 (209 USPQ 554 does not deal with this issue); In re Fitzgerald, 205 USPQ 594, 596 (CCPA); In re Marosi et al., 218 USPQ 289 (CAFC); and most recently, In re Thorpe et al., 227 USPQ 964 (CAFC, 1985) all of which make it clear that it is the final product per se which must be determined in a "product by process" claim, and not the patentability of the process, and that, as here, an old or obvious product produced by a new method is not patentable as a product, whether claimed in "product by process" claims or not. Note that Applicant has burden of proof in such cases, as the above case law makes clear.
With regard to claim 8, Matsuura discloses a semiconductor device (for example, see fig. 2D or 3D), comprising:
a substrate (10) having a frontside (a top side) and a backside (a bottom side) opposite to each other;
a semiconductor layer (18) disposed on the frontside of the substrate (10);
a source electrode (22) disposed on the semiconductor layer (18);
a first metal layer (60) disposed on the source electrode (22);
an opening (referred to as “60A” by examiner’s annotation shown in fig. 3D below); wherein the opening 60A forming in a top surface of the first metal layer 60, wherein the opening (60A) is configured directly above the source electrode (22), and completely overlaps with the first metal layer (60) and the source electrode (22) in a top view (a cross-sectional view including a top view);
wherein the opening (60A) completely overlaps with the first metal layer (60) and the source electrode (22) in a top view (a cross-sectional view including a top view);
a backside via hole (64 as shown in fig. 3D below, or fig. 3C) extending from the backside of the substrate (10) to a bottom surface of the first metal layer (60), wherein the backside via hole (64) is laterally separated from the source electrode (22) by a non-zero distance; and
a backside metal layer (referred to as “58A” by examiner’s annotation shown in fig. 3D below; wherein the backside metal layer 58A is a portion of the layer 58) disposed on the backside of the substrate (10) and extending to partially cover a surface of the backside via hole (64).
the backside metal layer (58A) inherently conformally covers the surface of the backside via hole (64) to form a hollow space (opening) in the backside via hole (64);
a filling material (referred to as “58B” by examiner’s annotation shown in fig. 3D below; wherein the backside metal layer 58B is a portion of the layer 58) partially filled into the hollow space (the opening of the via hole 64), so that the backside metal layer (58A) wraps the filling material (58B);
wherein the filling material (58B) and the backside metal layer(58A) have a same material (the same layer 58 having the same material);
a wire bonding (an interconnection line 36, is directly bonding to the metal layer 60, functions as a wire bonding. Although the applicant uses terms different to those of Matsuura to label/describe the claimed invention, this does not result in any structural difference between the claimed invention and the prior art. The use different terminology to describe the plurality of elements that constitute an integrated circuit as this is just a writing style and the way in which a structural limitation is expressed does not affect the configuration of the described elements.) is applied on the first metal layer (60) through the opening (60A).
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Claim Rejections - 35 USC § 103
3. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
4. Claims 6, 10 are rejected under 35 U.S.C. 103 as being unpatentable over Matsuura (20130288401) in view of Palacios (20150270356).
With regard to claims 6, 10, Matsuura does not clearly disclose the filling material comprises an insulating material wherein the filling material has a bottom surface substantially level with a lowest bottom surface of the backside metal layer.
However, Palacios discloses the filling material (5) comprises an insulating material (the fill region 5 may be insulating; for example, see paragraph [0040]) wherein the filling material (5) has a bottom surface substantially level with a lowest bottom surface of the backside metal layer (4). (for example, paragraph [0039], see fig. 7).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the Matsuura’s device to have the filling material comprises an insulating material wherein the filling material has a bottom surface substantially level with a lowest bottom surface of the backside metal layer as taught by Palacios in order to minimize the signal interference for enhancing a stability operation of the semiconductor device, as is known to one of ordinary skill in the art.
5. Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Matsuura (20130288401).
With regard to claim 12, Matsuura discloses a diameter of the backside via hole is between 30 μm and 60 μm (the first opening 52, fig. 2B may have an inner diameter of, for example, tens of microns to hundreds of microns and overlapping the range of 30 μm and 60 μm), and a height of the backside via hole is between 50 μm and 200 μm (the thickness of the substrate 10 is 200 μm wherein the via hole forming in the substrate 10; for example, see paragraph [0029]), but does not clearly disclose a diameter of the backside via hole is between 30 μm and 60 μm. However, it would have been obvious to one having ordinary skill in the art at the time the invention was made to have a diameter of the backside via hole is between 30 μm and 60 μm because a prima facie case of obviousness exists where the claimed ranges and prior art ranges overlap that one skilled in the art would have expected them to have the same properties. Moreover, the Federal Circuit informs us that a prima facie case of obviousness typically exists when the ranges of a claimed composition overlap the ranges disclosed in the prior art. In re Peterson, 65 USPQ2d 1379, 1382 (Fed. Cir 2003) citing In re Geisler, 116 F.3d 1465, 1469, 43 USPQ2d 1362, 1365 (Fed. Cir. 1997); In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936-37 (CCPA 1976); and In re Malagari, 499 F.2d 1297, 1303, 182 USPQ 549, 553 (CCPA 1974). See MPEP § 2144.05.
It is well understood that obviousness based upon a combination of elements requires a suggestion, motivation or teaching to those skilled in the art for such a combination. In re Fine, 5 USPQ2d 1596 (Fed. Cir. 1988). This requirement prevents the use of “the inventor’s disclosure as a blueprint for piecing together the prior art to defeat patentability—the essence of hindsight.” Ecolochem, Inc. v. So. Cal. Edison Co., 56 USPQ2d 1065 (Fed. Cir. 2000) (quoting In re Dembiczak, 50 USPQ2d 1614 (Fed. Cir. 1999)). However, as the Federal Circuit points out in Iron Grip Barbell Co. v. USA Sports Inc., when the difference between the claimed invention and the prior art rests only in the fact that applicants claim a narrower range than that found in the prior art, the case for obviousness does not rest on combining elements, and evidence of motivation/suggestion is not required to avoid using hindsight. Iron Grip Barbell Co. v. USA Sports Inc., 73 USPQ2d 1225, 1227 (Fed. Cir 2004). Iron Grip also teaches us that whether the prior art range is found in one, two, or many references is “a distinction without a difference.” Id at 1228. See also MPEP § 2144.05.
7. Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Matsuura (20130288401) in view of Tadepalli (20220216309).
With regard to claim 15, Matsuura does not clearly disclose the first layer is configured to be used as a chip probe test pad.
However, Tadepalli discloses the first layer (228) is functioning as a chip probe test pad. (for example, see paragraph [0024], fig. 1).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the Matsuura’s device to have the first layer is configured to be used as a chip probe test pad as taught by Tadepalli in order to enhance improve testability for enhancing a stability operation of the semiconductor device, as is known to one of ordinary skill in the art.
8. Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Matsuura (20130288401) in view of Yamaki (8592825).
With regard to claim 16, Matsuura discloses the wire bonding (36) to a top surface of the metal layer (60), but Matsuura does not clearly disclose the backside via hole is laterally offset from the wire, so that the backside via hole does not overlap with the wire in a top view.
However, Yamaki discloses the backside via hole (V) is laterally offset from the wire (30), so that the backside via hole (V) does not overlap with the wire (30) in a top view (a cross-sectional view including a top view).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the Matsuura’s device to have the backside via hole is laterally offset from the wire, so that the backside via hole does not overlap with the wire in a top view as taught by Yamaki in order to enhance a high electrical connection efficiency of the semiconductor device for enhancing a stability operation of the semiconductor device, as is known to one of ordinary skill in the art.
Response to Amendment
9. Applicant's arguments with respect to claims have been considered but are moot in view of the new ground(s) of rejection.
Conclusion
10. Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
11. Any inquiry concerning this communication or earlier communications from the examiner should be directed to TAN N TRAN whose telephone number is (571) 272 - 1923. The examiner can normally be reached on 8:30-5:00PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached on (571) 272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/TAN N TRAN/
Primary Examiner, Art Unit 2812
