DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on February 3, 2023 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Drawings
The drawings received on February 3, 2023 are acceptable.
Claim Objections
Claim 12 is objected to because of the following informalities. Appropriate correction is required.
It appears that “a protected chip” in line 4 should be “the chip.”
It appears that “a protected circuit” in line 4 should be “the protected circuit.”
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1 and 12 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Sugahara (US 7933107 B2).
Regarding claims 1 and 12, Sugahara teaches a chip comprising a protected circuit and an electro-static protection circuit, wherein the electro-static protection circuit comprises: an electro-static protection circuit (11 and 12A in Fig. 3; para. (21) of Description), wherein the electro-static protection circuit is located inside a protected chip (para. (11)-(12) of Background/Summary) and connected with a protected circuit (para. (8) of Background/Summary; based on the function of an electro-static protection circuit, it is implicit that an electro-static protection circuit is connected with a protected circuit, otherwise it would not be offering protection); and a control circuit (13 in Fig. 3; para. (24) of Description), wherein the control circuit is connected with the electro-static protection circuit (Fig. 3), the control circuit is configured to output, when static electricity is generated on the protected chip, a high-level signal to the electro-static protection circuit to trigger the electro-static protection circuit to discharge an electro-static current (para. (14), (25)-(26) of Description), and output, when the static electricity is not generated on the protected chip, a low-level signal to the electro-static protection circuit to reduce a static leakage current of the electro-static protection circuit (Fig. 3; since the circuit of Fig. 3 turns on the electro-static protection circuit during an ESD event to start a discharge operation, it is implicit that this circuit turns the circuit off during normal operation, no longer applying voltage to the diode string and reducing leakage).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-5, 7-11, 15-18, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Sugahara (US 7933107 B2) in view of Sato (US 2005/0212009 A1).
Regarding claims 2 and 15, Sugahara discloses wherein the electro-static protection circuit comprises: a silicon-controlled rectifier (22 in Fig. 3; para. (21) of Description), provided with an anode (A in Fig. 3), a cathode (K in Fig. 3) and a trigger end (G1 in Fig. 3), and a diode string, wherein the diode string comprises a plurality of diodes connected in series (270 in Fig. 3; para. (23) of Description), an anode of the diode string is connected with the trigger end of the silicon-controlled rectifier (Fig. 3; para. (23) of Description: “An anode of the diode circuit 270 is connected to the first gate G1 of the SCR 22.”), and a cathode of the diode string is connected with the control circuit (Fig. 3; para. (24) of Description: “The trigger control circuit 13 includes a P-channel MOS transistor 28 functioning as a switch element. The MOS transistor 28 has a current path between source and drain connected between a cathode of the diode circuit 270.”), wherein when the static electricity is generated on the protected chip, the control circuit outputs the high-level signal to the cathode of the diode string to trigger the silicon-controlled rectifier to discharge an electro-static current (para. (14), (25)-(26) of Description; Fig. 3 shows that on a high/on signal, the control circuit will signal the trigger circuit (diode string) to trigger the SCR to discharge), and when the static electricity is not generated on the protected chip, the control circuit outputs the low-level signal to the cathode of the diode string to reduce a voltage drop at two ends of the diode string (para. (14), (25)-(26) of Description; Fig. 3 shows that on a low/off signal, the control circuit will direct no signal or voltage to the diode string, thus implicitly reducing a voltage drop at both ends of the diode string).
Sugahara does not explicitly disclose wherein the control circuit is connected between the anode and the cathode of the silicon-controlled rectifier.
Sato discloses wherein the control circuit (27, 30, 31 in Fig. 9) is connected between the anode (24 in Fig. 9) and the cathode (25 in Fig. 9) of the silicon-controlled rectifier (21 in Fig. 9; [0059]).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to have connected the control circuit in such a way as disclosed by Sato with the chip and electro-static protection circuit disclosed by Sugahara in order to have a high resistance during normal operation and low resistance while enabling protection (Sato, [0037]). Therefore, connecting the control circuit in such a way as disclosed by Sato with the chip and electro-static protection circuit disclosed by Sugahara would enable the electro-static protection circuit to reduce leakage during normal operation and discharge a surge voltage during protection operation.
Regarding claims 3 and 16, Sugahara discloses wherein a trigger voltage of the silicon-controlled rectifier increases with increase of a number of diodes (para. (25) of Description: “a trigger voltage Vtrg of the trigger circuit 12A is obtained from the following equation (1). Vtrg=(n+m)*Vf+Vbe(23).” When this trigger voltage is met, the SCR is triggered (para. (26) of Description: “when the voltage exceeds the foregoing trigger voltage Vtrg, the trigger circuit 12A triggers the discharge circuit 11 to turn on the SCR 22.”)
Regarding claims 4 and 17, Sugahara discloses wherein a number of diodes is 2 or 3 (270 Fig. 3; para. (23) of Description: “The diode circuit 270 is composed of at least one or a plurality of diodes 27…”).
Regarding claims 5 and 18, Sugahara discloses wherein a trigger voltage of the silicon-controlled rectifier is less than a maximum voltage of an electro-static protection design window. (Examiner’s note: based on the circuit, it is implicit that the trigger voltage of the SCR is less than a maximum voltage of an electro-static design window; if the trigger voltage was above the maximum voltage, the SCR would break due to overvoltage and no longer work.)
Regarding claims 7 and 20, Sugahara discloses wherein an equivalent circuit of the silicon-controlled rectifier comprises a first triode (23 in Fig. 3; para. (21) of Description), a second triode (24 in Fig. 3) and a first resistor (26 in Fig. 3), an emitter of the first triode is the anode of the silicon-controlled rectifier (A in Fig. 3), a base of the first triode is connected with the anode of the diode string and a collector of the second triode (Fig. 3; para. (21)-(22) of Description), a collector of the first triode is connected with a base of the second triode and one end of the first resistor (Fig. 3; para. (21)-(22) of Description), and an emitter of the second triode is connected with the other end of the first resistor and serves as the cathode of the silicon-controlled rectifier (Fig. 3; para. (21)-(22) of Description).
Regarding claim 8, Sugahara discloses wherein the first triode is a PNP triode (23 in Fig. 3; para. (21) of Description) and the second triode is an NPN triode (24 inf Fig. 3; para. (21) of Description).
Regarding claims 9-11, Sugahara discloses the invention from above, but does not explicitly teach wherein the control circuit comprises: a trigger sub-circuit, wherein the trigger sub-circuit is connected between the anode and the cathode of the silicon controlled rectifier, and is configured to generate a high-level signal when the static electricity is generated on the protected chip, and generate a low-level signal when the static electricity is not generated on the protected chip; and a buffer sub-circuit, wherein the buffer sub-circuit is connected between the cathode of the silicon controlled rectifier and the cathode of the diode string, and an input end of the buffer sub-circuit is connected with an output end of the trigger sub-circuit.
Sato discloses wherein the control circuit comprises: a trigger sub-circuit (30, 31 in Fig. 9), wherein the trigger sub-circuit is connected between the anode (24 in Fig. 9) and the cathode (25 in Fig. 9) of the silicon controlled rectifier, and is configured to generate a high-level signal when the static electricity is generated on the protected chip, and generate a low-level signal when the static electricity is not generated on the protected chip ([0060]; displacement current caused by the capacitor turns on the SCR during an ESD event, while the MOS and SCR remain off during normal operation); and a buffer sub-circuit (27 in Fig. 9), wherein the buffer sub-circuit is connected between the cathode (25 in Fig. 9; [0059]) of the silicon-controlled rectifier and the cathode of the diode string (26-1 – 26-n in Fig. 9; [0059]), and an input end of the buffer sub-circuit is connected with an output end of the trigger sub-circuit (Fig. 9; [0059]).
Sato discloses wherein the trigger sub-circuit comprises a second resistor (31 in Fig. 9; [0059]-[0060]) and a capacitor (30 in Fig. 9; [0059]-[0060]), one end of the capacitor is connected with the anode of the silicon-controlled rectifier (24 in Fig. 9; [0059]), the other end of the capacitor is connected with one end of the second resistor and serves as the output end of the trigger sub-circuit (Fig. 9), and the other end of the second resistor is connected with the cathode of the silicon controlled rectifier (25 in Fig. 9; [0059]).
Sato discloses wherein the buffer sub-circuit comprises an N-Metal Oxide Semiconductor (NMOS) transistor (27 in Fig. 9; [0059]), a source of the NMOS transistor is connected with the cathode of the silicon-controlled rectifier (25 in Fig. 9; [0059]), a gate of the NMOS transistor is connected with the output end of the trigger sub-circuit (30, 31 in Fig. 9; [0059])), and a drain of the NMOS transistor is connected with the cathode of the diode string (26-1 – 26-n in Fig. 9; [0059]).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to use the control circuit, including trigger and buffer sub-circuits, disclosed by Sato with the chip and electro-static protection circuit disclosed by Sugahara. It is well-known in the art that NMOS transistors are smaller than equivalent PMOS transistors; therefore, using an NMOS buffer would reduce the necessary size of the chip, thus making the chip less expensive to produce.
Claims 6 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Sugahara (US 7933107 B2) in view of Sato (US 2005/0212009 A1), in further view of Chen et al. (US 2004/0100746 A1).
Regarding claims 6 and 19, the combination of Sugahara and Sato discloses the chip from above but does not explicitly teach wherein a holding voltage of the silicon-controlled rectifier is greater than a power supply voltage of the protected chip.
Chen et al. discloses wherein a holding voltage of the silicon-controlled rectifier is greater than a power supply voltage of the protected chip ([0054]: “the holding voltage of the SCR is raised to a first holding voltage that is above a power supply voltage to keep the SCR from latching-up during normal operations.”)
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to use the method of adjusting a holding voltage disclosed by Chen et al. with the chip and electro-static protection circuit disclosed by Sugahara in order to keep the SCR from latching up during normal operation.
Claims 13 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Sugahara (US 7933107 B2) in view of Cai et al. (US 2017/0069616 A1).
Regarding claim 13, Sugahara discloses the chip from above, but does not explicitly teach wherein the protected circuit comprises a power supply end, a ground end and a signal transmission end, and the electro-static protection circuit is connected between any two of the power supply end, the ground end and the signal transmission end to perform electro-static protection on the protected circuit.
Cai et al. discloses wherein the protected circuit (20 in Fig. 1) comprises a power supply end (VDD in Fig. 1), a ground end (VSS in Fig. 1) and a signal transmission end (10, 11 in Fig. 1), and the electro-static protection circuit (12, 14, 16, 18, 26 in Fig. 1) is connected between any two of the power supply end, the ground end and the signal transmission end to perform electro-static protection on the protected circuit ([0007]-[0008]).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to use the circuit layout disclosed by Cai et al. with the chip and electro-static protection circuit disclosed by Sugahara in order provide electro-static protection between multiple terminals of a protected circuit.
Regarding claim 14, Sugahara discloses the chip from above, but does not explicitly teach a plurality of the electro-static protection circuits, and the electro-static protection circuits are connected between the power supply end and the ground end, between the power supply end and the signal transmission end, and between the ground end and the signal transmission end.
Cai et al. discloses a plurality of the electro-static protection circuits, and the electro-static protection circuits (12, 14, 16, 18, 26 in Fig. 1; [0007]-[0010]) are connected between the power supply end and the ground end, between the power supply end and the signal transmission end, and between the ground end and the signal transmission end ([0007]-[0010]).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to use the circuit layout disclosed by Cai et al. with the chip and electro-static protection circuit disclosed by Sugahara in order provide electro-static protection between multiple terminals of a protected circuit, thus increasing overall protection.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure. Please see attached PTO-892.
Satou et al. (US 2005/0047042 A1) teaches a semiconductor integrated circuit device including a semiconductor integrated circuit formed in a semiconductor chip, and a switching element that is formed in the semiconductor chip and has a current path whose one end and the other end are both connected to the semiconductor integrated circuit. The switching element receives a control signal produced by a control circuit and causes a current to flow from the one end to the other end of the current path by a bipolar operation. The semiconductor integrated circuit device further includes the control circuit that is formed in the semiconductor chip and configured to control a conductive/non-conductive state of the current path of the switching element.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL ROBERT SCHWARCK whose telephone number is (571)272-0289. The examiner can normally be reached Mon-Fri 8:00-5:00 EST.
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/FRED E FINCH III/Primary Examiner, Art Unit 2838
/DANIEL R SCHWARCK/Examiner, Art Unit 2838