DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statements (IDS) submitted on April 3rd, 2023 and July 3rd, 2023 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements have been considered by the examiner.
Claim Objections
Claim 6 is objected to because of the following informalities: “…directing and detecting are executed by an alignment unit of the electrooptic.” should read as “…directing and detecting are executed by an alignment unit of the electrooptic chip. Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-10 are rejected under 35 U.S.C. 103 as being unpatentable over Theurer et al. (“Flip-Chip Integration of InP to SiN Photonic Integrated Circuits,” Journal of Lightwave Technology, Vol. 38, No. 9, May 2020) in view of Lu et al. (US20160097901 A1).
Regarding Claim 1, Theurer et al. discloses a method for aligning a laser chip with an electrooptic chip (p. 2631), the method comprising:
directing a probe signal through the electrooptic chip and towards the laser chip (p. 2632)
detecting a reflected a probe signal by a first detector of the electrooptic chip, the reflected probe signal being reflected from the laser chip (Fig. 3)
the reflected probe signal passes through a first optical path of the electrooptic chip
determining based on the reflected probe signal, whether the laser chip is aligned with the electrooptic chip (p. 2632)
the directing and detecting occur while maintaining a spatial relationship between the laser chip and the electrooptic chip (p. 2631-2632)
the alignment is performed without operating the laser chip
However, Theurer et al. does not expressly disclose that the probe signal and reflected probe signal are within a first wavelength range that is distinct from a second wavelength range used for the laser signal, or that the first optical path differs from a second optical path configured to convey signals within the second wavelength range, nor that the laser chip is configured to output a laser signal within the second wavelength range. Lu et al. explicitly discloses a first optical path and a second optical path that differ from each other, wherein a wavelength selective coupler (which may take the form of an electrooptic chip) routes signals of a first wavelength along the first optical path and signals of second wavelength along the second optical path (paragraphs 0007-0011, 0028; Claims 1, 13). Lu et al. further discloses a reflector at the distal end of the first optical path exhibiting differential reflectivity, configured to have high reflectivity for signals of a first wavelength, and low reflectivity for signals of the second wavelength (paragraphs 0010-0011; Claims 5, 11). It would have been obvious to one of ordinary skill in the art, before the effective filing date, to modify the alignment system of Theurer et al. to incorporate the wavelength-selective dual-path architecture of Lu et al., such that a first wavelength range is used for the probe signal routed through the first optical path and a second wavelength range is used for the operational laser signal routed through the separate second optical path, with the laser chip’s distal element providing differential reflectivity between the two wavelength ranges.
Regarding Claim 2, Theurer et al explicitly discloses changing the spatial relationship of the electrooptic and laser chips during assembly until alignment is confirmed. (p. 2631-2632)
Regarding Claim 3, Lu et al. discloses a first WSC (wavelength selective coupler) port of a WSC directing the probe signal from the first WSC port to a second WSC port through a first WSC optical path configured to convey signals within the first wavelength range. Lu et al. further discloses a third WSC port optically coupled to the second WSC port via a second WSC optical path configured to convey signals within the second wavelength range (paragraphs 0007-0009; Claims 1, 7, 13).
Regarding Claim 4, Theurer et al. discloses measuring probe signal strength as a part of the alignment process (p. 2632). Measuring a probe signal for power monitoring is standard technique within the art.
Regarding Claim 5, Theurer et al. expressly discloses executing the directing and detecting while a laser of the laser chip is deactivated. (p. 2631; Abstract paragraph)
Regarding Claim 6, To the extent the claim is interpreted as reciting an alignment unit of the electrooptic chip, Theurer et al. discloses that the directing and detecting are executed by an alignment unit of the electrooptic [chip] (p. 2632)
Regarding Claim 7, Theurer et al. expressly discloses outputting a laser signal from the laser chip towards an electrooptic chip that is aligned with the laser chip (p.2632-2633). Theurer et al. further discloses that the alignment was obtained by applying an alignment process comprising directing a probe signal toward the laser chip, detecting a reflected probe signal, and determining alignment based on the reflected probe signal without operating the laser chip. (p. 2631-2632; Abstract paragraph). The limitations that the laser passes through a second optical path configured to convey signals within a second wavelength range, that the probe signal is within a first wavelength range that differs from the second wavelength range, and that the first optical path differs from the second optical path are taught by the combination with Lu et al. as analyzed for Claim 1 (Lu et al. 0007-0012; Claims 1, 13)
Regarding Claim 8, Theurer et al. discloses a system comprising a laser chip and an electrooptic chip. Theurer et al. further discloses a first optical path configured to direct a probe signal from the electrooptic chip toward the laser chip and direct a reflected probe signal to the first detector (p. 2632). The limitations that the laser chip is configured to output a laser signal within a second wavelength range, that the first optical path differs from the second, that the second optical path is configured to convey signals within a second wavelength range, that the probe signal is within a first wavelength range that differs from the second wavelength range are taught by the combination with Lu et al. as mentioned in Claim 1 which discloses the dual-path WSC routing structure separating the probe wavelength path from the operational laser signal wavelength path (0007-0012; Claims 1, 5, 11, 13).
Regarding Claim 9, Lu et al. further discloses a WSC configured to receive the reflected probe signal from the laser chip and output it toward a part of the first optical path, receive the laser signal from the chip, and output the laser signal toward a part of the second optical path. (paragraphs 0007-0008; Claims 1, 5) It would have been obvious to one of ordinary skill in the art, before the effective filing date, to implement this WSC structure performing all the functions of the parent claim.
Regarding Claim 10, Lu et al. further discloses a three-port dual-internal-path WSC, configured to convey signals, with their respective wavelengths to and from respective ports (paragraphs 0007-0009; Claims 1, 7, 13-14). It would have been obvious to one of ordinary skill in the art, before the effective filing date, to implement this three-port configuration into the WSC structure performing all the functions of the parent claim.
Claims 11-25 are rejected under 35 U.S.C. 103 as being unpatentable over Theurer et al. (“Flip-Chip Integration of InP to SiN Photonic Integrated Circuits,” Journal of Lightwave Technology, Vol. 38, No. 9, May 2020) in view of Maxwell et al. (“Hybrid Integration of monolithic semiconductor optical amplifier arrays using positive assembly” Proceedings of the 55th Electronic Components and Technology Conference, May 31-June 3, 2005, IEEE Document No. 1441444), and in further view of Cole (US6654523 B1) and Lu et al. (US20160097901 A1).
Regarding Claim 11, Theurer et al. discloses a method for optically aligning multiple chip regions (p. 2631-2632; Abstract paragraph), the method comprising:
directing an optical probe signal from a first chip region toward an intermediate chip region during an alignment iteration without operating the chip
evaluating the detected signal to determine whether the chip regions are aligned
maintaining a spatial relationship between the chip regions when aligned
changing the spatial relationship and performing another alignment iteration when misaligned
Theurer et al. does not expressly disclose a three-chip region a comprising a first, second, and intermediate chip region, nor an active electrooptical component idle during alignment; wherein the intermediate chip region is at least partially transparent to both wavelength bands and the alignment path passes through the intermediate chip region to a detector of the second chip region. Maxwell et al. expressly discloses a three-chip region comprising a first, second and intermediate chip region, and an active electrooptical component that is idle during alignment iteration. Maxwell et al. further discloses the intermediate chip region is at least partially transparent to both the first and second wavelength bands. Neither Theurer et al. or Maxwell et al. expressly disclose using a transmissive optical probe signal that passes through the intermediate chip region to a detector of the second chip region, wherein the attenuation of the alignment path is indicative of alignment. Cole expressly discloses directing an alignment probe signal through an optical path within a chip, from a source at one end to a detector at the other end, wherein the detected probe signal strength through the alignment path is indicative of alignment between chips (Abstract paragraph; Col. 3, 1-30). Cole further discloses that the alignment path is independent of the operational signal path, and alignment is determined without activation (Col. 2, 45-65; Col. 3, 1-15). It would have been obvious to one of ordinary skill in the art, before the effective filing date, to combine the three-chip-region passive assembly of Maxwell et al. with the transmissive-probe alignment methodology of Cole, as further guided by Theurer et al.’s teaching that probe-signal based passive alignment without activating the chip is desirable, and further incorporating the wavelength selective WSC routing structure of Lu et al. for dependent claims reciting WSC-specific limitations . A person of ordinary skill in the art would recognize that a traveling-wave semiconductor optical amplifier with AR-coated facets would yield a weak signal under Theurer’s methodology, providing strong motivation to adopt a transmissive approach as taught by Cole. Lu et al. discloses the WSC dual-path WSC port structure separating first and second band signals into separate optical paths, and it would have been obvious to incorporate this structure into the multi-chip-region system for the same reasons as set forth in the rejection of Claims 1-10. Namely, to separate the alignment probe wavelength path from the operational transmission wavelength path using a WSC.
Regarding Claim 12, Maxwell et al. expressly discloses that the optical signal path passes through the active electrical component (p. 1-2 Figs. 1, 7).
Regarding Claim 13, Cole discloses that an intermediate optical path does not pass through the active electrooptical component (Col. 3, 11-25). It would have been obvious to one of ordinary skill in the art, before the effective filing date, to provide an auxiliary optical path bypassing the active electrooptical component for alignment, as a matter of routine engineering design choice.
Regarding Claim 14, Maxwell et al. explicitly discloses that the active electrooptical component is a semiconductor optical amplifier (SOA) (Abstract paragraph; p. 1-2).
Regarding Claim 15, Maxwell et al. discloses maintaining the spatial relationship comprises bonding and wire-bonding multiple chip regions together (p. 2; Fig. 4). Theurer et al. further discloses bonding the chips after alignment is confirmed (p. 2632-2633).
Regarding Claim 16, Maxwell et al. expressly discloses activating the SOA component following a formation of conductive paths to SOA component (p. 2; Fig. 4)
Regarding Claim 17, Maxwell et al. discloses that an optical signal of the second wavelength band is transmitted and directed toward the intermediate chip region, following the bonding and activation of the SOA component (p. 3; Fig. 9). Theurer et al. further discloses that the laser signal is directed through the chip region following alignment and bonding (p. 2632-2633).
Regarding Claim 18, Cole discloses that the first alignment probe optical path is separate from a second optical path within the chip region (Col. 3, 11-25). Lu et al. further discloses the dual-wavelength separated first and second optical paths (0007-0009; Claim 13). It would have been obvious to one of ordinary skill in the art, before the effective filing date, to implement dual alignment and transmission paths within the second chip region of the Maxwell et al. structure, applying the WSC dual-path routing of Lu et al. and the independent alignment optical path concept of Cole, for the same reasons as stated in the parent claim.
Regarding Claim 19, Maxwell et al., Cole, and Lu et al. disclose all the limitations of the parent claim. Lu et al. further discloses the WSC routing structure for first optical probe signals within the first wavelength range comprising a plurality of ports configured to receive convey, and output signals, with the first wavelength reflected signal returning through the same first WSC optical path (0007-0008; Claims 1,7). It would have been obvious to one of ordinary skill in the art, before the effective filing date, to apply this WSC architecture to both the first and second chip regions of the Maxwell et al. three-chip system =, as the same wavelength-selective routing function is needed at both ends of the intermediate chip region to route the transmitted optical probe signal.
Regarding Claim 20, Maxwell et al., Cole, and Lu et al. disclose all the limitations of the parent claim. Lu et al. further discloses the WSC second optical path routing second-wavelength signals through separate WSC ports (0007-0009; Claims 7, 14). It would have been obvious to one of ordinary skill in the art, before the effective filing date, to extend this second-wavelength path routing to both WSCs of the first and second chip regions for the transmission iteration, as this would be the natural consequence of applying Lu et al.’s dual-path structure to both chip regions of the Maxwell et al. system.
Regarding Claim 21, Fabricating multiple photonic chip regions on a single substrate is a well-known and standard design approach in silicon photonics, within the ordinary skill in the art.
Regarding Claim 22, Maxwell et al. discloses that the SOA chip comprises further alignment iterations interfacing with waveguides on both sides of the intermediate chip region, meaning a probe signal form either the first or second chip region is structurally possible (p. 2). Cole further discloses alignment iterations operable from either end of the optical circuit (Col. 3, 30-50). It would have been obvious to one of ordinary skill in the art, before the effective filing date, to direct a probe signal from the second chip region as a complementary or verification alignment iteration, with a detector in the first chip region, as both the teachings of Maxwell et al. and Cole support this.
Regarding Claim 23, Maxwell et al. expressly discloses that the intermediate optical path further comprises a plurality of waveguide and anti-reflective elements (p. 1-2). Theurer et al. further discloses index-matching and anti-reflective coatings at the chip-to-chip interface.
Regarding Claim 24, Lu et al. discloses the first-to-second port routing through a first WSC optical path for first wavelength signals (0007-0008; Claims 1, 7). It would have been obvious to one of ordinary skill in the art, before the effective filing date, to apply this WSC routing structure to both chip regions as an obvious consequence of implementing the Maxwell et al. three-chip system with Lu et al.’s wavelength-selective routing.
Regarding Claim 25, Theurer et al. discloses aligning chip regions using optical probe signals without operating the active chip, and evaluating the detected signal to determine whether the chip regions are aligned (p.2631-2632). Theurer further discloses an alignment path whose signal strength is indicative of alignment. Theurer et al. further discloses receiving an operational laser signal following alignment and conveying it through the photonic chip for electrooptic processing. Theurer et al. does not expressly disclose a three-chip region structure with a second chip region comprising an active electrooptical component with spaced apart ports, nor an alignment path that passes transmissively through the intermediate chip region, or a first combiner shared between the ingress part of the alignment and transmission path, or receiving a transmitted optical signal from a second wavelength source external to the multiple chip regions. Maxwell et al. discloses the three-chip region structure, with the second chip region comprising an active electrooptical component (SOA) with spaced apart ports optically coupled to the SOA (p. 1-2; Figs. 1, 7, 9). Maxwell et al. further discloses the intermediate chip region is at least partially transparent to both the first and second wavelength bands and that the SOA is idle during alignment. Maxwell et al. further discloses electrooptically processing a transmitted optical signal by the active electrooptical component, from the multiple chip regions (p. 2-3; Fig. 9). Neither Theurer et al. or Maxwell et al. expressly disclose using a transmissive optical probe signal that passes through the intermediate chip region to a detector of the second chip region, wherein the attenuation of the alignment path is indicative of alignment. Cole expressly discloses directing an alignment probe signal through an optical path within a chip, from a source at one end to a detector at the other end, wherein the detected probe signal strength through the alignment path is indicative of alignment between chips (Abstract paragraph; Col. 3, 1-30). Cole further discloses that the alignment and operational paths share common structural elements. Lu et al. discloses a WSC routing first and second wavelength signals along separate first and second optical paths (0007-0009; Claims 1, 7). Lu et al. further discloses a second wavelength source external to the multiple chip regions (0007-0008; Claim 1). It would have been obvious to one of ordinary skill in the art, before the effective filing date, to combine the three-chip-region passive assembly of Maxwell et al. with the transmissive-probe alignment methodology of Cole, as further guided by Theurer et al.’s teaching that probe-signal based passive alignment without activating the chip is desirable, and further incorporating the wavelength selective WSC routing structure of Lu et al. for dependent claims reciting WSC-specific limitations.
Conclusion
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/NASIM KAIRI COOPER/ Examiner, Art Unit 2874
/THOMAS A HOLLWEG/Supervisory Patent Examiner, Art Unit 2874
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