Prosecution Insights
Last updated: April 19, 2026
Application No. 18/165,359

POWER AMPLIFIER SYSTEM WITH PROTECTION CIRCUITRY

Non-Final OA §103§112
Filed
Feb 07, 2023
Examiner
BARTOL, LANCE TORBJORN
Art Unit
2843
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Qorvo US Inc.
OA Round
3 (Non-Final)
78%
Grant Probability
Favorable
3-4
OA Rounds
3y 5m
To Grant
99%
With Interview

Examiner Intelligence

Grants 78% — above average
78%
Career Allow Rate
29 granted / 37 resolved
+10.4% vs TC avg
Strong +31% interview lift
Without
With
+30.8%
Interview Lift
resolved cases with interview
Typical timeline
3y 5m
Avg Prosecution
38 currently pending
Career history
75
Total Applications
across all art units

Statute-Specific Performance

§103
54.5%
+14.5% vs TC avg
§102
18.2%
-21.8% vs TC avg
§112
26.3%
-13.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 37 resolved cases

Office Action

§103 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Continued Examination Under 37 CFR 1.114 A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on March 13, 2026 has been entered. Response to Amendment The amendment filed March 13, 2026 has been entered. Claims 1-24 remain pending in the application. Applicant’s amendments to the claims have overcome each and every 35 U.S.C. § 112 rejection previously presented in the Final Office Action mailed December 16, 2025. Response to Arguments Applicant’s arguments, see pages 8-14, filed March 13, 2026, with respect to the rejections of claims 1-24 under 35 U.S.C. § 103 have been fully considered and are persuasive. Therefore, the rejections have been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of newly found prior art reference Lehmann et al. (Patent Publication Number WO 2012/012850 A1), hereafter referred to as Lehmann. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claim 24 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 24 recites the limitation “the first stage” in line 5. There is insufficient antecedent basis for this limitation in the claim. Amending the limitation to “the first stage amplifier” is sufficient to overcome this rejection, which is how the limitation will be treated for examination purposes. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-3, 9-11, and 23-24 are rejected under 35 U.S.C. 103 as being unpatentable over Peng in view of Lehmann. Regarding claim 1, Peng discloses: A power amplifier system (Peng, Fig. 1) comprising: a first stage amplifier (Fig. 1, 105) having a first supply terminal (Fig. 1, see connection between 105 and 103), a first input (Fig. 1, see connection between 105 and 101), and a first output (Fig. 1, see connection between 105 and 106); a second stage amplifier (Fig. 1, 106) having a second supply terminal (Fig. 1, see connection between 106 and 104), a second output (Fig. 1, see connection between 106 and 107), and a second input coupled to the first output (Fig. 1, see connection between 106 and 105); a first stage bias circuitry (Fig. 1, 102) having a bias output coupled to a bias input of the first stage amplifier (Page 4, Last Paragraph, lines 7-8) and a bias control input (Fig. 1, see connection between 102 and 104); and absolute maximum ratings protection circuitry (Fig. 1, 102 and 104) having a voltage monitoring input coupled to the second supply terminal (Fig. 1, see connection between 104 and 106) and a bias control output coupled to the bias control input (Fig. 1, see connection between 104 and 102), wherein the absolute maximum ratings protection circuitry is configured to reduce the bias of the first stage amplifier through the bias control output based upon voltage monitored at the voltage monitoring input exceeding a predetermined voltage level (Page 5, Paragraph 2, lines 1-7), but fails to disclose [first stage bias circuitry] comprised of continuous-time components, [absolute maximum ratings protection circuitry] comprised of continuous-time components. However, Lehmann teaches [first stage bias circuitry] comprised of continuous-time components (Lehmann, Page 14, lines 3-6 and Page 15, lines 3-7), [absolute maximum ratings protection circuitry] comprised of continuous-time components (Page 14, lines 3-6 and Page 15, lines 12-14). Peng and Lehmann are both considered to be analogous to the claimed invention because they are in the same field of improving power amplifiers used in radio frequency communications. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Peng to incorporate the teachings of Lehmann to implement the circuit of Peng with continuous-time circuitry, which would have the effect of enabling reducing power consumption of the circuit of Peng (Lehmann, Page 14, lines 3-6). Regarding claim 2, Peng further discloses: wherein the predetermined voltage level is at or below a maximum voltage specification for the second stage amplifier (Peng, Page 4, section “Specific implementation examples”, Paragraph 4, lines 1-5 [the over-voltage protection circuit is used to protect the power amplifier, if the reference voltage level is above the maximum voltage specification, it would not serve the purpose of protecting the power amplifier]). Regarding claim 3, Peng further discloses: wherein the absolute maximum ratings protection circuitry has a voltage reference input (Peng, Fig. 1, see connection between 104 and Vref2) configured to receive a reference voltage from which the predetermined voltage level is derived (Fig. 1, Vref2). Regarding claim 9, Peng further discloses: further comprising additional absolute maximum ratings protection circuitry (Peng, Fig. 1, 103 and 102) having an additional voltage monitoring input coupled to the first supply terminal (Fig. 1, see connection between 103 and 105) and an additional bias control output coupled to the bias control input (Fig. 1, see connection between 103 and 102), wherein the additional absolute maximum ratings protection circuitry is configured to reduce the bias of the first stage amplifier through the bias control output based upon voltage monitored at the additional voltage monitoring input exceeding an additional predetermined voltage level (Page 5, Paragraph 2, lines 1-8). Regarding claim 10, Peng further discloses: wherein the additional predetermined voltage level is at or below a maximum voltage specification for the first stage amplifier (Peng, Page 4, section “Specific implementation examples”, Paragraph 4, lines 1-5 [the over-voltage protection circuit is used to protect the power amplifier, if the reference voltage level is above the maximum voltage specification, it would not serve the purpose of protecting the power amplifier]). Regarding claim 11, Peng further discloses: wherein the additional absolute maximum ratings protection circuitry has an additional voltage reference input (Peng, Fig. 1, see connection between 103 and Vref1) configured to receive the reference voltage from which the additional predetermined voltage level is derived (Fig. 1, Vref1). Regarding claim 23, Peng discloses: A method of operating a power amplifier system (Peng, Fig. 1) having a first stage amplifier (Fig. 1, 105) with bias circuitry (Fig. 1, 102) and a first supply terminal (Fig. 1, see connection between 105 and 103), a second stage amplifier (Fig. 1, 106), a second supply terminal (Fig. 1, see connection between 106 and 104), and absolute maximum ratings protection circuitry (Fig. 1, 102 and 104) having a voltage monitoring input coupled to the second supply terminal (Fig. 1, see connection between 104 and 106) and a bias control output coupled to the bias circuitry (Fig. 1, see connection between 104 and 102), the method comprising: monitoring voltage at the voltage monitoring input by way of the absolute maximum ratings protection circuitry (Page 5, Paragraph 2, lines 1-7); and reducing the bias of the first stage amplifier through the bias control output based upon voltage monitored at the voltage monitoring input exceeding a predetermined voltage level (Page 5, Paragraph 2, lines 1-7), but fails to disclose [bias circuitry] comprised of continuous-time components, [absolute maximum ratings protection circuitry] comprised of continuous-time components. However, Lehmann teaches [bias circuitry] comprised of continuous-time components (Lehmann, Page 14, lines 3-6 and Page 15, lines 3-7), [absolute maximum ratings protection circuitry] comprised of continuous-time components (Page 14, lines 3-6 and Page 15, lines 12-14). Peng and Lehmann are both considered to be analogous to the claimed invention because they are in the same field of improving power amplifiers used in radio frequency communications. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Peng to incorporate the teachings of Lehmann to implement the circuit of Peng with continuous-time circuitry, which would have the effect of enabling reducing power consumption of the circuit of Peng (Lehmann, Page 14, lines 3-6). Regarding claim 24, Peng further discloses: further comprising: monitoring voltage at the first supply terminal by way of another absolute maximum ratings protection circuitry (Peng, Fig. 1, 103 and 102) having another bias control output (Fig. 1, see connection between 103 and 102); and reducing the bias of the first stage through the another bias control output based upon the voltage monitored at the first supply terminal exceeding another predetermined voltage level (Page 5, Paragraph 2, lines 1-8). Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Peng in view of Lehmann as applied to claim 3 above, and further in view of Taniguchi et al. (Patent Publication Number CN 1,397,106 A), hereafter referred to as Taniguchi. Regarding claim 4, Peng fails to disclose: wherein the absolute maximum ratings protection circuitry comprises: a first transistor having a first collector coupled to the voltage monitoring input through a series stack of diodes and a first resistor, a first emitter, and a first base coupled to the voltage reference input through a second resistor; and a second transistor having a second collector coupled to the bias control output, a second base coupled to the first emitter, and a second emitter coupled to a fixed voltage node. However, Taniguchi teaches wherein the absolute maximum ratings protection circuitry comprises: a first transistor (Taniguchi, Fig. 26, 106b) having a first collector coupled to the voltage monitoring input through a series stack of diodes and a first resistor (Fig. 26, see connection between collector of 106b and supply of power amplifier transistor 103 via 108d, 116, 108a, 107a, transistor diodes 112b and 112a, and resistor 108c), a first emitter (Fig. 26, see emitter of 106b), and a first base coupled to the voltage reference input through a second resistor (Fig. 26, see connection between base of 106b and VREF2 via 116, resistors 108a and 107a, and 112b); and a second transistor (Fig. 26, 106a) having a second collector coupled to the bias control output (Fig. 26, see connection between collector of 106a and base of amplifying transistor 103 via 116, 108a, and 107a), a second base coupled to the first emitter (Fig. 26, see connection between base of 106a and emitter of 106b via 108a), and a second emitter coupled to a fixed voltage node (Fig. 26, see connection between emitter of 106a and ground). Peng, Lehmann, and Taniguchi are all considered to be analogous to the claimed invention because they are in the same field of improving power amplifiers used in radio frequency communications. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Peng to incorporate the teachings of Taniguchi to include the biasing circuitry of Taniguchi in the circuit of Peng, which would have the effect of reducing the influence of noise (Taniguchi, Page 2, Section “the background technology”, Paragraph 2, lines 1-3). Claims 5-6 are rejected under 35 U.S.C. 103 as being unpatentable over Peng in view of Lehmann and Taniguchi as applied to claim 4 above, and further in view of Karaushi (Patent Publication Number JP 2004/013230 A), hereafter referred to as Karaushi. Regarding claim 5, Peng and Taniguchi fail to disclose: wherein the absolute maximum ratings protection circuitry further comprises a filter capacitor coupled between the second base and the fixed voltage node. However, Karaushi teaches wherein the absolute maximum ratings protection circuitry further comprises a filter capacitor (Karaushi, Fig. 1, C1) coupled between the second base (Fig. 1, see connection between base of Q2 and C1) and the fixed voltage node (Fig. 1, see connection between C1 and VSS). Peng, Lehmann, Taniguchi, and Karaushi are all considered to be analogous to the claimed invention because they are in the same field of improving power amplifiers used in radio frequency communications. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Peng to incorporate the teachings of Karaushi to include the filter capacitor of Karaushi in the circuit of Peng, which would have the effect of reducing noise fluctuations in the circuit of Peng (Paragraph 21, lines 1-7). Regarding claim 6, Peng and Taniguchi fail to disclose: wherein the absolute maximum ratings protection circuitry further comprises a third transistor having a third collector coupled to the first emitter, a third base coupled to the second base, and a third emitter coupled to the fixed voltage node through a third resistor. However, Karaushi further teaches wherein the absolute maximum ratings protection circuitry further comprises a third transistor (Karaushi, Fig. 1, Q1) having a third collector coupled to the first emitter (Fig. 1, see connection between collector of Q1 and emitter of Q3), a third base coupled to the second base (Fig. 1, see connection between bases of Q1 and Q2), and a third emitter coupled to the fixed voltage node through a third resistor (Fig. 1, see connection between emitter of Q1 and VSS via resistor R4). Peng, Lehmann, Taniguchi, and Karaushi are all considered to be analogous to the claimed invention because they are in the same field of improving power amplifiers used in radio frequency communications. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Peng to incorporate the teachings of Karaushi to include the current mirror circuit of Karaushi in the circuit of Peng, which would have the effect of providing a bias voltage with reduced noise fluctuation to the power amplifier of Peng (Karaushi, Paragraph 21, lines 1-7). Claims 7-8 are rejected under 35 U.S.C. 103 as being unpatentable over Peng in view of Lehmann, Taniguchi and Karaushi as applied to claim 6 above, and further in view of Onosaka (Patent Number JP 2,546,051 Y2), hereafter referred to as Onosaka. Regarding claim 7, Peng, Taniguchi, and Karaushi fail to disclose: wherein the absolute maximum ratings protection circuitry further comprises: a fourth transistor having a fourth collector coupled to the first emitter, a fourth emitter coupled to the fixed voltage node, and a fourth base; and a fifth transistor having a fifth collector and a fifth base that are coupled together to the fourth base, and a fifth emitter coupled to the fixed voltage node, wherein the fifth collector is further coupled to the voltage reference input through a fourth resistor, and a diode coupled in series. However, Onosaka teaches wherein the absolute maximum ratings protection circuitry further comprises: a fourth transistor (Onosaka, Fig. 1, Q6) having a fourth collector coupled to the first emitter (Fig. 1, see connection between collector of Q6 and emitter of Q3), a fourth emitter coupled to the fixed voltage node (Fig. 1, see connection between emitter of Q6 and ground), and a fourth base (Fig. 1, see base of Q6); and a fifth transistor (Fig. 1, Q5) having a fifth collector (Fig. 1, see collector of Q5) and a fifth base (Fig. 1, see base of Q5 that are coupled together to the fourth base (Fig. 1, see connection of base and collector of Q5 to base of Q6), and a fifth emitter coupled to the fixed voltage node (Fig. 1, see connection between emitter of Q5 and ground), wherein the fifth collector is coupled to the voltage reference input through a fourth resistor, and a diode coupled in series (Fig. 1, see series connection between collector of Q5 and Vz via resistor R11 and diode D1). Peng, Lehmann, Taniguchi, Karaushi, and Onosaka are all considered to be analogous to the claimed invention because they are in the same field of improving power amplifiers used in radio frequency communications. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Peng to incorporate the teachings of Onosaka to include the current mirror circuit of Onosaka in the circuit of Peng, which would have the effect of enabling a fast activation time for the maximum ratings protection circuit of Peng (Onosaka, Page 3, Paragraph 4, lines 1-6). Regarding claim 8, Peng fails to disclose: wherein the fixed voltage node is coupled to a circuit ground. However, Taniguchi teaches wherein the fixed voltage node is coupled to a circuit ground (Taniguchi, Fig. 26, see that emitter of 106a is coupled to ground). Peng, Lehmann, Taniguchi, Karaushi, and Onosaka are all considered to be analogous to the claimed invention because they are in the same field of improving power amplifiers used in radio frequency communications. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Peng to incorporate the teachings of Taniguchi to include the biasing circuitry of Taniguchi in the circuit of Peng, which would have the effect of reducing the influence of noise (Taniguchi, Page 2, Section “the background technology”, Paragraph 2, lines 1-3). Claims 12-14 and 20-22 are rejected under 35 U.S.C. 103 as being unpatentable over Peng in view of Wang (Patent Number US 8,022,770 B1), hereafter referred to as Wang, and Lehmann. Regarding claim 12, Peng discloses: A wireless communication device (Peng, Fig. 1) comprising: wherein the transmit circuitry comprises: a first stage amplifier (Fig. 1, 105) having a first supply terminal (Fig. 1, see connection between 105 and 103), a first input (Fig. 1, see connection between 105 and 101), and a first output (Fig. 1, see connection between 105 and 106); a second stage amplifier (Fig. 1, 106) having a second supply terminal (Fig. 1, see connection between 106 and 104), a second output (Fig. 1, see connection between 106 and 107), and a second input coupled to the first output (Fig. 1, see connection between 106 and 105); a first stage bias circuitry (Fig. 1, 102) having a bias output coupled to a bias input of the first stage amplifier (Page 4, Last Paragraph, lines 7-8) and a bias control input (Fig. 1, see connection between 102 and 104); and absolute maximum ratings protection circuitry (Fig. 1, 102 and 104) having a voltage monitoring input coupled to the second supply terminal (Fig. 1, see connection between 104 and 106) and a bias control output coupled to the bias control input (Fig. 1, see connection between 104 and 102), wherein the absolute maximum ratings protection circuitry is configured to reduce the bias of the first stage amplifier through the bias control output based upon voltage monitored at the voltage monitoring input exceeding a predetermined voltage level (Page 5, Paragraph 2, lines 1-7); but fails to disclose a baseband processor; transmit circuitry configured to receive encoded data from the baseband processor and to modulate a carrier signal with the encoded data, [first stage bias circuitry] comprised of continuous-time components, [absolute maximum ratings protection circuitry] comprised of continuous-time components. However, Wang teaches a baseband processor (Wang, Fig. 1, 110); transmit circuitry (Fig. 1, 155) configured to receive encoded data from the baseband processor and to modulate a carrier signal with the encoded data (Col. 3, line 67-Col. 4, line 4), but fails to disclose [first stage bias circuitry] comprised of continuous-time components, [absolute maximum ratings protection circuitry] comprised of continuous-time components. However, Lehmann teaches [first stage bias circuitry] comprised of continuous-time components (Lehmann, Page 14, lines 3-6 and Page 15, lines 3-7), [absolute maximum ratings protection circuitry] comprised of continuous-time components (Page 14, lines 3-6 and Page 15, lines 12-14). Peng, Wang, and Lehmann are all considered to be analogous to the claimed invention because they are in the same field of improving power amplifiers used in radio frequency communications. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Peng to incorporate the teachings of Wang and Lehmann to include the baseband processing circuitry of Wang in the circuit of Peng, which would have the effect of allowing the power amplifier of Peng to be incorporated into an RF signal chain (Wang, Col. 3, lines 21-28), and to implement the circuit of Peng with continuous-time circuitry, which would have the effect of enabling reducing power consumption of the circuit of Peng (Lehmann, Page 14, lines 3-6). Regarding claim 13, Peng further discloses: wherein the predetermined voltage level is at or below a maximum voltage specification for the second stage amplifier (Peng, Page 4, section “Specific implementation examples”, Paragraph 4, lines 1-5 [the over-voltage protection circuit is used to protect the power amplifier, if the reference voltage level is above the maximum voltage specification, it would not serve the purpose of protecting the power amplifier]). Regarding claim 14, Peng further discloses: wherein the absolute maximum ratings protection circuitry has a voltage reference input (Peng, Fig. 1, see connection between 104 and Vref2) configured to receive a reference voltage from which the predetermined voltage level is derived (Fig. 1, Vref2). Regarding claim 20, Peng further discloses: further comprising additional absolute maximum ratings protection circuitry (Peng, Fig. 1, 103 and 102) having an additional voltage monitoring input coupled to the first supply terminal (Fig. 1, see connection between 103 and 105) and an additional bias control output coupled to the bias control input (Fig. 1, see connection between 103 and 102), wherein the additional absolute maximum ratings protection circuitry is configured to reduce the bias of the first stage amplifier through the bias control output based upon voltage monitored at the additional voltage monitoring input exceeding an additional predetermined voltage level (Page 5, Paragraph 2, lines 1-8). Regarding claim 21, Peng further discloses: wherein the additional predetermined voltage level is at or below a maximum voltage specification for the first stage amplifier (Peng, Page 4, section “Specific implementation examples”, Paragraph 4, lines 1-5 [the over-voltage protection circuit is used to protect the power amplifier, if the reference voltage level is above the maximum voltage specification, it would not serve the purpose of protecting the power amplifier]). Regarding claim 22, Peng further discloses: wherein the additional absolute maximum ratings protection circuitry has an additional voltage reference input (Peng, Fig. 1, see connection between 103 and Vref1) configured to receive the reference voltage from which the additional predetermined voltage level is derived (Fig. 1, Vref1). Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Peng in view of Wang and Lehmann as applied to claim 14 above, and further in view of Taniguchi. Regarding claim 15, Peng and Wang fail to disclose: wherein the absolute maximum ratings protection circuitry comprises: a first transistor having a first collector coupled to the voltage monitoring input through a series stack of diodes and a first resistor, a first emitter, and a first base coupled to the voltage reference input through a first resistor; and a second transistor having a second collector coupled to the bias control output, a second base coupled to the first emitter, and a second emitter coupled to a fixed voltage node. However, Taniguchi teaches a first transistor (Taniguchi, Fig. 26, 106b) having a first collector coupled to the voltage monitoring input through a series stack of diodes and a first resistor (Fig. 26, see connection between collector of 106b and supply of power amplifier transistor 103 via 108d, 116, 108a, 107a, transistor diodes 112b and 112a, and resistor 108c), a first emitter (Fig. 26, see emitter of 106b), and a first base coupled to the voltage reference input through a first resistor (Fig. 26, see connection between base of 106b and VREF2 via 116, resistors 108a and 107a, and 112b); and a second transistor (Fig. 26, 106a) having a second collector coupled to the bias control output (Fig. 26, see connection between collector of 106a and base of amplifying transistor 103 via 116, 108a, and 107a), a second base coupled to the first emitter (Fig. 26, see connection between base of 106a and emitter of 106b via 108a), and a second emitter coupled to a fixed voltage node (Fig. 26, see connection between emitter of 106a and ground). Peng, Wang, Lehmann, and Taniguchi are all considered to be analogous to the claimed invention because they are in the same field of improving power amplifiers used in radio frequency communications. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Peng to incorporate the teachings of Taniguchi to include the biasing circuitry of Taniguchi in the circuit of Peng, which would have the effect of reducing the influence of noise (Taniguchi, Page 2, Section “the background technology”, Paragraph 2, lines 1-3). Claims 16-17 are rejected under 35 U.S.C. 103 as being unpatentable over Peng in view of Wang, Lehmann, and Taniguchi as applied to claim 15 above, and further in view of Karaushi. Regarding claim 16, Peng, Wang, and Taniguchi fail to disclose: wherein the absolute maximum ratings protection circuitry further comprises a filter capacitor coupled between the second base and the fixed voltage node. However, Karaushi teaches wherein the absolute maximum ratings protection circuitry further comprises a filter capacitor (Karaushi, Fig. 1, C1) coupled between the second base (Fig. 1, see connection between base of Q2 and C1) and the fixed voltage node (Fig. 1, see connection between C1 and VSS). Peng, Wang, Lehmann, Taniguchi, and Karaushi are all considered to be analogous to the claimed invention because they are in the same field of improving power amplifiers used in radio frequency communications. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Peng to incorporate the teachings of Karaushi to include the filter capacitor of Karaushi in the circuit of Peng, which would have the effect of reducing noise fluctuations in the circuit of Peng (Paragraph 21, lines 1-7). Regarding claim 17, Peng, Wang, and Taniguchi fail to disclose: wherein the absolute maximum ratings protection circuitry further comprises a third transistor having a third collector coupled to the first emitter, a third base coupled to the second base, and a third emitter coupled to the fixed voltage node through a third resistor. However, Karaushi further teaches wherein the absolute maximum ratings protection circuitry further comprises a third transistor (Karaushi, Fig. 1, Q1) having a third collector coupled to the first emitter (Fig. 1, see connection between collector of Q1 and emitter of Q3), a third base coupled to the second base (Fig. 1, see connection between bases of Q1 and Q2), and a third emitter coupled to the fixed voltage node through a third resistor (Fig. 1, see connection between emitter of Q1 and VSS via resistor R4). Peng, Wang, Lehmann, Taniguchi, and Karaushi are all considered to be analogous to the claimed invention because they are in the same field of improving power amplifiers used in radio frequency communications. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Peng to incorporate the teachings of Karaushi to include the current mirror circuit of Karaushi in the circuit of Peng, which would have the effect of providing a bias voltage with reduced noise fluctuation to the power amplifier of Peng (Karaushi, Paragraph 21, lines 1-7). Claims 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over Peng in view of Wang, Lehmann, Taniguchi, and Karaushi as applied to claim 17 above, and further in view of Onosaka. Regarding claim 18, Peng, Wang, Taniguchi, and Karaushi fail to disclose: wherein the absolute maximum ratings protection circuitry further comprises: a fourth transistor having a fourth collector coupled to the first emitter, a fourth emitter coupled to the fixed voltage node, and a fourth base; and a fifth transistor having a fifth collector and a fifth base that are coupled together to the fourth base, and a fifth emitter coupled to the fixed voltage node, wherein the fifth collector is further coupled to the voltage reference input through a fourth resistor, and a diode coupled in series. However, Onosaka teaches wherein the absolute maximum ratings protection circuitry further comprises: a fourth transistor (Onosaka, Fig. 1, Q6) having a fourth collector coupled to the first emitter (Fig. 1, see connection between collector of Q6 and emitter of Q3), a fourth emitter coupled to the fixed voltage node (Fig. 1, see connection between emitter of Q6 and ground), and a fourth base (Fig. 1, see base of Q6); and a fifth transistor (Fig. 1, Q5) having a fifth collector (Fig. 1, see collector of Q5) and a fifth base (Fig. 1, see base of Q5 that are coupled together to the fourth base (Fig. 1, see connection of base and collector of Q5 to base of Q6), and a fifth emitter coupled to the fixed voltage node (Fig. 1, see connection between emitter of Q5 and ground), wherein the fifth collector is coupled to the voltage reference input through a fourth resistor, and a diode coupled in series (Fig. 1, see series connection between collector of Q5 and Vz via resistor R11 and diode D1). Peng, Wang, Lehmann, Taniguchi, Karaushi, and Onosaka are all considered to be analogous to the claimed invention because they are in the same field of improving power amplifiers used in radio frequency communications. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Peng to incorporate the teachings of Onosaka to include the current mirror circuit of Onosaka in the circuit of Peng, which would have the effect of enabling a fast activation time for the maximum ratings protection circuit of Peng (Onosaka, Page 3, Paragraph 4, lines 1-6). Regarding claim 19, Peng and Wang fail to disclose: wherein the fixed voltage node is coupled to circuit ground. However, Taniguchi teaches wherein the fixed voltage node is coupled to circuit ground (Taniguchi, Fig. 26, see that emitter of 106a is coupled to ground). Peng, Wang, Lehmann, Taniguchi, Karaushi, and Onosaka are all considered to be analogous to the claimed invention because they are in the same field of improving power amplifiers used in radio frequency communications. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Peng to incorporate the teachings of Taniguchi to include the biasing circuitry of Taniguchi in the circuit of Peng, which would have the effect of reducing the influence of noise (Taniguchi, Page 2, Section “the background technology”, Paragraph 2, lines 1-3). Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Mitzlaff et al. (Patent Publication Number US 2008/0218271 A1) discloses (Fig. 2) an overvoltage protection circuit for a power amplifier based on the supply voltage of the second stage amplifier to modify the biases of the first and second stages. Rogers (Patent Publication Number US 2021/0126598 A1) discloses (Fig .4) a biasing circuit comprising resistors and diodes in series for a power amplifier. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Lance T Bartol whose telephone number is (703)756-1267. The examiner can normally be reached Monday - Thursday 6:30 a.m. - 4:00 p.m. CT, Alternating Fridays 6:30 - 3:00. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrea Lindgren Baltzell can be reached at 571-272-5918. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /LANCE TORBJORN BARTOL/Examiner, Art Unit 2843 /ANDREA LINDGREN BALTZELL/Supervisory Patent Examiner, Art Unit 2843
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Prosecution Timeline

Feb 07, 2023
Application Filed
Aug 19, 2025
Non-Final Rejection — §103, §112
Nov 17, 2025
Response Filed
Dec 02, 2025
Final Rejection — §103, §112
Feb 11, 2026
Response after Non-Final Action
Mar 13, 2026
Request for Continued Examination
Mar 19, 2026
Response after Non-Final Action
Mar 25, 2026
Non-Final Rejection — §103, §112 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12597897
DIFFERENTIAL AMPLIFYING APPARATUS
2y 5m to grant Granted Apr 07, 2026
Patent 12580539
TRANSIMPEDANCE AMPLIFIER CIRCUIT
2y 5m to grant Granted Mar 17, 2026
Patent 12580526
POWER AMPLIFIER WITH CLAMP AND FEEDBACK PROTECTION CIRCUITRY
2y 5m to grant Granted Mar 17, 2026
Patent 12556148
HYBRID LOW POWER RAIL TO RAIL AMPLIFIER WITH LEAKAGE CONTROL
2y 5m to grant Granted Feb 17, 2026
Patent 12542517
BASELINE WANDER DIFFERENTIAL TIA WITH RESISTIVE FEEDFORWARD AC COUPLING PATH
2y 5m to grant Granted Feb 03, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
78%
Grant Probability
99%
With Interview (+30.8%)
3y 5m
Median Time to Grant
High
PTA Risk
Based on 37 resolved cases by this examiner. Grant probability derived from career allow rate.

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