DETAILED ACTION
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 01/22/2026 has been entered.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Claims 1, 11, 21, and 26 have been amended. Claims 1, 3-11, 13-21, 23-26, and 28-30 are currently pending.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1, 11, 21, and 26 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3-5, 7-11, 13-15, 17-21, 23-26, and 28-30 are rejected under 35 U.S.C. 103 as being unpatentable over Das Sharma (US 2019/0042524) in view of Schneider (US 2019/0121417).
Regarding claim 1, Das Sharma teaches an apparatus (Figs. 4A & 4B, Host upstream component 402), comprising: a bus interface (Figs. 4A & 4B, Bus interfaces 412/414; Paragraph 0058, upstream component 402 can include a first downstream port 412 and a first upstream port 414) configured to couple the apparatus to a component (Figs. 4A & 4B, Device downstream component 404) through a link (Figs. 4A & 4B, PCIe link comprising lanes 422/424/426/428) and configured to perform operations comprising: transmitting a link configuration change request (Figs. 4A & 4B, Host upstream component 402 contains system manager 450 that transmits lane change requests to register of downstream component; Paragraph 0061, system manager can set a register… in the downstream component 404 to cause each component to recognize the change in a line direction) to the component through the bus interface to reconfigure the link from a first link configuration to a second link configuration (Fig. 8 flowchart, Host upstream component (USP) causes lane directions in link to change in steps 802-816; Paragraph 0090, link width can be adjusted by the host or the device through a register setting indication (816)… desired width in each direction is exchanged and the width decided), wherein the second link configuration indicates a lane configuration for a lane of the link (Fig. 4A shows first link configuration 426 and Fig. 4B shows second link configuration 426 wherein the lane has swapped directions), and wherein the lane configuration indicates a bidirectional lane, a unidirectional transmit lane, or a unidirectional receive lane (Fig. 6 shows configuration of Figs. 4A & 4B with unidirectional transmit lane and unidirectional receive lane in link 611, and a bidirectional lane 612a; Paragraph 0044, Reconfiguration of the lane, such as discussed herein, however, may cause a single lane to be reconfigured into one or more unidirectional lanes… Paragraph 0046, some lanes can be bidirectional lanes); and communicating over the bus interface based on the link configuration change request (Fig. 4B, Reconfigured lanes are used to transmit data traffic; Paragraph 0062, dynamically adjust a number of upstream and/or downstream lines to accommodate traffic flows for connected devices).
Das Sharma does not teach the apparatus comprising: wherein the second link configuration indicates a lane configuration and a generation of signaling for each lane of at least two lanes of the link, including a first lane having a first generation of signaling and a second lane having a second generation of signaling that is different than the first generation of signaling.
Schneider teaches the apparatus comprising: wherein the second link configuration indicates a lane configuration (Lane configuration includes bandwidth configuration and training sets; Paragraph 0045, To scale bandwidth, a link may aggregate multiple lanes denoted by xN, where N is any supported Link width, such as 1, 2, 4, 8, 12, 16, 32, 64, or wider) and a generation of signaling for each lane of at least two lanes (Fig. 5, Link 520 comprises at least one lanes; Paragraph 0058, link connecting a modem and application processor may be bi-directional (e.g., with one lane for sending data from the modem to the application processor (in the upstream direction) and another lane for sending data from the application processor to the modem (in the downstream direction))) of the link (Fig. 5, Each lane is configured with a PCIe Generation 1-5 (i.e. generation of signaling) and a configuration during negotiation; Paragraph 0053, a set of multiple defined link speeds may be supported on the link (e.g., Gen 1, Gen 2, Gen 3, Gen 4, Gen 5 PCIe speeds… over the link 520… Paragraph 0068, link may then be… performing related speed negotiation and training), including a first lane having a first generation of signaling and a second lane having a second generation of signaling that is different than the first generation of signaling (Fig. 5, Link 520 includes an upstream lane that uses a first generation of signaling speed and a downstream lane that uses a second different generation of signaling speed; Paragraph 0058, link speeds may be different in the upstream and downstream directions (e.g., with the modem controlling determination of upstream link speeds, and the application processor controlling determination of the downstream link speed)… Paragraph 0059, a link when using various link speeds… various PCIe generation link speeds (e.g., PCIe Gen 1, PCIe Gen 2, PCIe Gen3, PCIe Gen 4)).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Das Sharma’s apparatus to incorporate the teachings of Schneider and include a PCIe generation signaling configuration of a plurality of lanes in the configuration signal of Das Sharma, wherein an upstream lane is a first generation of signaling speed and a downstream lane is a second generation of signaling speed.
One of ordinary skill in the art would be motivated to make the modifications in order to enable the PCIe communication system to flexibly transition between data rates based on bandwidth requirements, thus improving speed and meeting performance metric requirements (See Schneider: Paragraphs 0002, 0048, 0059, and 0061).
Regarding claim 3, Das Sharma in view of Schneider teaches the apparatus of claim 1. Das Sharma teaches the apparatus comprising wherein at least one lane configuration of the first link configuration is bidirectional and at least one lane configuration of the second link configuration is bidirectional (Fig. 6, Bidirectional lanes 612a and 613a/b can be kept in both first and second link configurations).
Regarding claim 4, Das Sharma in view of Schneider teaches the apparatus of claim 1. Das Sharma teaches the apparatus comprising wherein the link configuration change request includes a first value indicating a first number of lanes of the link configured as a bidirectional lane, a second value indicating a second number of lanes of the link configured as a unidirectional transmit lane, and a third value indicating a third number of lanes of the link configured as a unidirectional receive lane (Page 8, Table 1 shows which lanes are Rx (i.e. unidirectional receive), Tx (i.e. unidirectional transmit), and additional lanes (i.e. bidirectional); Paragraph 0078, Lane 2 612 can form an additional downstream (TX) line 612a from host 602 to device 604).
Regarding claim 5, Das Sharma in view of Schneider teaches the apparatus of claim 1. Das Sharma teaches the apparatus comprising wherein the bus interface is configured to perform further operations comprising: determining a characteristic for a workload of the component, wherein the characteristic indicates at least one of a transmit data rate and a receive data rate on the link (Paragraph 0062, system manager can use bandwidth topology information to dynamically adjust a number of upstream and/or downstream lines to accommodate traffic flows for connected devices that will use more of one type of line (e.g., upstream vs downstream)), and wherein the link configuration change request is based on the characteristic for the workload (Paragraph 0062, If the bandwidth is available on the lines, then the system manager can switch the direction of one or more lines of the multi-lane link to establish the asymmetric interface).
Regarding claim 7, Das Sharma in view of Schneider teaches the apparatus of claim 1. Das Sharma teaches the apparatus comprising a data rate for each lane (Paragraph 0054, data rates of serial interconnects (e.g., PCIe, UPI, USB, etc.) increase, retimers are increasingly used to extend the channel reach).
Schneider teaches the apparatus comprising wherein the second link configuration indicates a data rate for each lane of the at least two lanes of the link (Fig. 5, Each lane is configured with a PCIe Generation 1-5 wherein each Generation has a different data rate speed; Paragraph 0053, a set of multiple defined link speeds may be supported on the link (e.g., Gen 1, Gen 2, Gen 3, Gen 4, Gen 5 PCIe speeds… over the link 520… Paragraph 0068, link may then be… performing related speed negotiation and training).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Das Sharma’s apparatus to incorporate the teachings of Schneider and include a PCIe generation signaling configuration of a plurality of lanes in the configuration signal of Das Sharma, wherein an upstream lane is a first generation of signaling speed and a downstream lane is a second generation of signaling speed.
One of ordinary skill in the art would be motivated to make the modifications in order to enable the PCIe communication system to flexibly transition between data rates based on bandwidth requirements, thus improving speed and meeting performance metric requirements (See Schneider: Paragraphs 0002, 0048, 0059, and 0061).
Regarding claim 8, Das Sharma in view of Schneider teaches the apparatus of claim 1. Das Sharma teaches the apparatus comprising wherein the bus interface comprises a register configured to store a value corresponding to a link configuration for the link (Paragraph 0061, the system manager can set a register in the upstream component 402 and/or in the downstream component 404 to cause each component to recognize the change in a line direction).
Regarding claim 9, Das Sharma in view of Schneider teaches the apparatus of claim 1. Das Sharma teaches the apparatus comprising wherein the bus interface comprises a peripheral component interconnect express (PCIe) interface (Paragraph 0066, the multi-lane link is based on the PCIe protocol, the link in FIG. 5A would be an x4 Link. In this example, the x4 PCIe Link will have 4 Upstream and 4. Downstream Lanes).
Schneider teaches the apparatus comprising the at least one generation of signaling comprises a generation of the peripheral component interconnect express (PCIe) interface for each lane of the at least two lanes of the link (Fig. 5, Link 520 includes an upstream lane that uses a first generation of signaling speed and a downstream lane that uses a second different generation of signaling speed; Paragraph 0058, link speeds may be different in the upstream and downstream directions (e.g., with the modem controlling determination of upstream link speeds, and the application processor controlling determination of the downstream link speed)… Paragraph 0059, a link when using various link speeds… various PCIe generation link speeds (e.g., PCIe Gen 1, PCIe Gen 2, PCIe Gen3, PCIe Gen 4)).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Das Sharma’s apparatus to incorporate the teachings of Schneider and include a PCIe generation signaling configuration of a plurality of lanes in the configuration signal of Das Sharma, wherein an upstream lane is a first generation of signaling speed and a downstream lane is a second generation of signaling speed.
One of ordinary skill in the art would be motivated to make the modifications in order to enable the PCIe communication system to flexibly transition between data rates based on bandwidth requirements, thus improving speed and meeting performance metric requirements (See Schneider: Paragraphs 0002, 0048, 0059, and 0061).
Regarding claim 10, Das Sharma in view of Schneider teaches the apparatus of claim 9. Das Sharma teaches the apparatus comprising wherein the apparatus comprises a PCIe endpoint or a PCIe root complex (Fig. 3, Upstream component 302 is root complex; Paragraph 0048, first component 302, which can be an upstream component, root complex), and the component comprises a PCIe endpoint or a PCIe root complex (Fig. 3, Downstream component 308 is an endpoint; Paragraph 0048, a second component 308, which can be a downstream component, endpoint).
Regarding claim 11, Das Sharma teaches a method, comprising: transmitting a link configuration change request (Figs. 4A & 4B, Host upstream component 402 contains system manager 450 that transmits lane change requests to register of downstream component; Paragraph 0061, system manager can set a register… in the downstream component 404 to cause each component to recognize the change in a line direction) to a component (Figs. 4A & 4B, Device downstream component 404)) through the bus interface (Figs. 4A & 4B, Bus interfaces 412/414; Paragraph 0058, upstream component 402 can include a first downstream port 412 and a first upstream port 414) to reconfigure a link from a first link configuration to a second link configuration (Fig. 8 flowchart, Host upstream component (USP) causes lane directions in link to change in steps 802-816; Paragraph 0090, link width can be adjusted by the host or the device through a register setting indication (816)… desired width in each direction is exchanged and the width decided), wherein the second link configuration indicates a lane configuration for a lane of the link (Fig. 4A shows first link configuration 426 and Fig. 4B shows second link configuration 426 wherein the lane has swapped directions), and wherein the lane configuration indicates a bidirectional lane, a unidirectional transmit lane, or a unidirectional receive lane (Fig. 6 shows configuration of Figs. 4A & 4B with unidirectional transmit lane and unidirectional receive lane in link 611, and a bidirectional lane 612a; Paragraph 0044, Reconfiguration of the lane, such as discussed herein, however, may cause a single lane to be reconfigured into one or more unidirectional lanes… Paragraph 0046, some lanes can be bidirectional lanes); and communicating over the bus interface based on the link configuration change request (Fig. 4B, Reconfigured lanes are used to transmit data traffic; Paragraph 0062, dynamically adjust a number of upstream and/or downstream lines to accommodate traffic flows for connected devices).
Das Sharma does not teach the method comprising: wherein the second link configuration indicates a lane configuration and a generation of signaling for each lane of at least two lanes of the link, including a first lane having a first generation of signaling and a second lane having a second generation of signaling that is different than the first generation of signaling.
Schneider teaches the method comprising: wherein the second link configuration indicates a lane configuration (Lane configuration includes bandwidth configuration and training sets; Paragraph 0045, To scale bandwidth, a link may aggregate multiple lanes denoted by xN, where N is any supported Link width, such as 1, 2, 4, 8, 12, 16, 32, 64, or wider) and a generation of signaling for each lane of at least two lanes (Fig. 5, Link 520 comprises at least one lanes; Paragraph 0058, link connecting a modem and application processor may be bi-directional (e.g., with one lane for sending data from the modem to the application processor (in the upstream direction) and another lane for sending data from the application processor to the modem (in the downstream direction))) of the link (Fig. 5, Each lane is configured with a PCIe Generation 1-5 and a configuration during negotiation; Paragraph 0053, a set of multiple defined link speeds may be supported on the link (e.g., Gen 1, Gen 2, Gen 3, Gen 4, Gen 5 PCIe speeds… over the link 520… Paragraph 0068, link may then be… performing related speed negotiation and training), including a first lane having a first generation of signaling and a second lane having a second generation of signaling that is different than the first generation of signaling (Fig. 5, Link 520 includes an upstream lane that uses a first generation of signaling speed and a downstream lane that uses a second different generation of signaling speed; Paragraph 0058, link speeds may be different in the upstream and downstream directions (e.g., with the modem controlling determination of upstream link speeds, and the application processor controlling determination of the downstream link speed)… Paragraph 0059, a link when using various link speeds… various PCIe generation link speeds (e.g., PCIe Gen 1, PCIe Gen 2, PCIe Gen3, PCIe Gen 4)).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Das Sharma’s method to incorporate the teachings of Schneider and include a PCIe generation signaling configuration of a plurality of lanes in the configuration signal of Das Sharma, wherein an upstream lane is a first generation of signaling speed and a downstream lane is a second generation of signaling speed.
One of ordinary skill in the art would be motivated to make the modifications in order to enable the PCIe communication system to flexibly transition between data rates based on bandwidth requirements, thus improving speed and meeting performance metric requirements (See Schneider: Paragraphs 0002, 0048, 0059, and 0061).
Regarding claim 13, Das Sharma in view of Schneider teaches the method of claim 11. Das Sharma teaches the method comprising wherein at least one lane configuration of the first link configuration is bidirectional and at least one lane configuration of the second link configuration is bidirectional (Fig. 6, Bidirectional lanes 612a and 613a/b can be kept in both first and second link configurations).
Regarding claim 14, Das Sharma in view of Schneider teaches the method of claim 11. Das Sharma teaches the method comprising wherein the link configuration change request includes a first value indicating a first number of lanes of the link configured as a bidirectional lane, a second value indicating a second number of lanes of the link configured as a unidirectional transmit lane, and a third value indicating a third number of lanes of the link configured as a unidirectional receive lane (Page 8, Table 1 shows which lanes are Rx (i.e. unidirectional receive), Tx (i.e. unidirectional transmit), and additional lanes (i.e. bidirectional); Paragraph 0078, Lane 2 612 can form an additional downstream (TX) line 612a from host 602 to device 604).
Regarding claim 15, Das Sharma in view of Schneider teaches the method of claim 11. Das Sharma teaches the method comprising: determining a characteristic for a workload of the component, wherein the characteristic indicates at least one of a transmit data rate and a receive data rate on the link (Paragraph 0062, system manager can use bandwidth topology information to dynamically adjust a number of upstream and/or downstream lines to accommodate traffic flows for connected devices that will use more of one type of line (e.g., upstream vs downstream)), and wherein the link configuration change request is based on the characteristic for the workload (Paragraph 0062, If the bandwidth is available on the lines, then the system manager can switch the direction of one or more lines of the multi-lane link to establish the asymmetric interface).
Regarding claim 17, Das Sharma in view of Schneider teaches the method of claim 11. Das Sharma teaches the method comprising a data rate for each lane (Paragraph 0054, data rates of serial interconnects (e.g., PCIe, UPI, USB, etc.) increase, retimers are increasingly used to extend the channel reach).
Schneider teaches the method comprising wherein the second link configuration indicates a data rate for each lane of the at least two lanes of the link (Fig. 5, Link 520 includes an upstream lane that uses a first generation of signaling speed and a downstream lane that uses a second different generation of signaling speed which are different data rates; Paragraph 0058, link speeds may be different in the upstream and downstream directions (e.g., with the modem controlling determination of upstream link speeds, and the application processor controlling determination of the downstream link speed)… Paragraph 0059, a link when using various link speeds… various PCIe generation link speeds (e.g., PCIe Gen 1, PCIe Gen 2, PCIe Gen3, PCIe Gen 4)).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Das Sharma’s method to incorporate the teachings of Schneider and include a PCIe generation signaling configuration of a plurality of lanes in the configuration signal of Das Sharma, wherein an upstream lane is a first generation of signaling speed and a downstream lane is a second generation of signaling speed.
One of ordinary skill in the art would be motivated to make the modifications in order to enable the PCIe communication system to flexibly transition between data rates based on bandwidth requirements, thus improving speed and meeting performance metric requirements (See Schneider: Paragraphs 0002, 0048, 0059, and 0061).
Regarding claim 18, Das Sharma in view of Schneider teaches the method of claim 11. Das Sharma teaches the method comprising storing a value corresponding to a link configuration for the link in a register (Paragraph 0061, the system manager can set a register in the upstream component 402 and/or in the downstream component 404 to cause each component to recognize the change in a line direction).
Regarding claim 19, Das Sharma in view of Schneider teaches the method of claim 11. Das Sharma teaches the method comprising wherein the bus interface comprises a peripheral component interconnect express (PCIe) interface (Paragraph 0066, the multi-lane link is based on the PCIe protocol, the link in FIG. 5A would be an x4 Link. In this example, the x4 PCIe Link will have 4 Upstream and 4. Downstream Lanes).
Schneider teaches the method comprising the generation of signaling comprises a generation of the peripheral component interconnect express (PCIe) interface for each lane of the at least two lanes of the link (Fig. 5, Link 520 includes an upstream lane that uses a first generation of signaling speed and a downstream lane that uses a second different generation of signaling speed; Paragraph 0058, link speeds may be different in the upstream and downstream directions (e.g., with the modem controlling determination of upstream link speeds, and the application processor controlling determination of the downstream link speed)… Paragraph 0059, a link when using various link speeds… various PCIe generation link speeds (e.g., PCIe Gen 1, PCIe Gen 2, PCIe Gen3, PCIe Gen 4)).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Das Sharma’s method to incorporate the teachings of Schneider and include a PCIe generation signaling configuration of a plurality of lanes in the configuration signal of Das Sharma, wherein an upstream lane is a first generation of signaling speed and a downstream lane is a second generation of signaling speed.
One of ordinary skill in the art would be motivated to make the modifications in order to enable the PCIe communication system to flexibly transition between data rates based on bandwidth requirements, thus improving speed and meeting performance metric requirements (See Schneider: Paragraphs 0002, 0048, 0059, and 0061).
Regarding claim 20, Das Sharma in view of Schneider teaches the method of claim 19. Das Sharma teaches the apparatus comprising wherein the method comprises a PCIe endpoint or a PCIe root complex (Fig. 3, Upstream component 302 is root complex; Paragraph 0048, first component 302, which can be an upstream component, root complex), and the component comprises a PCIe endpoint or a PCIe root complex (Fig. 3, Downstream component 308 is an endpoint; Paragraph 0048, a second component 308, which can be a downstream component, endpoint).
Regarding claim 21, Das Sharma teaches an apparatus (Figs. 4A & 4B, Host upstream component 402), comprising: a bus interface (Figs. 4A & 4B, Bus interfaces 412/414; Paragraph 0058, upstream component 402 can include a first downstream port 412 and a first upstream port 414) configured to couple the apparatus to a component (Figs. 4A & 4B, Device downstream component 404) through a link (Figs. 4A & 4B, PCIe link 422/424/426/428) and configured to perform operations comprising: receiving a link configuration change request (Figs. 4A & 4B, Host upstream component 402 can receive lane change requests to register of downstream component; Paragraph 0090, during link operation, the link width can be adjusted by the host or the device through a register setting indication… desired width in each direction is exchanged and the width decided) from the component through the bus interface to reconfigure the link from a first link configuration to a second link configuration (Fig. 8 flowchart, Host upstream component (USP) causes lane directions in link to change in steps 802-816), wherein the second link configuration indicates a lane configuration for a lane of the link (Fig. 4A shows first link configuration 426 and Fig. 4B shows second link configuration 426 wherein the lane has swapped directions), and wherein the lane configuration indicates a bidirectional lane, a unidirectional transmit lane, or a unidirectional receive lane (Fig. 6 shows configuration of Figs. 4A & 4B with unidirectional transmit lane and unidirectional receive lane in link 611, and a bidirectional lane 612a; Paragraph 0044, Reconfiguration of the lane, such as discussed herein, however, may cause a single lane to be reconfigured into one or more unidirectional lanes… Paragraph 0046, some lanes can be bidirectional lanes); and communicating over the bus interface based on the link configuration change request (Fig. 4B, Reconfigured lanes are used to transmit data traffic; Paragraph 0062, dynamically adjust a number of upstream and/or downstream lines to accommodate traffic flows for connected devices).
Das Sharma does not teach the apparatus comprising: wherein the second link configuration indicates a lane configuration and a generation of signaling for each lane of at least two lanes of the link, including a first lane having a first generation of signaling and a second lane having a second generation of signaling that is different than the first generation of signaling.
Schneider teaches the apparatus comprising: wherein the second link configuration indicates a lane configuration (Lane configuration includes bandwidth configuration and training sets; Paragraph 0045, To scale bandwidth, a link may aggregate multiple lanes denoted by xN, where N is any supported Link width, such as 1, 2, 4, 8, 12, 16, 32, 64, or wider) and a generation of signaling for each lane of at least two lanes (Fig. 5, Link 520 comprises at least one lanes; Paragraph 0058, link connecting a modem and application processor may be bi-directional (e.g., with one lane for sending data from the modem to the application processor (in the upstream direction) and another lane for sending data from the application processor to the modem (in the downstream direction))) of the link (Fig. 5, Each lane is configured with a PCIe Generation 1-5 and a configuration during negotiation; Paragraph 0053, a set of multiple defined link speeds may be supported on the link (e.g., Gen 1, Gen 2, Gen 3, Gen 4, Gen 5 PCIe speeds… over the link 520… Paragraph 0068, link may then be… performing related speed negotiation and training), including a first lane having a first generation of signaling and a second lane having a second generation of signaling that is different than the first generation of signaling (Fig. 5, Link 520 includes an upstream lane that uses a first generation of signaling speed and a downstream lane that uses a second different generation of signaling speed; Paragraph 0058, link speeds may be different in the upstream and downstream directions (e.g., with the modem controlling determination of upstream link speeds, and the application processor controlling determination of the downstream link speed)… Paragraph 0059, a link when using various link speeds… various PCIe generation link speeds (e.g., PCIe Gen 1, PCIe Gen 2, PCIe Gen3, PCIe Gen 4)).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Das Sharma’s apparatus to incorporate the teachings of Schneider and include a PCIe generation signaling configuration of a plurality of lanes in the configuration signal of Das Sharma, wherein an upstream lane is a first generation of signaling speed and a downstream lane is a second generation of signaling speed.
One of ordinary skill in the art would be motivated to make the modifications in order to enable the PCIe communication system to flexibly transition between data rates based on bandwidth requirements, thus improving speed and meeting performance metric requirements (See Schneider: Paragraphs 0002, 0048, 0059, and 0061).
Regarding claim 23, Das Sharma in view of Schneider teaches the apparatus of claim 21. Das Sharma teaches the apparatus comprising wherein at least one lane configuration of the first link configuration is bidirectional and at least one lane configuration of the second link configuration is bidirectional (Fig. 6, Bidirectional lanes 612a and 613a/b can be kept in both first and second link configurations).
Regarding claim 24, Das Sharma in view of Schneider teaches the apparatus of claim 21. Das Sharma teaches the apparatus comprising wherein the link configuration change request includes a first value indicating a first number of lanes of the link configured as a bidirectional lane, a second value indicating a second number of lanes of the link configured as a unidirectional transmit lane, and a third value indicating a third number of lanes of the link configured as a unidirectional receive lane (Page 8, Table 1 shows which lanes are Rx (i.e. unidirectional receive), Tx (i.e. unidirectional transmit), and additional lanes (i.e. bidirectional); Paragraph 0078, Lane 2 612 can form an additional downstream (TX) line 612a from host 602 to device 604).
Regarding claim 25, Das Sharma in view of Schneider teaches the apparatus of claim 21. Das Sharma teaches the apparatus comprising wherein the bus interface comprises a register configured to store a value corresponding to a link configuration for the link (Paragraph 0061, the system manager can set a register in the upstream component 402 and/or in the downstream component 404 to cause each component to recognize the change in a line direction), the bus interface comprises a peripheral component interconnect express (PCIe) interface (Paragraph 0066, the multi-lane link is based on the PCIe protocol, the link in FIG. 5A would be an x4 Link. In this example, the x4 PCIe Link will have 4 Upstream and 4. Downstream Lanes), and the component comprises a PCIe endpoint or a PCIe root complex (Fig. 3, Downstream component 308 is an endpoint; Paragraph 0048, a second component 308, which can be a downstream component, endpoint).
Regarding claim 26, Das Sharma teaches a method, comprising: receiving a link configuration change request (Figs. 4A & 4B, Host upstream component 402 can receive lane change requests to register of downstream component; Paragraph 0090, during link operation, the link width can be adjusted by the host or the device through a register setting indication… desired width in each direction is exchanged and the width decided) from a component (Figs. 4A & 4B, Device downstream component 404)) through the bus interface (Figs. 4A & 4B, Bus interfaces 412/414; Paragraph 0058, upstream component 402 can include a first downstream port 412 and a first upstream port 414) to reconfigure a link from a first link configuration to a second link configuration (Fig. 8 flowchart, Host upstream component (USP) causes lane directions in link to change in steps 802-816; Paragraph 0090, link width can be adjusted by the host or the device through a register setting indication (816)… desired width in each direction is exchanged and the width decided), wherein the second link configuration indicates a lane configuration for a lane of the link (Fig. 4A shows first link configuration 426 and Fig. 4B shows second link configuration 426 wherein the lane has swapped directions), and wherein the lane configuration indicates a bidirectional lane, a unidirectional transmit lane, or a unidirectional receive lane (Fig. 6 shows configuration of Figs. 4A & 4B with unidirectional transmit lane and unidirectional receive lane in link 611, and a bidirectional lane 612a; Paragraph 0044, Reconfiguration of the lane, such as discussed herein, however, may cause a single lane to be reconfigured into one or more unidirectional lanes… Paragraph 0046, some lanes can be bidirectional lanes); and communicating over the bus interface based on the link configuration change request (Fig. 4B, Reconfigured lanes are used to transmit data traffic; Paragraph 0062, dynamically adjust a number of upstream and/or downstream lines to accommodate traffic flows for connected devices).
Das Sharma does not teach the method comprising: wherein the second link configuration indicates a lane configuration and a generation of signaling for each lane of at least two lanes of the link, including a first lane having a first generation of signaling and a second lane having a second generation of signaling that is different than the first generation of signaling.
Schneider teaches the method comprising: wherein the second link configuration indicates a lane configuration (Lane configuration includes bandwidth configuration and training sets; Paragraph 0045, To scale bandwidth, a link may aggregate multiple lanes denoted by xN, where N is any supported Link width, such as 1, 2, 4, 8, 12, 16, 32, 64, or wider) and a generation of signaling for each lane of at least two lanes (Fig. 5, Link 520 comprises at least one lanes; Paragraph 0058, link connecting a modem and application processor may be bi-directional (e.g., with one lane for sending data from the modem to the application processor (in the upstream direction) and another lane for sending data from the application processor to the modem (in the downstream direction))) of the link (Fig. 5, Each lane is configured with a PCIe Generation 1-5 and a configuration during negotiation; Paragraph 0053, a set of multiple defined link speeds may be supported on the link (e.g., Gen 1, Gen 2, Gen 3, Gen 4, Gen 5 PCIe speeds… over the link 520… Paragraph 0068, link may then be… performing related speed negotiation and training), including a first lane having a first generation of signaling and a second lane having a second generation of signaling that is different than the first generation of signaling (Fig. 5, Link 520 includes an upstream lane that uses a first generation of signaling speed and a downstream lane that uses a second different generation of signaling speed; Paragraph 0058, link speeds may be different in the upstream and downstream directions (e.g., with the modem controlling determination of upstream link speeds, and the application processor controlling determination of the downstream link speed)… Paragraph 0059, a link when using various link speeds… various PCIe generation link speeds (e.g., PCIe Gen 1, PCIe Gen 2, PCIe Gen3, PCIe Gen 4)).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Das Sharma’s method to incorporate the teachings of Schneider and include a PCIe generation signaling configuration of a plurality of lanes in the configuration signal of Das Sharma, wherein an upstream lane is a first generation of signaling speed and a downstream lane is a second generation of signaling speed.
One of ordinary skill in the art would be motivated to make the modifications in order to enable the PCIe communication system to flexibly transition between data rates based on bandwidth requirements, thus improving speed and meeting performance metric requirements (See Schneider: Paragraphs 0002, 0048, 0059, and 0061).
Regarding claim 28, Das Sharma in view of Schneider teaches the method of claim 26. Das Sharma teaches the method comprising wherein at least one lane configuration of the first link configuration is bidirectional and at least one lane configuration of the second link configuration is bidirectional (Fig. 6, Bidirectional lanes 612a and 613a/b can be kept in both first and second link configurations).
Regarding claim 29, Das Sharma in view of Schneider teaches the method of claim 26. Das Sharma teaches the method comprising wherein the link configuration change request includes a first value indicating a first number of lanes of the link configured as a bidirectional lane, a second value indicating a second number of lanes of the link configured as a unidirectional transmit lane, and a third value indicating a third number of lanes of the link configured as a unidirectional receive lane (Page 8, Table 1 shows which lanes are Rx (i.e. unidirectional receive), Tx (i.e. unidirectional transmit), and additional lanes (i.e. bidirectional); Paragraph 0078, Lane 2 612 can form an additional downstream (TX) line 612a from host 602 to device 604).
Regarding claim 30, Das Sharma in view of Schneider teaches the method of claim 26. Das Sharma teaches the method comprising storing a value corresponding to a link configuration for the link in a register (Paragraph 0061, the system manager can set a register in the upstream component 402 and/or in the downstream component 404 to cause each component to recognize the change in a line direction), the bus interface comprises a peripheral component interconnect express (PCIe) interface (Paragraph 0066, the multi-lane link is based on the PCIe protocol, the link in FIG. 5A would be an x4 Link. In this example, the x4 PCIe Link will have 4 Upstream and 4. Downstream Lanes), and the component comprises a PCIe endpoint or a PCIe root complex (Fig. 3, Downstream component 308 is an endpoint; Paragraph 0048, a second component 308, which can be a downstream component, endpoint).
Claims 6 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Das Sharma (US 2019/0042524) in view of Schneider (US 2019/0121417) and further in view of Kopzon (US 2019/0050365).
Regarding claim 6, Das Sharma in view of Schneider teaches the apparatus of claim 1. Das Sharma teaches the apparatus comprising wherein: transmitting the link configuration change request comprises: transmitting a lane weight redistribution request to the component (Paragraph 0090, during link operation, the link width can be adjusted by the host or the device through a register setting indication (816)… desired width in each direction is exchanged and the width decided); and reconfiguring the link with a new lane weight distribution according to the second link configuration (Paragraph 0090, link can undergo the link training procedure previously described (818); the multi-lane link can then be initialized (e.g., in a default state) (814)), and the communicating over the link based on the link configuration change request is after the reconfiguring the link (Fig. 4B, Reconfigured lanes are used to transmit data traffic; Paragraph 0062, dynamically adjust a number of upstream and/or downstream lines to accommodate traffic flows for connected devices that will use more of one type of line (e.g., upstream vs downstream)).
Neither Das Sharma nor Schneider teaches the apparatus comprising receiving an acknowledge of the lane weight redistribution request from the component.
Kopzon teaches the apparatus comprising receiving an acknowledge of the lane weight redistribution request from the component (Fig. 4, Acknowledgement is received at step 418 after links are switched at step 412; Paragraph 0057, system manager can perform connection set-up procedures, and other lane initialization steps to facilitate the use of the switched direction lanes for transmission or reception… system manager can receive an acknowledgement of initialization of the switched lanes from the connected device (418)).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Das Sharma/Schneider’s apparatus to incorporate the teachings of Kopzon and include acknowledgement responses to link configuration requests.
One of ordinary skill in the art would be motivated to make the modifications in order to enable the host to diagnose link configuration issues, thus preventing PCIe communication errors (See Kopzon: Paragraph 0063).
Regarding claim 16, Das Sharma in view of Schneider teaches the method of claim 11. Das Sharma teaches the method comprising wherein: transmitting the link configuration change request comprises: transmitting a lane weight redistribution request to the component (Paragraph 0090, during link operation, the link width can be adjusted by the host or the device through a register setting indication (816)… desired width in each direction is exchanged and the width decided); and reconfiguring the link with a new lane weight distribution according to the second link configuration (Paragraph 0090, link can undergo the link training procedure previously described (818); the multi-lane link can then be initialized (e.g., in a default state) (814)), and the communicating over the link based on the link configuration change request is after the reconfiguring the link (Fig. 4B, Reconfigured lanes are used to transmit data traffic; Paragraph 0062, dynamically adjust a number of upstream and/or downstream lines to accommodate traffic flows for connected devices that will use more of one type of line (e.g., upstream vs downstream)).
Neither Das Sharma nor Schneider teaches the method comprising receiving an acknowledge of the lane weight redistribution request from the component.
Kopzon teaches the method comprising receiving an acknowledge of the lane weight redistribution request from the component (Fig. 4, Acknowledgement is received at step 418 after links are switched at step 412; Paragraph 0057, system manager can perform connection set-up procedures, and other lane initialization steps to facilitate the use of the switched direction lanes for transmission or reception… system manager can receive an acknowledgement of initialization of the switched lanes from the connected device (418)).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Das Sharma/Schneider’s method to incorporate the teachings of Kopzon and include acknowledgement responses to link configuration requests.
One of ordinary skill in the art would be motivated to make the modifications in order to enable the host to diagnose link configuration issues, thus preventing PCIe communication errors (See Kopzon: Paragraph 0063).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US PGPUB 2020/0371579 to Selvam discloses that a PCIe link comprises multiple PCIe lanes which are configured with a transfer speed per lane using Gen1-4 PCIe speeds (Paragraph 0048, link 285 may support multiple link speeds corresponding to different generations (“GENs”) of the PCIe standard. In this regard, Table 1 below lists an exemplary transfer speed per lane per direction for a GEN1 speed, a GEN2 speed, a GEN3 speed, a GEN4 speed and GENS speed).
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/H.Z.W./Examiner, Art Unit 2184
/HENRY TSAI/Supervisory Patent Examiner, Art Unit 2184