DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 06/04/2026 have been fully considered but they are not persuasive. Applicant argues that the vias of Yen are not vias that bracket a volume of silicon in a semiconductor substrate. Applicant alleges that the inductor structure, including the metal layers and the vias are formed on the substrate, and the inductor structure comprises an air-core or dielectric core element. Applicant also argues that Yen does not teach the staggered vis interconnection pattern as claimed. Applicant asserts that the metal layers of Yen do not comprise one right angle turn or more than one right-angle turns.
After careful consideration without passion or prejudice, the argument is not found persuasive, respectfully. While the inductor structure 20 of Yen is formed over substrate 26, the examiner does not equate this substrate 26 as the claimed “semiconductor substrate.” The inductor structure 20 is formed in “die/wafer” (para. [0013]). The inductor structure 20 in Fig. 2 comprises metal layers M1-Mtop, which includes vias 102. The inductor structure 20 in “die/wafter” as disclosed in paragraph [0013] is also applicable in the applied Fig. 4 of Yen. In Fig. 4, the inductor structure 20 comprises P1-P4, including columns 104, and the inductor structure 20 of Fig. 4 is formed in “die/wafter” (the claimed “semiconductor substrate”) as described in paragraph [0013]). Therefore, these vias 102 (Fig. 2) and or columns 104 (Fig. 4), which are parts of the inductor structure 20, are “in a semiconductor substrate” as claimed.
In this field of art, any material surrounded by the inductor structure is known as “core” which is equivalent to “volume of core material” as recited in claim 1 and similar limitations in claims 10 and 14. For discussion purpose, even if the inductor structure of Yen comprises air-core or dielectric core element as argued (the examiner does not agree), air is made up of matters (e.g., nitrogen, oxygen, carbon dioxide, etc.) and has volume. So, air is still a “material” as claimed. Similarly, dielectric element is still a material. Therefore, Yen teaches “the vias bracket a volume of core material” as recited in claim 1 and similar limitation in claim 10. In Yen, the “die/wafter” core material is a semiconductor material. Therefore, Yen meets “a volume of core material” as recited in claim 1, “a volume of substrate material” as claimed in claim 10, and “a volume of semiconductor substrate” as required by claim 14.
The right-angled traces 103 in FIG. 4 of the present invention is similar to the right-angled trace 100 Yen. Therefore, the examiner maintains Yen teaches “staggered right-angled traces” as claimed. In addition, the originally filed specification does not even disclose “staggered right-angled traces” as amended on 12/17/2025. Accordingly, it’s maintained that Yen anticipates claims 1, 10 and 14 as currently recited. The “more than one right-angle turns” argument is moot because the claims reflecting that limitations are withdrawn.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-6, 10-18 and 21 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yen et al. (U.S. PG. Pub. No. 2017/0140867 A1).
With respect to claim 1, Yen et al., hereinafter referred to as “Yen,” teaches a method (method of forming an inductor 20, FIGs. 4-5D) comprising:
forming a plurality of vias 102 in a semiconductor substrate (“die/wafer” between metal layers M1 and Mtop, in which the inductor 20 is formed para. [0013]) that the vias bracket a volume (substrate volume between left and right vias 102) of core material (substrate material between left and right vias); and
configuring staggered right-angled traces (upper traces 100 having right-angled bent 100a, annotated Fig. 4) between top pads (upper end surface) of the vias and forming traces (lower traces 100) between bottom pads (lower end surface) of the vias to form a continuous path for current to flow circumferentially from a first end (end around port 22 or 24) of the core material to a second end (end around the other of port 22 or 24) of the core material (paras. [0021]-[0023]).
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With respect to claim 2, Yen teaches the method of claim 1, wherein the vias are formed into two parallel rows (para. [0021]).
With respect to claim 3, Yen teaches the method of claim 1, wherein the volume of core material is a prism (imaginary rectangular prism surrounded by the inductor 20) (para. [0021]).
With respect to claim 4, Yen teaches the method of claim 1, wherein the volume of core material is a rectangular volume (imaginary rectangular volume surrounded by the inductor 20) (para. [0021]).
With respect to claim 5, Yen teaches the method of claim 1, wherein the vias have a regular spacing (para. [0021]).
With respect to claim 6, Yen teaches the method of claim 1, wherein the staggered right-angled traces each comprise exactly one right-angle turn (para. [0021]).
With respect to claim 10, Yen teaches a semiconductor substrate (substrate of inductor 20, FIGs. 4-5D) comprising:
a volume of substrate material (substrate material between two columns of left and right vias 102) bordered by two rows of vias (left and right vias 102); and
staggered and right-angled metal traces 100 configured between the vias to form a coil (coil of inductor 20) along a length (length in axial direction) of the volume of substrate material (paras. [0021]-[0023]).
With respect to claim 11, Yen teaches the semiconductor substrate of claim 10, wherein the vias are evenly spaced in parallel rows (para. [0121]).
With respect to claim 12, Yen teaches the semiconductor substrate of claim 10, wherein the volume of substrate is rectangular (imaginary rectangular volume surrounded by the inductor 20) (para. [0021]).
With respect to claim 13, Yen teaches the semiconductor substrate of claim 10, wherein the metal traces each comprise exactly one right-angle (para. [0021])[.]
With respect to claim 14, Yen teaches the an inductor 20 (FIGs. 4-5D) comprising:
a plurality of vias 102 bracketing volume (volume between left and right vias 102) of semiconductor substrate (“die/wafer” between metal layers M1 and Mtop, in which the inductor 20 is formed para. [0013]), each via comprising a top metal pad (upper end surface) and a bottom metal pad (lower end surface); and
the vias alternately connected by way of staggered right-angled metal traces (upper traces 100 having right-angled bent 100a, annotated Fig. 4) between the top metal pads and traces (lower traces 100) between the bottom metal pads to form an end-to-end current loop along a length (length in axial direction) of the volume of semiconductor substrate (paras. [0021]-[0023]).
With respect to claim 15, Yen teaches the inductor of claim 14, wherein the vias are arranged in two parallel rows (para. [0021]).
With respect to claim 16, Yen teaches the inductor of claim 15, wherein the vias in each row have a regular spacing (para. [0021]).
With respect to claim 17, Yen teaches the inductor of claim 14, wherein the volume of core material is a rectangular prism (imaginary rectangular prism surrounded by the inductor 20) (para. [0021]).
With respect to claim 18, Yen teaches the inductor of claim 14, wherein the staggered right-angled metal traces between the top metal pads each comprise exactly one right-angle (para. [0021]).
With respect to claim 21, Yen teaches the method of claim 1, wherein the traces between the bottom pads of the vias are backside metal traces (para. [0021]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 7-9, 20 and 24 are rejected under 35 U.S.C. 103 as being unpatentable over Yen, as applied to claims 1 and 10 above, in view of Leigh et al. (U.S. Patent No. 5,821,846).
With respect to claim 7, Yen teaches the method of claim 1. Yen does not expressly teach the vias are grouped into via clusters.
Leigh et al., hereinafter referred to as “Leigh,” teaches a method (method to form an inductor 20, Fig. 20), wherein the vias 52 and 44 are grouped into via clusters (col. 5, lines 55-58 and col. 6, lines 12-14). It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to have the via clusters as taught by Leigh to the method of Yen to provide a device/inductor that can carry high current (col. 2, lines 27-31).
With respect to claim 8, Yen in view of Leigh teaches the method of claim 7, wherein the via clusters consist of pairs of vias (Leigh, col. 5, lines 55-58 and col. 6, lines 12-14).
With respect to claim 9, Yen teaches the method of claim 7, wherein the via clusters consist of quads of vias (Leigh, col. 5, lines 55-58 and col. 6, lines 12-14).
With respect to claim 20, Yen teaches the method of claim 1. Yen does not expressly teach wherein the vias are via clusters.
Leigh teaches a method (method to form an inductor 20, Fig. 20), wherein the vias 52 and 44 are via clusters (col. 5, lines 55-58 and col. 6, lines 12-14). It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to have the via clusters as taught by Leigh to the method of Yen to provide a device/inductor that can carry high current (col. 2, lines 27-31).
With respect to claim 24, Yen teaches the semiconductor substrate of claim 10. Yen does not expressly teach each of the vias consists of a quad.
Leigh teaches a substrate (Fig. 20), wherein the vias 52 and 44 consist of a quad (col. 5, lines 55-58 and col. 6, lines 12-14). It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to have the quad vias as taught by Leigh to the semiconductor substrate of Yen to provide a device/inductor that can carry high current (col. 2, lines 27-31).
Claims 19 and 25 are rejected under 35 U.S.C. 103 as being unpatentable over Yen, as applied to claims 18 and 10 above, and further in view of Lee et al. (U.S. Patent No. 6,856,003 B2).
With respect to claim 19, Yen teaches the inductor of claim 18. Yen does not expressly teach the traces are stacked traces.
Lee et al., hereinafter referred to as “Lee,” teaches an inductor 20 (FIG. 1A), wherein the traces 11 and 12 are stacked traces (col. 5, lines 31-34). It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to have the stacked traces as taught by Lee to the inductor of Yen to reduce current density.
With respect to claim 25, Yen teaches the semiconductor substrate of claim 10. Yen does not expressly teach the metal traces are triple stacked.
Lee teaches a semiconductor substrate (FIG. 1A), wherein the metal traces 11 and 12 are stacked traces (col. 5, lines 31-34). Lee does not expressly teach the metal traces are triple stacked. However, it would be within the skill of a person with ordinary skill in the art to use triple stacked traces, based on Lee’s double stacked metal traces, to provide the required electrical characteristics. Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to use the triple stacked metal traces as claimed, as would have been obvious over Lee, to reduce current density to meet design requirements.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MANGTIN LIAN whose telephone number is (571)270-5729. The examiner can normally be reached Monday-Friday 0800-1700.
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/MANG TIN BIK LIAN/ Primary Examiner, Art Unit 2837
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