DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Final Office Action is in response to the Amendment Request/REMARKS correspondence filed 10/20/2025.
Claims 1-34, & 36-37 are pending and rejected.
Response to Arguments
Applicant’s arguments, see REMARKS/Applicant Arguments, filed 10/20/2025, with respect to the rejection(s) of previous claims 1-35 under 35 USC 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of claim amendments which warranted further search and inquiry.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1, 10 & 13 are rejected under 35 U.S.C. 103 as being unpatentable over Paramesh et al (US11569897B2) in view of Moshfeghi (US11075723B2).
Regarding claim 1, Paramesh teaches a component chip for wireless communication comprising:
a set of one or more frequency domain components configured to receive and process a set of spatial streams in a frequency domain resulting in a subset of processed frequency domain spatial streams (col 3 lines 55-67, col 12 lines 2-19, repeatedly describes multi-layer hybrid architectures with a first processing layer handling all streams and later layers operating under tighter constraints, which is consistent with an upstream frequency-domain stage size for N streams), wherein the one or more frequency domain components are capable of receiving and processing a maximum quantity of N spatial streams (col 3 lines 55-67, col 12 lines 2-19, repeatedly describes multi-layer hybrid architectures with a first processing layer handling all streams and later layers operating under tighter constraints, which is consistent with an upstream frequency-domain stage size for N streams),
But Paramesh fails to teach and wherein a quantity of processed frequency domain spatial streams in the subset of processed frequency domain spatial streams is equal to half of the quantity of spatial streams in the set of spatial streams;
a frequency-to-time domain mapping component configured to obtain the subset of processed frequency domain spatial streams from the set of one or more frequency domain components and to map the subset of processed frequency domain spatial streams from the frequency domain to a time domain resulting in a subset of time domain spatial streams;
a set of one or more time domain components configured to process the subset of time domain spatial streams resulting in a subset of processed time domain spatial streams, the set of one or more time domain components being further configured to transmit the subset of processed time domain spatial streams, wherein the one or more time domain components are capable of processing and transmitting a maximum quantity of N/2 spatial streams; and
one or more medium access control (MAC) components configured to transmit or receive, via an interface, synchronization information to or from one or more other MAC components of one or more additional component chips.
However, Moshfeghi teaches and wherein a quantity of processed frequency domain spatial streams in the subset of processed frequency domain spatial streams is equal to half of the quantity of spatial streams in the set of spatial streams (col 12 lines 62-67, col 16 lines 40-58, portion of the distributed transceivers…are activated and other transceivers are switched off for power saving, the network management engine…determine the number of transceivers that are activated; teaches selecting and activating only a subset of available stream-handling resources);
a frequency-to-time domain mapping component configured to obtain the subset of processed frequency domain spatial streams from the set of one or more frequency domain components and to map the subset of processed frequency domain spatial streams from the frequency domain to a time domain resulting in a subset of time domain spatial streams (Abstract, col 11 lines 53-67, col 14-15 lines 63-67 & lines 1-2, OFDM requires frequency domain processing (subcarriers) and frequency-to-time-domain conversion (IFFT), which directly supported the claimed frequency-to-time domain mapping component; convert the coded data streams…into different corresponding IF bands…[and] further convert…into the same RF band—which supports the presence of explicit mapping stages between domains, reinforcing the claimed functional block that converts processed frequency-domain streams into time-domain signals for transmission);
a set of one or more time domain components configured to process the subset of time domain spatial streams resulting in a subset of processed time domain spatial streams, the set of one or more time domain components being further configured to transmit the subset of processed time domain spatial streams, wherein the one or more time domain components are capable of processing and transmitting a maximum quantity of N/2 spatial streams (Abstract, col 9 lines 8-15, col 12-13 lines 62-67 & 1-2 respectively, each of the coded data streams…may be concurrently transmitted, only a portion of the distributed transceivers…are activated, teaches that only a subset of streams are actually transmitted, based on resource limits); and
one or more medium access control (MAC) components configured to transmit or receive, via an interface, synchronization information to or from one or more other MAC components of one or more additional component chips (col 5 lines 13-22, col 12 lines 17-35, col 16 lines 40-58, MAC-layer protocols, control channels/interfaces, distributed/multi-component coordination, teaches distributed components, interfaces, and control/synchronization signaling across components and chips, satisfying the claimed MAC-to-MAC synchronization exchange via an interface).
Paramesh teaches a multi-layer MIMO architecture in which frequency-domain (spatio-spectral) processing supports multiple spatial streams up to a maximum capacity N, while downstream layers operate under tighter constraints. Moshfeghi teaches distributed transceiver systems with explicit OFDM frequency-domain processing, frequency-to-time domain conversion, selective activation of only a subset of available stream paths, and control-channel/interface signaling among distributed components including MAC-layer protocols. It would have been obvious to a person of ordinary skill in the art before the effective filing date, to combine these teachings to process N spatial streams in a frequency-domain stage, select and forward a reduced subset-such as one-half-to a time-domain transmit stage limited to N/2 streams, and to coordinate operation via inter-component MAC synchronization interfaces, in order to balance throughput, power consumptions, and hardware complexity.
Regarding claim 10, Paramesh teaches the component chip wherein the set of one or more frequency domain components are configured to process a quantity of spatial streams that is equal to a quantity of spatial streams that the set of one or more time domain components are configured to receive (col 3 lines 55-67, col 12 lines 2-19, repeatedly describes multi-layer hybrid architectures with a first processing layer handling all streams and later layers operating under tighter constraints, which is consistent with an upstream frequency-domain stage size for N streams).
Regarding claim 13, Paramesh teaches a component chip for wireless communication comprising:
a set of one or more time domain components configured to receive and process a first subset of a set of spatial streams in a time domain resulting in a subset of processed time domain spatial streams, wherein the one or more time domain components are capable of processing and receiving a maximum quantity of N/2 spatial streams (col 3 lines 55-67, col 12 lines 2-19, repeatedly describes multi-layer hybrid architectures with a first processing layer handling all streams and later layers operating under tighter constraints, which is consistent with an upstream frequency-domain stage size for N streams);
a time-to-frequency domain mapping component, the time-to-frequency domain mapping component configured to receive the subset of processed time domain spatial streams from the set of one or more time domain components and to map the subset of processed time domain spatial streams from the time domain to the frequency domain resulting in a subset of frequency domain spatial streams (col 3 lines 55-67, col 12 lines 2-19, repeatedly describes multi-layer hybrid architectures with a first processing layer handling all streams and later layers operating under tighter constraints, which is consistent with an upstream frequency-domain stage size for N streams);
But Paramesh fails to teach a set of one or more frequency domain components that are configured to receive and process the subset of frequency domain spatial streams and to receive a second subset of the set of spatial streams from one or more additional component chips, wherein the one or more frequency domain components are capable of receiving and processing a maximum quantity of N spatial streams; and
one or more medium access control (MAC) component configured to transmit or receive, via an interface, synchronization information to or from one or more other MAC components of the one or more additional component chips.
However, Moshfeghi teaches a set of one or more frequency domain components that are configured to receive and process the subset of frequency domain spatial streams and to receive a second subset of the set of spatial streams from one or more additional component chips, wherein the one or more frequency domain components are capable of receiving and processing a maximum quantity of N spatial streams (Abstract, col 11 lines 53-67, col 14-15 lines 63-67 & lines 1-2, OFDM requires frequency domain processing (subcarriers) and frequency-to-time-domain conversion (IFFT), which directly supported the claimed frequency-to-time domain mapping component; convert the coded data streams…into different corresponding IF bands…[and] further convert…into the same RF band—which supports the presence of explicit mapping stages between domains, reinforcing the claimed functional block that converts processed frequency-domain streams into time-domain signals for transmission); and
one or more medium access control (MAC) component configured to transmit or receive, via an interface, synchronization information to or from one or more other MAC components of the one or more additional component chips (col 5 lines 13-22, col 12 lines 17-35, col 16 lines 40-58, MAC-layer protocols, control channels/interfaces, distributed/multi-component coordination, teaches distributed components, interfaces, and control/synchronization signaling across components and chips, satisfying the claimed MAC-to-MAC synchronization exchange via an interface).
Paramesh teaches a multi-layer MIMO architecture in which frequency-domain (spatio-spectral) processing supports multiple spatial streams up to a maximum capacity N, while downstream layers operate under tighter constraints. Moshfeghi teaches distributed transceiver systems with explicit OFDM frequency-domain processing, frequency-to-time domain conversion, selective activation of only a subset of available stream paths, and control-channel/interface signaling among distributed components including MAC-layer protocols. It would have been obvious to a person of ordinary skill in the art before the effective filing date, to combine these teachings to process N spatial streams in a frequency-domain stage, select and forward a reduced subset-such as one-half-to a time-domain transmit stage limited to N/2 streams, and to coordinate operation via inter-component MAC synchronization interfaces, in order to balance throughput, power consumptions, and hardware complexity.
Regarding claim 36, Paramesh fails to teach the component chip wherein the one or more MAC components comprise one or more MAC layer processors.
However, Moshfeghi teaches the component chip wherein the one or more MAC components comprise one or more MAC layer processors (col 5 lines 13-22, col 12 lines 17-35, col 16 lines 40-58, MAC-layer protocols, control channels/interfaces, distributed/multi-component coordination, teaches distributed components, interfaces, and control/synchronization signaling across components and chips, satisfying the claimed MAC-to-MAC synchronization exchange via an interface).
Paramesh teaches a multi-layer MIMO architecture in which frequency-domain (spatio-spectral) processing supports multiple spatial streams up to a maximum capacity N, while downstream layers operate under tighter constraints. Moshfeghi teaches distributed transceiver systems with explicit OFDM frequency-domain processing, frequency-to-time domain conversion, selective activation of only a subset of available stream paths, and control-channel/interface signaling among distributed components including MAC-layer protocols. It would have been obvious to a person of ordinary skill in the art before the effective filing date, to combine these teachings to process N spatial streams in a frequency-domain stage, select and forward a reduced subset-such as one-half-to a time-domain transmit stage limited to N/2 streams, and to coordinate operation via inter-component MAC synchronization interfaces, in order to balance throughput, power consumptions, and hardware complexity.
Regarding claim 37, Paramesh fails to teach the component chip wherein the interface is a serial interface.
However, Moshfeghi teaches teach the component chip wherein the interface is a serial interface (col 5 lines 1-15, one or more digital connections or interfaces between the baseband processor…and the distributed transceivers”, Ethernet, PHY side is serialized etc.).
Paramesh teaches a multi-layer MIMO architecture in which frequency-domain (spatio-spectral) processing supports multiple spatial streams up to a maximum capacity N, while downstream layers operate under tighter constraints. Moshfeghi teaches distributed transceiver systems with explicit OFDM frequency-domain processing, frequency-to-time domain conversion, selective activation of only a subset of available stream paths, and control-channel/interface signaling among distributed components including MAC-layer protocols. It would have been obvious to a person of ordinary skill in the art before the effective filing date, to combine these teachings to process N spatial streams in a frequency-domain stage, select and forward a reduced subset-such as one-half-to a time-domain transmit stage limited to N/2 streams, and to coordinate operation via inter-component MAC synchronization interfaces, in order to balance throughput, power consumptions, and hardware complexity.
Claims 2-9, 11-12, & 14-21 are rejected under 35 U.S.C. 103 as being unpatentable over Paramesh in view of Moshfeghi as applied to claim 1 above, and further in view of Tolga et al (TW202228409A).
Regarding claim 2, Paramesh and Moshfeghi fail to teach the component chip wherein the component chip is configured to provide, to the one or more additional component chips, one or more additional subsets of the set of spatial streams not included in the subset of processed frequency domain spatial streams, wherein each of the one or more additional component chips is configured to transmit a respective subset of spatial streams.
However, Tolga teaches the component chip wherein the component chip is configured to provide, to the one or more additional component chips (English translation, pg. 3-4 paragraphs 3-17 & paragraphs 1-17, the disclosure describes chiplets (components) that be interconnected via wireless or wired interfaces (EMIBs, , TSVs) in multi-chip modules (MCMs). The reference to components communicating wirelessly or via substrate interconnects is coordination and data transfer which is providing synchronization information or subsets of data (spatial streams) to other chiplets); which supports a structure where one chiplet provides information or partial data streams to others for distributed transmission), to the one or more additional component chips, one or more additional subsets of the set of spatial streams not included in the subset of processed frequency domain spatial streams, wherein each of the one or more additional component chips is configured to transmit a respective subset of spatial streams (English translation, pg. 3-4 paragraphs 3-17 & paragraphs 1-17, the disclosure describes chiplets (components) that be interconnected via wireless or wired interfaces (EMIBs, , TSVs) in multi-chip modules (MCMs). The reference to components communicating wirelessly or via substrate interconnects is coordination and data transfer which is providing synchronization information or subsets of data (spatial streams) to other chiplets); which supports a structure where one chiplet provides information or partial data streams to others for distributed transmission).
Paramesh teaches a multi-layer MIMO architecture in which frequency-domain (spatio-spectral) processing supports multiple spatial streams up to a maximum capacity N, while downstream layers operate under tighter constraints. Moshfeghi teaches distributed transceiver systems with explicit OFDM frequency-domain processing, frequency-to-time domain conversion, selective activation of only a subset of available stream paths, and control-channel/interface signaling among distributed components including MAC-layer protocols. Furthermore, Tolga teaches modular, multi-chiplet architectures includes 2D-3D heterogenous integration with wired and wireless die-to-die communication. This architecture addresses performance, density, and power concerns by stacking and interconnecting multiple dielets or chiplets using TSVs, EMIBs, and WC2C (wireless chip-to-chip) technology. It would have been obvious to a person of ordinary skill in the art before the effective filing date, to combine these teachings to process N spatial streams in a frequency-domain stage, select and forward a reduced subset-such as one-half-to a time-domain transmit stage limited to N/2 streams, and to coordinate operation via inter-component MAC synchronization interfaces, in order to balance throughput, power consumptions, and hardware complexity. The motivation here is to enable high performance, low latency inter-chip communication in space constrained designs.
Regarding claim 3, Paramesh and Moshfeghi fails to teach the component chip wherein the component chip and the one or more additional component chips are configured to collectively transmit one or more spatial streams using a same frequency channel.
But Raleigh fails to teach the chip-level architecture and multi-chip operations.
However, Tolga teaches the component chip wherein the component chip and the one or more additional component chips are configured to collectively transmit one or more spatial streams using a same frequency channel (English translation, pg. 3-4 paragraphs 3-17 & paragraphs 1-17, disclosure of WC2C communication between chiplets that are collectively transmitting and receiving data; further discussion on coordination on across chiplets that share frequency resources for data exchange or processing, consistent with the idea of transmitting over the same frequency channel).
Paramesh teaches a multi-layer MIMO architecture in which frequency-domain (spatio-spectral) processing supports multiple spatial streams up to a maximum capacity N, while downstream layers operate under tighter constraints. Moshfeghi teaches distributed transceiver systems with explicit OFDM frequency-domain processing, frequency-to-time domain conversion, selective activation of only a subset of available stream paths, and control-channel/interface signaling among distributed components including MAC-layer protocols. Furthermore, Tolga teaches modular, multi-chiplet architectures includes 2D-3D heterogenous integration with wired and wireless die-to-die communication. This architecture addresses performance, density, and power concerns by stacking and interconnecting multiple dielets or chiplets using TSVs, EMIBs, and WC2C (wireless chip-to-chip) technology. It would have been obvious to a person of ordinary skill in the art before the effective filing date, to combine these teachings to process N spatial streams in a frequency-domain stage, select and forward a reduced subset-such as one-half-to a time-domain transmit stage limited to N/2 streams, and to coordinate operation via inter-component MAC synchronization interfaces, in order to balance throughput, power consumptions, and hardware complexity. The motivation here is to enable high performance, low latency inter-chip communication in space constrained designs.
Regarding claim 4, Paramesh and Moshfeghi fail to teach the component chip wherein the set of one or more frequency domain components comprises a transmission, and wherein the transmission beamformer is configured to provide the proper subset of processed frequency domain spatial streams to the frequency-to-time domain mapping component.
However, Tolga teaches the component chip wherein the set of one or more frequency domain components comprises a transmission ((English translation, pg. 3-4 paragraphs 3-17 & paragraphs 1-17, beamforming –system includes RF transceiver circuitry and antenna structures enabling directional communication and beamforming managing spatial streams; further stating RF circuitry handling frequency-domain data and passes it along to other modules (for time-domain processing), receive spatial streams from frequency domain components), and wherein the transmission beamformer is configured to provide the proper subset processed frequency domain of spatial streams to the frequency-to-time domain mapping component ((English translation, pg. 3-4 paragraphs 3-17 & paragraphs 1-17, beamforming –system includes RF transceiver circuitry and antenna structures enabling directional communication and beamforming managing spatial streams; further stating RF circuitry handling frequency-domain data and passes it along to other modules (for time-domain processing), receive spatial streams from frequency domain components).
Paramesh teaches a multi-layer MIMO architecture in which frequency-domain (spatio-spectral) processing supports multiple spatial streams up to a maximum capacity N, while downstream layers operate under tighter constraints. Moshfeghi teaches distributed transceiver systems with explicit OFDM frequency-domain processing, frequency-to-time domain conversion, selective activation of only a subset of available stream paths, and control-channel/interface signaling among distributed components including MAC-layer protocols. Furthermore, Tolga teaches modular, multi-chiplet architectures includes 2D-3D heterogenous integration with wired and wireless die-to-die communication. This architecture addresses performance, density, and power concerns by stacking and interconnecting multiple dielets or chiplets using TSVs, EMIBs, and WC2C (wireless chip-to-chip) technology. It would have been obvious to a person of ordinary skill in the art before the effective filing date, to combine these teachings to process N spatial streams in a frequency-domain stage, select and forward a reduced subset-such as one-half-to a time-domain transmit stage limited to N/2 streams, and to coordinate operation via inter-component MAC synchronization interfaces, in order to balance throughput, power consumptions, and hardware complexity. The motivation here is to enable high performance, low latency inter-chip communication in space constrained designs.
Regarding claim 5, Paramesh and Moshfeghi fail to teach the component chip wherein the set of one or more frequency domain components are further comfigured to process a reduced set of spatial streams, wherein a quantity of spatial streams of the reduced set of spatial streams is equal to a quantity of the subset of processed frequency domain spatial streams.
However, Tolga teaches the component chip wherein the set of one or more frequency domain components are further configured to process a reduced set of spatial streams, wherein a quantity of spatial streams of the reduced set of spatial streams is equal to a quantity of the subset of processed frequency domain spatial streams ((English translation, pg. 3-4 paragraphs 3-17 & paragraphs 1-17, disclosure describes portioned operation where each chiplet processes a subset of the total spatial streams, consistent with the notion of a reduced set that matches the subset selected; and further explains that components are independently or collectively configured depending on system needs, matching the idea that frequency domain components are configurable based on subset quantity).
Paramesh teaches a multi-layer MIMO architecture in which frequency-domain (spatio-spectral) processing supports multiple spatial streams up to a maximum capacity N, while downstream layers operate under tighter constraints. Moshfeghi teaches distributed transceiver systems with explicit OFDM frequency-domain processing, frequency-to-time domain conversion, selective activation of only a subset of available stream paths, and control-channel/interface signaling among distributed components including MAC-layer protocols. Furthermore, Tolga teaches modular, multi-chiplet architectures includes 2D-3D heterogenous integration with wired and wireless die-to-die communication. This architecture addresses performance, density, and power concerns by stacking and interconnecting multiple dielets or chiplets using TSVs, EMIBs, and WC2C (wireless chip-to-chip) technology. It would have been obvious to a person of ordinary skill in the art before the effective filing date, to combine these teachings to process N spatial streams in a frequency-domain stage, select and forward a reduced subset-such as one-half-to a time-domain transmit stage limited to N/2 streams, and to coordinate operation via inter-component MAC synchronization interfaces, in order to balance throughput, power consumptions, and hardware complexity. The motivation here is to enable high performance, low latency inter-chip communication in space constrained designs.
Regarding claim 6, Paramesh and Moshfeghi fails to teach the component chip further comprising a chip-to-chip bus configured to couple the set of one or more frequency domain components to a respective set of one or more frequency domain components of each of one or more additional component chips, wherein the set of one or more frequency domain components is configured to provide a respective subset of the set of spatial streams via the chip-to-chip bus to each of the one or more additional component chips.
However, Tolga teaches the component chip further comprising a chip-to-chip bus configured to couple the set of one or more frequency domain components to a respective set of one or more frequency domain components of each of one or more additional component chips (description English translation pg. 3-4 paragraphs 3-17 & paragraphs 1-17 respectively: chip-to-chip communication is a recurring theme, both wires (interposers, bridges, TSVs) and wireless; direct interconnection between frequency-processing elements across chips: Relevant text—“…the interposer is the electrical interface between the connectors…provide interconnections between components (chips or chiplets)…” which is the bus; & “…the chiplet 410a can communicate directly wirelessly with chiplet 410f” which supports wireless bus communication, & “…wireless chip-to-chip (WC2C) communication can complement wireless communications…”—shows physical bus), wherein the set of one or more frequency domain components is configured to provide a respective subset of the set of spatial streams via the chip-to-chip bus to each of the one or more additional component chips (description English translation pg. 3-4 paragraphs 3-17 & paragraphs 1-17 respectively: chip-to-chip communication is a recurring theme, both wires (interposers, bridges, TSVs) and wireless; direct interconnection between frequency-processing elements across chips: Relevant text—“…the interposer is the electrical interface between the connectors…provide interconnections between components (chips or chiplets)…” which is the bus; & “…the chiplet 410a can communicate directly wirelessly with chiplet 410f” which supports wireless bus communication, & “…wireless chip-to-chip (WC2C) communication can complement wireless communications…”—shows physical bus).
Paramesh teaches a multi-layer MIMO architecture in which frequency-domain (spatio-spectral) processing supports multiple spatial streams up to a maximum capacity N, while downstream layers operate under tighter constraints. Moshfeghi teaches distributed transceiver systems with explicit OFDM frequency-domain processing, frequency-to-time domain conversion, selective activation of only a subset of available stream paths, and control-channel/interface signaling among distributed components including MAC-layer protocols. Furthermore, Tolga teaches modular, multi-chiplet architectures includes 2D-3D heterogenous integration with wired and wireless die-to-die communication. This architecture addresses performance, density, and power concerns by stacking and interconnecting multiple dielets or chiplets using TSVs, EMIBs, and WC2C (wireless chip-to-chip) technology. It would have been obvious to a person of ordinary skill in the art before the effective filing date, to combine these teachings to process N spatial streams in a frequency-domain stage, select and forward a reduced subset-such as one-half-to a time-domain transmit stage limited to N/2 streams, and to coordinate operation via inter-component MAC synchronization interfaces, in order to balance throughput, power consumptions, and hardware complexity. The motivation here is to enable high performance, low latency inter-chip communication in space constrained designs.
Regarding claim 7, Paramesh and Moshfeghi fails to teach the component chip wherein the chip-to-chip bus is configured to couple the one or more MAC components with a respective physical (PHY) layer processor of each of the one or more additional component chips, or wherein the chip-to-chip bus is configured to couple the one or more MAC components with one or more respective MAC components of each of the one or more additional component chips.
However, Tolga teaches the component chip wherein the chip-to-chip bus is configured to couple the one or more MAC components with a respective physical (PHY) layer processor of each of the one or more additional component chips, or wherein the chip-to-chip bus is configured to couple the one or more MAC components with one or more respective MAC components of each of the one or more additional component chips (description English translation pg. 3-4 paragraphs 3-17 & paragraphs 1-17 respectively: description of protocol layering and references to MAC/PHY-type functions in control data planes; Relevant text: “…implement WC2C communication, an MCM…may implement protocols that can be divided into a control plane and a data plane…”—directly maps to the MAC/PHY layer model; “…radio control signaling…used to establish wireless communication within a module or package, and further to define routing paths for data.” & “…data layer carries network data…according to the directives of the control layer…”; enables MAC-to-PHY and MAC-to-MAC interactions across chips).
Paramesh teaches a multi-layer MIMO architecture in which frequency-domain (spatio-spectral) processing supports multiple spatial streams up to a maximum capacity N, while downstream layers operate under tighter constraints. Moshfeghi teaches distributed transceiver systems with explicit OFDM frequency-domain processing, frequency-to-time domain conversion, selective activation of only a subset of available stream paths, and control-channel/interface signaling among distributed components including MAC-layer protocols. Furthermore, Tolga teaches modular, multi-chiplet architectures includes 2D-3D heterogenous integration with wired and wireless die-to-die communication. This architecture addresses performance, density, and power concerns by stacking and interconnecting multiple dielets or chiplets using TSVs, EMIBs, and WC2C (wireless chip-to-chip) technology. It would have been obvious to a person of ordinary skill in the art before the effective filing date, to combine these teachings to process N spatial streams in a frequency-domain stage, select and forward a reduced subset-such as one-half-to a time-domain transmit stage limited to N/2 streams, and to coordinate operation via inter-component MAC synchronization interfaces, in order to balance throughput, power consumptions, and hardware complexity. The motivation here is to enable high performance, low latency inter-chip communication in space constrained designs.
Regarding claim 8, Paramesh and Moshfeghi fails to teach the component chip wherein the component chip is configured to perform one or more of: a clear channel assessment for the set of spatial streams, scheduling for the component chip and the one or more additional component chips, or identification of MAC protocol data unit (MPDU) information for the set of spatial streams.
However, Tolga teaches the component chip wherein the component chip is configured to perform one or more of: a clear channel assessment for the set of spatial streams, scheduling for the component chip and the one or more additional component chips, or identification of MAC protocol data unit (MPDU) information for the set of spatial streams (description English translation pg. 3-4 paragraphs 3-17 & paragraphs 1-17 respectively: MAC level functions from control plane capabilities in WC2C modules. Relevant text: “Modules implementing WC2C communication can include control plane capabilities” & “control layer capabilities or functional capabilities are included in the module” & “ Control layer protocols can be used to establish wireless communication…and further to define routing paths for data” – describes a CCA coordination).
Paramesh teaches a multi-layer MIMO architecture in which frequency-domain (spatio-spectral) processing supports multiple spatial streams up to a maximum capacity N, while downstream layers operate under tighter constraints. Moshfeghi teaches distributed transceiver systems with explicit OFDM frequency-domain processing, frequency-to-time domain conversion, selective activation of only a subset of available stream paths, and control-channel/interface signaling among distributed components including MAC-layer protocols. Furthermore, Tolga teaches modular, multi-chiplet architectures includes 2D-3D heterogenous integration with wired and wireless die-to-die communication. This architecture addresses performance, density, and power concerns by stacking and interconnecting multiple dielets or chiplets using TSVs, EMIBs, and WC2C (wireless chip-to-chip) technology. It would have been obvious to a person of ordinary skill in the art before the effective filing date, to combine these teachings to process N spatial streams in a frequency-domain stage, select and forward a reduced subset-such as one-half-to a time-domain transmit stage limited to N/2 streams, and to coordinate operation via inter-component MAC synchronization interfaces, in order to balance throughput, power consumptions, and hardware complexity. The motivation here is to enable high performance, low latency inter-chip communication in space constrained designs.
Regarding claim 9, Paramesh teaches the component chip further comprising:
a set of one or more reception time domain components configured to process a first proper subset of reception spatial streams, the first proper subset of reception spatial streams having a quantity that is equal to a quantity of spatial streams of the proper subset of spatial streams (col 3 lines 55-67, col 12 lines 2-19, repeatedly describes multi-layer hybrid architectures with a first processing layer handling all streams and later layers operating under tighter constraints, which is consistent with an upstream frequency-domain stage size for N streams);
and a set of one or more reception frequency domain components configurable to receive a set of reception spatial streams that includes the first proper subset of received spatial streams and a second proper subset of reception spatial streams from a second component chip (col 3 lines 55-67, col 12 lines 2-19, repeatedly describes multi-layer hybrid architectures with a first processing layer handling all streams and later layers operating under tighter constraints, which is consistent with an upstream frequency-domain stage size for N streams).
But Paramesh and Moshfeghi fails to teach receiving streams from other chips.
However, Tolga teaches receiving streams from other chips (description English translation pg. 3-4 paragraphs 3-17 & paragraphs 1-17 respectively: reception functionality and inter-chip spatial stream transfer mapped to frequency and time domain components for reception; relevant text: “The MCM 500c…enables mesh type wireless communication between several dies…data communication can be achieved without jumping over many dies” & “Chiplet 410a can communicate directly wirelessly with chiplet 410f” & “The radio data connections…may be established using control layer functions performed using radio control signaling”).
Paramesh teaches a multi-layer MIMO architecture in which frequency-domain (spatio-spectral) processing supports multiple spatial streams up to a maximum capacity N, while downstream layers operate under tighter constraints. Moshfeghi teaches distributed transceiver systems with explicit OFDM frequency-domain processing, frequency-to-time domain conversion, selective activation of only a subset of available stream paths, and control-channel/interface signaling among distributed components including MAC-layer protocols. Furthermore, Tolga teaches modular, multi-chiplet architectures includes 2D-3D heterogenous integration with wired and wireless die-to-die communication. This architecture addresses performance, density, and power concerns by stacking and interconnecting multiple dielets or chiplets using TSVs, EMIBs, and WC2C (wireless chip-to-chip) technology. It would have been obvious to a person of ordinary skill in the art before the effective filing date, to combine these teachings to process N spatial streams in a frequency-domain stage, select and forward a reduced subset-such as one-half-to a time-domain transmit stage limited to N/2 streams, and to coordinate operation via inter-component MAC synchronization interfaces, in order to balance throughput, power consumptions, and hardware complexity. The motivation here is to enable high performance, low latency inter-chip communication in space constrained designs.
Regarding claim 11, Paramesh and Moshfeghi fails to teach the component chip wherein the component chip is configured for operating with a first frequency bandwidth associated with the set of one or more frequency domain components being configured to process the set of spatial streams having a first quantity that is greater than a quantity of spatial streams of the subset of processed frequency domain spatial streams, wherein, the component chip is configured for operating with a second frequency bandwidth associated with the set of one or more frequency domain components being configured to process the set of spatial streams having a second quantity of spatial streams that is equal to the quantity of spatial streams of the subset of processed frequency domain spatial streams, the second frequency bandwidth being greater than the first frequency bandwidth.
However, Tolga teaches the component chip wherein the component chip wherein the component chip is configured for operating with a first frequency bandwidth associated with the set of one or more frequency domain components being configured to process the set of spatial streams having a first quantity that is greater than a quantity of spatial streams of the subset of processed frequency domain spatial streams ((description English translation pg. 3-4 paragraphs 3-17 & paragraphs 1-17 respectively: discussion of frequency scaling with antenna configuration and CMOS support at 110-170 GHz which supports multiple bandwidth configurations in consolidation with stream quantities. Relevant text: “the data layer of WC2C communication can operate at frequencies in the 110-170 GHz D-band”), wherein, the component chip is configured for operating with a second frequency bandwidth associated with the set of one or more frequency domain components being configured to process the set of spatial streams having a second quantity of spatial streams that is equal to the quantity of spatial streams of the subset of processed frequency domain spatial streams, the second frequency bandwidth being greater than the first frequency bandwidth ((description English translation pg. 3-4 paragraphs 3-17 & paragraphs 1-17 respectively: discussion of frequency scaling with antenna configuration and CMOS support at 110-170 GHz which supports multiple bandwidth configurations in consolidation with stream quantities. Relevant text: “the data layer of WC2C communication can operate at frequencies in the 110-170 GHz D-band”).
Paramesh teaches a multi-layer MIMO architecture in which frequency-domain (spatio-spectral) processing supports multiple spatial streams up to a maximum capacity N, while downstream layers operate under tighter constraints. Moshfeghi teaches distributed transceiver systems with explicit OFDM frequency-domain processing, frequency-to-time domain conversion, selective activation of only a subset of available stream paths, and control-channel/interface signaling among distributed components including MAC-layer protocols. Furthermore, Tolga teaches modular, multi-chiplet architectures includes 2D-3D heterogenous integration with wired and wireless die-to-die communication. This architecture addresses performance, density, and power concerns by stacking and interconnecting multiple dielets or chiplets using TSVs, EMIBs, and WC2C (wireless chip-to-chip) technology. It would have been obvious to a person of ordinary skill in the art before the effective filing date, to combine these teachings to process N spatial streams in a frequency-domain stage, select and forward a reduced subset-such as one-half-to a time-domain transmit stage limited to N/2 streams, and to coordinate operation via inter-component MAC synchronization interfaces, in order to balance throughput, power consumptions, and hardware complexity. The motivation here is to enable high performance, low latency inter-chip communication in space constrained designs.
Regarding claim 12, Paramesh teaches to teach a system comprising: the component chip of claim 1 (col 3 lines 55-67, col 12 lines 2-19, repeatedly describes multi-layer hybrid architectures with a first processing layer handling all streams and later layers operating under tighter constraints, which is consistent with an upstream frequency-domain stage size for N streams);
the one or more additional component chips configured to transmit a respective subset of spatial streams (col 3 lines 55-67, col 12 lines 2-19, repeatedly describes multi-layer hybrid architectures with a first processing layer handling all streams and later layers operating under tighter constraints, which is consistent with an upstream frequency-domain stage size for N streams);
But Paramesh and Moshfeghi fails to teach and a chip-to-chip bus configured to couple the set of one or more frequency domain components to an additional set of frequency domain components of the one or more additional component chips.
However, Tolga teaches and a chip-to-chip bus configured to couple the set of one or more frequency domain components to an additional set of frequency domain components of the one or more additional component chips ( ((description English translation pg. 3-4 paragraphs 3-17 & paragraphs 1-17 respectively: chip-to-chip bus as wireless interconnects acting functionally like a bus and the coupling of frequency domain components is shown by wireless broadcast and direct links. Relevant texts: “Chiplet 410a can communicate directly wirelessly with chiplet 410f” & “WC2C provides additional flexibility…by enabling broadcast and multipoint-to-multipoint connections” & “modules implementing WC2C communication can include…radio data connections…establish using control layer functions”).
Paramesh teaches a multi-layer MIMO architecture in which frequency-domain (spatio-spectral) processing supports multiple spatial streams up to a maximum capacity N, while downstream layers operate under tighter constraints. Moshfeghi teaches distributed transceiver systems with explicit OFDM frequency-domain processing, frequency-to-time domain conversion, selective activation of only a subset of available stream paths, and control-channel/interface signaling among distributed components including MAC-layer protocols. Furthermore, Tolga teaches modular, multi-chiplet architectures includes 2D-3D heterogenous integration with wired and wireless die-to-die communication. This architecture addresses performance, density, and power concerns by stacking and interconnecting multiple dielets or chiplets using TSVs, EMIBs, and WC2C (wireless chip-to-chip) technology. It would have been obvious to a person of ordinary skill in the art before the effective filing date, to combine these teachings to process N spatial streams in a frequency-domain stage, select and forward a reduced subset-such as one-half-to a time-domain transmit stage limited to N/2 streams, and to coordinate operation via inter-component MAC synchronization interfaces, in order to balance throughput, power consumptions, and hardware complexity. The motivation here is to enable high performance, low latency inter-chip communication in space constrained designs.
Regarding claim 14, Paramesh teaches the component chip further comprising a bus configured to couple the set of one or more frequency domain components to the one or more additional component chips (col 3 lines 55-67, col 12 lines 2-19, repeatedly describes multi-layer hybrid architectures with a first processing layer handling all streams and later layers operating under tighter constraints, which is consistent with an upstream frequency-domain stage size for N streams).
But Paramesh and Moshfeghi fails to teach chip-to-chip cooperation.
However, Tolga teaches chip-to-chip cooperation (Description English translation pg. 3-4 paragraphs 3-17 & paragraphs 1-17 respectively: Wireless die-to-die interconnects and WC2C communication between chiplets described as supporting broadcast and multipoint-to-multi-point connections”; it is also stated that WC2C can be used to greatly alleviate or reduce data traffic through TSVs, interposers, or bridges and to improve device performance. Relevant text: “WC2C provides additional flexibility…enabling broadcast and multipoint-to-multipoint connections”, & “…each chiplet or component can include an antenna structure 415 and radio frequency circuitry (transceiver circuitry 412)” which discloses per-chip wireless transmission ability; & “…module 400 can include or provide wired communication between components” & “…chiplet 410a can communicate directly with chiplet410f” –supports one chip in communication and providing data to another—transmission of subsets and synchronization information between chips).
Paramesh teaches a multi-layer MIMO architecture in which frequency-domain (spatio-spectral) processing supports multiple spatial streams up to a maximum capacity N, while downstream layers operate under tighter constraints. Moshfeghi teaches distributed transceiver systems with explicit OFDM frequency-domain processing, frequency-to-time domain conversion, selective activation of only a subset of available stream paths, and control-channel/interface signaling among distributed components including MAC-layer protocols. Furthermore, Tolga teaches modular, multi-chiplet architectures includes 2D-3D heterogenous integration with wired and wireless die-to-die communication. This architecture addresses performance, density, and power concerns by stacking and interconnecting multiple dielets or chiplets using TSVs, EMIBs, and WC2C (wireless chip-to-chip) technology. It would have been obvious to a person of ordinary skill in the art before the effective filing date, to combine these teachings to process N spatial streams in a frequency-domain stage, select and forward a reduced subset-such as one-half-to a time-domain transmit stage limited to N/2 streams, and to coordinate operation via inter-component MAC synchronization interfaces, in order to balance throughput, power consumptions, and hardware complexity. The motivation here is to enable high performance, low latency inter-chip communication in space constrained designs.
Regarding claim 15, Paramesh and Moshfeghi fails to teach the component chip wherein the bus comprises: a symmetric bus, or an asymmetric bus.
However, Tolga teaches the component chip wherein the bus comprises: a symmetric bus, or an asymmetric bus (Description English translation pg. 3-4 paragraphs 3-17 & paragraphs 1-17 respectively: description of interconnects (interposer, EMIB, and wireless interconnect) inherently enable symmetric (full duplex) or asymmetric (unidirectional or limited Tx/Rx paths) communication depending on configuration. Relevant text: “the interposer is the electrical interface between the connectors…bridges…EMIBs…provide high interconnect density when exactly needed…”; “WC2C communication…enables broadcast and multipoint-to-multi-point connections”).
Paramesh teaches a multi-layer MIMO architecture in which frequency-domain (spatio-spectral) processing supports multiple spatial streams up to a maximum capacity N, while downstream layers operate under tighter constraints. Moshfeghi teaches distributed transceiver systems with explicit OFDM frequency-domain processing, frequency-to-time domain conversion, selective activation of only a subset of available stream paths, and control-channel/interface signaling among distributed components including MAC-layer protocols. Furthermore, Tolga teaches modular, multi-chiplet architectures includes 2D-3D heterogenous integration with wired and wireless die-to-die communication. This architecture addresses performance, density, and power concerns by stacking and interconnecting multiple dielets or chiplets using TSVs, EMIBs, and WC2C (wireless chip-to-chip) technology. It would have been obvious to a person of ordinary skill in the art before the effective filing date, to combine these teachings to process N spatial streams in a frequency-domain stage, select and forward a reduced subset-such as one-half-to a time-domain transmit stage limited to N/2 streams, and to coordinate operation via inter-component MAC synchronization interfaces, in order to balance throughput, power consumptions, and hardware complexity. The motivation here is to enable high performance, low latency inter-chip communication in space constrained designs.
Regarding claim 16, Paramesh and Moshfeghi fails to teach the component chip wherein the component of the set of one or more frequency domain components comprises a demodulator.
However, Tolga teaches the component chip wherein the component of the set of one or more frequency domain components comprises a demodulator (Description English translation pg. 3-4 paragraphs 3-17 & paragraphs 1-17 respectively: describes a transceiver that includes a demodulator and a wireless transceiver circuit is present in each chiplet, and transceivers include demodulation functionality. Relevant text: “the enable wireless communication, each chiplet…can include an antenna structure and radio frequency circuitry (transceiver circuitry)”).
Paramesh teaches a multi-layer MIMO architecture in which frequency-domain (spatio-spectral) processing supports multiple spatial streams up to a maximum capacity N, while downstream layers operate under tighter constraints. Moshfeghi teaches distributed transceiver systems with explicit OFDM frequency-domain processing, frequency-to-time domain conversion, selective activation of only a subset of available stream paths, and control-channel/interface signaling among distributed components including MAC-layer protocols. Furthermore, Tolga teaches modular, multi-chiplet architectures includes 2D-3D heterogenous integration with wired and wireless die-to-die communication. This architecture addresses performance, density, and power concerns by stacking and interconnecting multiple dielets or chiplets using TSVs, EMIBs, and WC2C (wireless chip-to-chip) technology. It would have been obvious to a person of ordinary skill in the art before the effective filing date, to combine these teachings to process N spatial streams in a frequency-domain stage, select and forward a reduced subset-such as one-half-to a time-domain transmit stage limited to N/2 streams, and to coordinate operation via inter-component MAC synchronization interfaces, in order to balance throughput, power consumptions, and hardware complexity. The motivation here is to enable high performance, low latency inter-chip communication in space constrained designs.
Regarding claim 17, Paramesh and Moshfeghi fails to teach the component chip wherein the demodulator is configured to receive the first proper subset of the set of spatial streams from the time-to-frequency domain mapping component and to receive the second proper subset of the set of spatial streams from one or more additional component chips.
However, Tolga teaches the component chip wherein the demodulator is configured to receive the first proper subset of the set of spatial streams from the time-to-frequency domain mapping component and to receive the second proper subset of the set of spatial streams from one or more additional component chips (Description English translation pg. 3-4 paragraphs 3-17 & paragraphs 1-17 respectively: description of architecture supports receiving signals from multiple chiplets (suggesting subsets), and the idea is inferable based on WC2C’s broadcast and multipoint structure. Relevant text: “Wireless chip-to-chip (WC2C) technology…enables broadcast and multipoint-to-multipoint connections…” & “Components can include…radio frequency circuitry…enabling wireless communication between chiplets”).
Paramesh teaches a multi-layer MIMO architecture in which frequency-domain (spatio-spectral) processing supports multiple spatial streams up to a maximum capacity N, while downstream layers operate under tighter constraints. Moshfeghi teaches distributed transceiver systems with explicit OFDM frequency-domain processing, frequency-to-time domain conversion, selective activation of only a subset of available stream paths, and control-channel/interface signaling among distributed components including MAC-layer protocols. Furthermore, Tolga teaches modular, multi-chiplet architectures includes 2D-3D heterogenous integration with wired and wireless die-to-die communication. This architecture addresses performance, density, and power concerns by stacking and interconnecting multiple dielets or chiplets using TSVs, EMIBs, and WC2C (wireless chip-to-chip) technology. It would have been obvious to a person of ordinary skill in the art before the effective filing date, to combine these teachings to process N spatial streams in a frequency-domain stage, select and forward a reduced subset-such as one-half-to a time-domain transmit stage limited to N/2 streams, and to coordinate operation via inter-component MAC synchronization interfaces, in order to balance throughput, power consumptions, and hardware complexity. The motivation here is to enable high performance, low latency inter-chip communication in space constrained designs.
Regarding claim 18, Paramesh and Moshfeghi fails to teach the component chip wherein the set of one or more frequency domain components comprises a medium access control (MAC) layer processor, wherein the MAC layer processor is configured to receive the first proper subset of the set of spatial streams from the set of one or more frequency domain components and to receive the second proper subset of the set of spatial streams from the one or more additional component chips via a bus.
However, Tolga teaches the component chip wherein the set of one or more frequency domain components comprises a medium access control (MAC) layer processor, wherein the MAC layer processor is configured to receive the first proper subset of the set of spatial streams from the set of one or more frequency domain components and to receive the second proper subset of the set of spatial streams from the one or more additional component chips via a bus ((Description English translation pg. 3-4 paragraphs 3-17 & paragraphs 1-17 respectively: disclosure of MAC control functions (routing control plane, and packet delivery and routing and data forwarding behavior aligns with MAC-layer responsibilities. Relevant text: “modules implementing WC2C communication can include control plane capabilities…using control signaling” & “Protocols…define routing paths for data…Control layering messages…inform other components where to forward data).
Paramesh teaches a multi-layer MIMO architecture in which frequency-domain (spatio-spectral) processing supports multiple spatial streams up to a maximum capacity N, while downstream layers operate under tighter constraints. Moshfeghi teaches distributed transceiver systems with explicit OFDM frequency-domain processing, frequency-to-time domain conversion, selective activation of only a subset of available stream paths, and control-channel/interface signaling among distributed components including MAC-layer protocols. Furthermore, Tolga teaches modular, multi-chiplet architectures includes 2D-3D heterogenous integration with wired and wireless die-to-die communication. This architecture addresses performance, density, and power concerns by stacking and interconnecting multiple dielets or chiplets using TSVs, EMIBs, and WC2C (wireless chip-to-chip) technology. It would have been obvious to a person of ordinary skill in the art before the effective filing date, to combine these teachings to process N spatial streams in a frequency-domain stage, select and forward a reduced subset-such as one-half-to a time-domain transmit stage limited to N/2 streams, and to coordinate operation via inter-component MAC synchronization interfaces, in order to balance throughput, power consumptions, and hardware complexity. The motivation here is to enable high performance, low latency inter-chip communication in space constrained designs.
Regarding claim 19, Paramesh and Moshfeghi fails to teach the component chip wherein the set of one or more frequency domain components is configurable to process the first proper subset of the set of spatial streams and not the second proper subset of the set of spatial streams.
However, Tolga teaches the component chip wherein the set of one or more frequency domain components is configurable to process the first proper subset of the set of spatial streams and not the second proper subset of the set of spatial streams ((Description English translation pg. 3-4 paragraphs 3-17 & paragraphs 1-17 respectively: discloses selective communication architecture suggests configurability, allowing a chiplet to process specific streams/subsets. Relevant text: “Wireless communications can enable selective communication…multipoint-to-multipoint connections…” & “Control layer protocols can define routing paths for data…”).
Paramesh teaches a multi-layer MIMO architecture in which frequency-domain (spatio-spectral) processing supports multiple spatial streams up to a maximum capacity N, while downstream layers operate under tighter constraints. Moshfeghi teaches distributed transceiver systems with explicit OFDM frequency-domain processing, frequency-to-time domain conversion, selective activation of only a subset of available stream paths, and control-channel/interface signaling among distributed components including MAC-layer protocols. Furthermore, Tolga teaches modular, multi-chiplet architectures includes 2D-3D heterogenous integration with wired and wireless die-to-die communication. This architecture addresses performance, density, and power concerns by stacking and interconnecting multiple dielets or chiplets using TSVs, EMIBs, and WC2C (wireless chip-to-chip) technology. It would have been obvious to a person of ordinary skill in the art before the effective filing date, to combine these teachings to process N spatial streams in a frequency-domain stage, select and forward a reduced subset-such as one-half-to a time-domain transmit stage limited to N/2 streams, and to coordinate operation via inter-component MAC synchronization interfaces, in order to balance throughput, power consumptions, and hardware complexity. The motivation here is to enable high performance, low latency inter-chip communication in space constrained designs.
Regarding claim 20, Paramesh and Moshfeghi fails to teach the component chip wherein the component chip is configurable for operating with a first frequency bandwidth associated with the set of one or more frequency domain components being configured to process the set of spatial streams having a first quantity that is greater than a quantity of spatial streams of the first proper subset of the set of spatial streams that the set of one or more time domain components is configured to receive, and wherein the component chip is configurable for operating with a second frequency bandwidth associated with the set of one or more frequency domain components being configured to process the set of spatial streams having a second quantity of spatial streams that is equal to the quantity of spatial streams of the first proper subset of spatial streams that the set of one or more time domain components are configured to receive, the second frequency bandwidth being greater than the first frequency bandwidth.
However, Tolga teaches the component chip wherein the component chip is configurable for operating with a first frequency bandwidth associated with the set of one or more frequency domain components being configured to process the set of spatial streams having a first quantity that is greater than a quantity of spatial streams of the first proper subset of the set of spatial streams that the set of one or more time domain components is configured to receive ((Description English translation pg. 3-4 paragraphs 3-17 & paragraphs 1-17 respectively: disclosure provides reconfigurable high-frequency operation like bandwidth scalability; bandwidth variation linked to spatial stream disclosed as dynamic routing and chiplet processing architecture. Relevant text: “Data layer of WC2C communication can operate at frequencies in the 110-170GHz D-band…higher bandwidth can be achieved” & Modules…include control plane capabilities…defining routing paths …reconfigurable data center networks”), and wherein the component chip is configurable for operating with a second frequency bandwidth associated with the set of one or more frequency domain components being configured to process the set of spatial streams having a second quantity of spatial streams that is equal to the quantity of spatial streams of the first proper subset of spatial streams that the set of one or more time domain components are configured to receive, the second frequency bandwidth being greater than the first frequency bandwidth ((Description English translation pg. 3-4 paragraphs 3-17 & paragraphs 1-17 respectively: disclosure provides reconfigurable high-frequency operation like bandwidth scalability; bandwidth variation linked to spatial stream disclosed as dynamic routing and chiplet processing architecture. Relevant text: “Data layer of WC2C communication can operate at frequencies in the 110-170GHz D-band…higher bandwidth can be achieved” & Modules…include control plane capabilities…defining routing paths …reconfigurable data center networks”).
Paramesh teaches a multi-layer MIMO architecture in which frequency-domain (spatio-spectral) processing supports multiple spatial streams up to a maximum capacity N, while downstream layers operate under tighter constraints. Moshfeghi teaches distributed transceiver systems with explicit OFDM frequency-domain processing, frequency-to-time domain conversion, selective activation of only a subset of available stream paths, and control-channel/interface signaling among distributed components including MAC-layer protocols. Furthermore, Tolga teaches modular, multi-chiplet architectures includes 2D-3D heterogenous integration with wired and wireless die-to-die communication. This architecture addresses performance, density, and power concerns by stacking and interconnecting multiple dielets or chiplets using TSVs, EMIBs, and WC2C (wireless chip-to-chip) technology. It would have been obvious to a person of ordinary skill in the art before the effective filing date, to combine these teachings to process N spatial streams in a frequency-domain stage, select and forward a reduced subset-such as one-half-to a time-domain transmit stage limited to N/2 streams, and to coordinate operation via inter-component MAC synchronization interfaces, in order to balance throughput, power consumptions, and hardware complexity. The motivation here is to enable high performance, low latency inter-chip communication in space constrained designs.
Regarding claim 21, Paramesh and Moshfeghi fails to teach a system comprising: the component chip of claim 13; the one or more additional component chips; and a chip-to-chip bus configured to couple the set of one or more frequency domain components to an additional set of frequency domain components of the one or more additional component chips.
However, Tolga teaches a system comprising: the component chip of claim 13 (Description English translation pg. 3-4 paragraphs 3-17 & paragraphs 1-17 respectively: the wireless chip-to-chip interconnect acts as a bus, linking component chips that each include frequency domain components (transceivers). Relevant text: “Fig. 4 illustrates an example…including wireless interconnection.” & “Chiplet 410a can communicate directly wirelessly with chiplet 410f…” & “to enable wireless communication, each chiplet includes an antenna…and transceiver circuitry…”) ; the one or more additional component chips (Description English translation pg. 3-4 paragraphs 3-17 & paragraphs 1-17 respectively: the wireless chip-to-chip interconnect acts as a bus, linking component chips that each include frequency domain components (transceivers). Relevant text: “Fig. 4 illustrates an example…including wireless interconnection.” & “Chiplet 410a can communicate directly wirelessly with chiplet 410f…” & “to enable wireless communication, each chiplet includes an antenna…and transceiver circuitry…”); and a chip-to-chip bus configured to couple the set of one or more frequency domain components to an additional set of frequency domain components of the one or more additional component chips (Description English translation pg. 3-4 paragraphs 3-17 & paragraphs 1-17 respectively: the wireless chip-to-chip interconnect acts as a bus, linking component chips that each include frequency domain components (transceivers). Relevant text: “Fig. 4 illustrates an example…including wireless interconnection.” & “Chiplet 410a can communicate directly wirelessly with chiplet 410f…” & “to enable wireless communication, each chiplet includes an antenna…and transceiver circuitry…”).
Paramesh teaches a multi-layer MIMO architecture in which frequency-domain (spatio-spectral) processing supports multiple spatial streams up to a maximum capacity N, while downstream layers operate under tighter constraints. Moshfeghi teaches distributed transceiver systems with explicit OFDM frequency-domain processing, frequency-to-time domain conversion, selective activation of only a subset of available stream paths, and control-channel/interface signaling among distributed components including MAC-layer protocols. Furthermore, Tolga teaches modular, multi-chiplet architectures includes 2D-3D heterogenous integration with wired and wireless die-to-die communication. This architecture addresses performance, density, and power concerns by stacking and interconnecting multiple dielets or chiplets using TSVs, EMIBs, and WC2C (wireless chip-to-chip) technology. It would have been obvious to a person of ordinary skill in the art before the effective filing date, to combine these teachings to process N spatial streams in a frequency-domain stage, select and forward a reduced subset-such as one-half-to a time-domain transmit stage limited to N/2 streams, and to coordinate operation via inter-component MAC synchronization interfaces, in order to balance throughput, power consumptions, and hardware complexity. The motivation here is to enable high performance, low latency inter-chip communication in space constrained designs.
Claims 22-35 are rejected under 35 U.S.C. 103 as being unpatentable over Raleigh et al (US20030072382) in view of Tolga.
Regarding claim 22, Raleigh a method for wireless communication performable at a wireless communication device (WCD), comprising:
transmitting an indication of a total quantity of spatial streams supported by the WCD, the total quantity of spatial streams being a sum of a first quantity of spatial streams supported by a first component chip of the WCD and a second quantity of spatial streams supported by a second component chip of the WCD ([0066]-[0069] describes a transmitter space-frequency Pre-processor (TSFP) that performs spatial processing and SOP (IFFT) –mapping from frequency to time domain; TSFP output is a parallel set of digital time domain signals fed to modulation and RF System block 40 and radiated visa transmit antenna array 50: frequency domain processing and selection—spatial processing in TSFP; Frequency-to-time mapping: SOP (IFFT), and time domain transmission—modulation and antenna array stages); and
But Raleigh fails to teach communicating using one or more of the first component chip or the second component chip.
However, Tolga teaches communicating using one or more of the first component chip or the second component chip, wherein synchronization information is communicated between the first component chip and the second component chip via an interface (Description English translation pg. 3-4 paragraphs 3-17 & paragraphs 1-17 respectively: Wireless die-to-die interconnects and WC2C communication between chiplets described as supporting broadcast and multipoint-to-multi-point connections”; it is also stated that WC2C can be used to greatly alleviate or reduce data traffic through TSVs, interposers, or bridges and to improve device performance. Relevant text: “WC2C provides additional flexibility…enabling broadcast and multipoint-to-multipoint connections”, & “…each chiplet or component can include an antenna structure 415 and radio frequency circuitry (transceiver circuitry 412)” which discloses per-chip wireless transmission ability; & “…module 400 can include or provide wired communication between components” & “…chiplet 410a can communicate directly with chiplet410f” –supports one chip in communication and providing data to another—transmission of subsets and synchronization information between chips).
A person of ordinary skill in the art would have been motivated to combine the teachings of Raleigh, and Tolga to arrive at a component chip for wireless communication with enhanced spatial stream capacity through modular and scalable architecture. Raleigh discloses a space-time signal processing system that leverages multiple antennas and multipath channels to significantly increase capacity, thereby motivating the use of more spatial streams to achieve higher throughput and spectral efficiency. Tolga teaches modular, multi-chiplet architectures includes 2D-3D heterogenous integration with wired and wireless die-to-die communication. This architecture addresses performance, density, and power concerns by stacking and interconnecting multiple dielets or chiplets using TSVs, EMIBs, and WC2C (wireless chip-to-chip) technology. The motivation here is to enable high performance, low latency inter-chip communication in space constrained designs.
Furthermore, this teaches the desirability and feasibility of transmitting and processing large quantities of spatial streams, which directly aligns with the purpose of Raleigh’s signal processing benefits and the flexible chiplet design of Tolga. The combination of these teaching would have been obvious because it yields a architecture composed of modular chiplets capable of handling a quantity of spatial streams that surpasses what a single chip could process alone, supported by high-speed interchip connectivity and efficient signal processing techniques. Together, they provide a clear roadmap to the claimed invention of a component chip configured to process a quantity of spatial streams exceeding the capacity of a single chip.
Regarding claim 23, Raleigh teaches the method further comprising:
transmitting an indication of a first supported frequency bandwidth for communication via the first quantity of spatial streams and a second supported frequency bandwidth for communication via the second quantity of spatial streams ([0066]-[0069] describes a transmitter space-frequency Pre-processor (TSFP) that performs spatial processing and SOP (IFFT) –mapping from frequency to time domain; TSFP output is a parallel set of digital time domain signals fed to modulation and RF System block 40 and radiated visa transmit antenna array 50: frequency domain processing and selection—spatial processing in TSFP; Frequency-to-time mapping: SOP (IFFT), and time domain transmission—modulation and antenna array stages).
Regarding claim 24, Raleigh fails to teach the method wherein communicating using the one or more of the first component chip or the second component chip comprises: communicating using the first component chip and the second component chip via a same frequency channel.
However, Tolga teaches the method wherein communicating using the one or more of the first component chip or the second component chip comprises: communicating using the first component chip and the second component chip via a same frequency channel (Description English translation pg. 3-4 paragraphs 3-17 & paragraphs 1-17 respectively: Wireless die-to-die interconnects and WC2C communication between chiplets described as supporting broadcast and multipoint-to-multi-point connections”; it is also stated that WC2C can be used to greatly alleviate or reduce data traffic through TSVs, interposers, or bridges and to improve device performance. Relevant text: “WC2C provides additional flexibility…enabling broadcast and multipoint-to-multipoint connections”, & “…each chiplet or component can include an antenna structure 415 and radio frequency circuitry (transceiver circuitry 412)” which discloses per-chip wireless transmission ability; & “…module 400 can include or provide wired communication between components” & “…chiplet 410a can communicate directly with chiplet410f” –supports one chip in communication and providing data to another—transmission of subsets and synchronization information between chips).
A person of ordinary skill in the art would have been motivated to combine the teachings of Raleigh, and Tolga to arrive at a component chip for wireless communication with enhanced spatial stream capacity through modular and scalable architecture. Raleigh discloses a space-time signal processing system that leverages multiple antennas and multipath channels to significantly increase capacity, thereby motivating the use of more spatial streams to achieve higher throughput and spectral efficiency. Tolga teaches modular, multi-chiplet architectures includes 2D-3D heterogenous integration with wired and wireless die-to-die communication. This architecture addresses performance, density, and power concerns by stacking and interconnecting multiple dielets or chiplets using TSVs, EMIBs, and WC2C (wireless chip-to-chip) technology. The motivation here is to enable high performance, low latency inter-chip communication in space constrained designs.
Furthermore, this teaches the desirability and feasibility of transmitting and processing large quantities of spatial streams, which directly aligns with the purpose of Raleigh’s signal processing benefits and the flexible chiplet design of Tolga. The combination of these teaching would have been obvious because it yields a architecture composed of modular chiplets capable of handling a quantity of spatial streams that surpasses what a single chip could process alone, supported by high-speed interchip connectivity and efficient signal processing techniques. Together, they provide a clear roadmap to the claimed invention of a component chip configured to process a quantity of spatial streams exceeding the capacity of a single chip.
Regarding claim 25, Raleigh teaches the method wherein communicating using the one or more of the first component chip or the second component chip comprises:
providing, to the first component chip and to the second component chip, a set of spatial streams ([0069]-[0071], [0081], describes parallel time-domain signals being routed to RF chains, and antenna arrays transmitting in parallel; further discussion MISO/SIMO configurations and adaptable channel use—concept of multiple processing chains and disaggregate transmission), wherein each of the one or more additional component chips is configured to transmit a respective subset of spatial streams ([0069]-[0071], [0081], describes parallel time-domain signals being routed to RF chains, and antenna arrays transmitting in parallel; further discussion MISO/SIMO configurations and adaptable channel use—concept of multiple processing chains and disaggregate transmission);
transmitting a first subset the set of spatial streams via the first component chip ([0069]-[0071], [0081], describes parallel time-domain signals being routed to RF chains, and antenna arrays transmitting in parallel; further discussion MISO/SIMO configurations and adaptable channel use—concept of multiple processing chains and disaggregate transmission), wherein each of the one or more additional component chips is configured to transmit a respective subset of spatial streams ([0069]-[0071], [0081], describes parallel time-domain signals being routed to RF chains, and antenna arrays transmitting in parallel; further discussion MISO/SIMO configurations and adaptable channel use—concept of multiple processing chains and disaggregate transmission); and
transmitting a second subset of the set of spatial streams via the second component chip ([0069]-[0071], [0081], describes parallel time-domain signals being routed to RF chains, and antenna arrays transmitting in parallel; further discussion MISO/SIMO configurations and adaptable channel use—concept of multiple processing chains and disaggregate transmission), wherein each of the one or more additional component chips is configured to transmit a respective subset of spatial streams ([0069]-[0071], [0081], describes parallel time-domain signals being routed to RF chains, and antenna arrays transmitting in parallel; further discussion MISO/SIMO configurations and adaptable channel use—concept of multiple processing chains and disaggregate transmission).
But Raleigh fails to teach chip-to-chip cooperation.
However, Tolga teaches chip-to-chip cooperation (Description English translation pg. 3-4 paragraphs 3-17 & paragraphs 1-17 respectively: Wireless die-to-die interconnects and WC2C communication between chiplets described as supporting broadcast and multipoint-to-multi-point connections”; it is also stated that WC2C can be used to greatly alleviate or reduce data traffic through TSVs, interposers, or bridges and to improve device performance. Relevant text: “WC2C provides additional flexibility…enabling broadcast and multipoint-to-multipoint connections”, & “…each chiplet or component can include an antenna structure 415 and radio frequency circuitry (transceiver circuitry 412)” which discloses per-chip wireless transmission ability; & “…module 400 can include or provide wired communication between components” & “…chiplet 410a can communicate directly with chiplet410f” –supports one chip in communication and providing data to another—transmission of subsets and synchronization information between chips).
A person of ordinary skill in the art would have been motivated to combine the teachings of Raleigh, and Tolga to arrive at a component chip for wireless communication with enhanced spatial stream capacity through modular and scalable architecture. Raleigh discloses a space-time signal processing system that leverages multiple antennas and multipath channels to significantly increase capacity, thereby motivating the use of more spatial streams to achieve higher throughput and spectral efficiency. Tolga teaches modular, multi-chiplet architectures includes 2D-3D heterogenous integration with wired and wireless die-to-die communication. This architecture addresses performance, density, and power concerns by stacking and interconnecting multiple dielets or chiplets using TSVs, EMIBs, and WC2C (wireless chip-to-chip) technology. The motivation here is to enable high performance, low latency inter-chip communication in space constrained designs.
Furthermore, this teaches the desirability and feasibility of transmitting and processing large quantities of spatial streams, which directly aligns with the purpose of Raleigh’s signal processing benefits and the flexible chiplet design of Tolga. The combination of these teaching would have been obvious because it yields a architecture composed of modular chiplets capable of handling a quantity of spatial streams that surpasses what a single chip could process alone, supported by high-speed interchip connectivity and efficient signal processing techniques. Together, they provide a clear roadmap to the claimed invention of a component chip configured to process a quantity of spatial streams exceeding the capacity of a single chip.
Regarding claim 26, Raleigh fails to teach the method wherein providing the set of spatial streams to the second component chip comprises: providing the set of spatial streams to the first component chip; performing medium access control (MAC) layer processing on the set of spatial streams; and providing, after performing the MAC layer processing, the set of spatial streams to the second component chip.
However, Tolga teaches the method wherein providing the set of spatial streams to the second component chip comprises: providing the set of spatial streams to the first component chip; performing medium access control (MAC) layer processing on the set of spatial streams ((Description English translation pg. 3-4 paragraphs 3-17 & paragraphs 1-17 respectively: disclosure of MAC control functions (routing control plane, and packet delivery and routing and data forwarding behavior aligns with MAC-layer responsibilities. Relevant text: “modules implementing WC2C communication can include control plane capabilities…using control signaling” & “Protocols…define routing paths for data…Control layering messages…inform other components where to forward data); and providing, after performing the MAC layer processing, the set of spatial streams to the second component chip ((Description English translation pg. 3-4 paragraphs 3-17 & paragraphs 1-17 respectively: disclosure of MAC control functions (routing control plane, and packet delivery and routing and data forwarding behavior aligns with MAC-layer responsibilities. Relevant text: “modules implementing WC2C communication can include control plane capabilities…using control signaling” & “Protocols…define routing paths for data…Control layering messages…inform other components where to forward data).
A person of ordinary skill in the art would have been motivated to combine the teachings of Raleigh, and Tolga to arrive at a component chip for wireless communication with enhanced spatial stream capacity through modular and scalable architecture. Raleigh discloses a space-time signal processing system that leverages multiple antennas and multipath channels to significantly increase capacity, thereby motivating the use of more spatial streams to achieve higher throughput and spectral efficiency. Tolga teaches modular, multi-chiplet architectures includes 2D-3D heterogenous integration with wired and wireless die-to-die communication. This architecture addresses performance, density, and power concerns by stacking and interconnecting multiple dielets or chiplets using TSVs, EMIBs, and WC2C (wireless chip-to-chip) technology. The motivation here is to enable high performance, low latency inter-chip communication in space constrained designs.
Furthermore, this teaches the desirability and feasibility of transmitting and processing large quantities of spatial streams, which directly aligns with the purpose of Raleigh’s signal processing benefits and the flexible chiplet design of Tolga. The combination of these teaching would have been obvious because it yields a architecture composed of modular chiplets capable of handling a quantity of spatial streams that surpasses what a single chip could process alone, supported by high-speed interchip connectivity and efficient signal processing techniques. Together, they provide a clear roadmap to the claimed invention of a component chip configured to process a quantity of spatial streams exceeding the capacity of a single chip.
Regarding claim 28, Raleigh fails to teach the method wherein the synchronization information comprises one or more of: first synchronization information from a first frequency domain component of the first component chip that is provided to a second frequency domain component of the second component chip, or second synchronization information from a first time domain component of the first component chip that is provided to a second time domain component of the second component chip.
However, Tolga teaches teach the method wherein providing the synchronization information comprises providing one or more of: first synchronization information from a first frequency domain component of the first component chip that is provided to a second frequency domain component of the second component chip, or second synchronization information from a first time domain component of the first component chip that is provided to a second time domain component of the second component chip (Description English translation pg. 3-4 paragraphs 3-17 & paragraphs 1-17 respectively: Wireless die-to-die interconnects and WC2C communication between chiplets described as supporting broadcast and multipoint-to-multi-point connections”; it is also stated that WC2C can be used to greatly alleviate or reduce data traffic through TSVs, interposers, or bridges and to improve device performance. Relevant text: “WC2C provides additional flexibility…enabling broadcast and multipoint-to-multipoint connections”, & “…each chiplet or component can include an antenna structure 415 and radio frequency circuitry (transceiver circuitry 412)” which discloses per-chip wireless transmission ability; & “…module 400 can include or provide wired communication between components” & “…chiplet 410a can communicate directly with chiplet410f” –supports one chip in communication and providing data to another—transmission of subsets and synchronization information between chips).
A person of ordinary skill in the art would have been motivated to combine the teachings of Raleigh, and Tolga to arrive at a component chip for wireless communication with enhanced spatial stream capacity through modular and scalable architecture. Raleigh discloses a space-time signal processing system that leverages multiple antennas and multipath channels to significantly increase capacity, thereby motivating the use of more spatial streams to achieve higher throughput and spectral efficiency. Tolga teaches modular, multi-chiplet architectures includes 2D-3D heterogenous integration with wired and wireless die-to-die communication. This architecture addresses performance, density, and power concerns by stacking and interconnecting multiple dielets or chiplets using TSVs, EMIBs, and WC2C (wireless chip-to-chip) technology. The motivation here is to enable high performance, low latency inter-chip communication in space constrained designs.
Furthermore, this teaches the desirability and feasibility of transmitting and processing large quantities of spatial streams, which directly aligns with the purpose of Raleigh’s signal processing benefits and the flexible chiplet design of Tolga. The combination of these teaching would have been obvious because it yields a architecture composed of modular chiplets capable of handling a quantity of spatial streams that surpasses what a single chip could process alone, supported by high-speed interchip connectivity and efficient signal processing techniques. Together, they provide a clear roadmap to the claimed invention of a component chip configured to process a quantity of spatial streams exceeding the capacity of a single chip.
Regarding claim 29, Raleigh teaches the method further comprising selecting a communication mode for communicating using spatial streams ([0066]-[0069] describes a transmitter space-frequency Pre-processor (TSFP) that performs spatial processing and SOP (IFFT) –mapping from frequency to time domain; TSFP output is a parallel set of digital time domain signals fed to modulation and RF System block 40 and radiated visa transmit antenna array 50: frequency domain processing and selection—spatial processing in TSFP; Frequency-to-time mapping: SOP (IFFT), and time domain transmission—modulation and antenna array stages), wherein the communication mode is associated with one or more of:
a quantity of spatial streams for communication streams ([0066]-[0069] describes a transmitter space-frequency Pre-processor (TSFP) that performs spatial processing and SOP (IFFT) –mapping from frequency to time domain; TSFP output is a parallel set of digital time domain signals fed to modulation and RF System block 40 and radiated visa transmit antenna array 50: frequency domain processing and selection—spatial processing in TSFP; Frequency-to-time mapping: SOP (IFFT), and time domain transmission—modulation and antenna array stages),
But Raleigh fails to teach a configuration to communicate via a single frequency channel using the first component chip and the second component chip, or
a configuration to communicate via a first frequency band using the first component chip and via a second frequency band using the second component chip.
However, Tolga teaches a configuration to communicate via a single frequency channel using the first component chip and the second component chip, or
a configuration to communicate via a first frequency band using the first component chip and via a second frequency band using the second component chip (Description English translation pg. 3-4 paragraphs 3-17 & paragraphs 1-17 respectively: Wireless die-to-die interconnects and WC2C communication between chiplets described as supporting broadcast and multipoint-to-multi-point connections”; it is also stated that WC2C can be used to greatly alleviate or reduce data traffic through TSVs, interposers, or bridges and to improve device performance. Relevant text: “WC2C provides additional flexibility…enabling broadcast and multipoint-to-multipoint connections”, & “…each chiplet or component can include an antenna structure 415 and radio frequency circuitry (transceiver circuitry 412)” which discloses per-chip wireless transmission ability; & “…module 400 can include or provide wired communication between components” & “…chiplet 410a can communicate directly with chiplet410f” –supports one chip in communication and providing data to another—transmission of subsets and synchronization information between chips).
A person of ordinary skill in the art would have been motivated to combine the teachings of Raleigh, and Tolga to arrive at a component chip for wireless communication with enhanced spatial stream capacity through modular and scalable architecture. Raleigh discloses a space-time signal processing system that leverages multiple antennas and multipath channels to significantly increase capacity, thereby motivating the use of more spatial streams to achieve higher throughput and spectral efficiency. Tolga teaches modular, multi-chiplet architectures includes 2D-3D heterogenous integration with wired and wireless die-to-die communication. This architecture addresses performance, density, and power concerns by stacking and interconnecting multiple dielets or chiplets using TSVs, EMIBs, and WC2C (wireless chip-to-chip) technology. The motivation here is to enable high performance, low latency inter-chip communication in space constrained designs.
Furthermore, this teaches the desirability and feasibility of transmitting and processing large quantities of spatial streams, which directly aligns with the purpose of Raleigh’s signal processing benefits and the flexible chiplet design of Tolga. The combination of these teaching would have been obvious because it yields a architecture composed of modular chiplets capable of handling a quantity of spatial streams that surpasses what a single chip could process alone, supported by high-speed interchip connectivity and efficient signal processing techniques. Together, they provide a clear roadmap to the claimed invention of a component chip configured to process a quantity of spatial streams exceeding the capacity of a single chip.
Regarding claim 30, Raleigh teaches the method wherein communicating using the one or more of the first component chip or the second component chip comprises:
receiving a first subset of a set of spatial streams, having the first quantity of spatial streams, via the first component chip ([0066]-[0069] describes a transmitter space-frequency Pre-processor (TSFP) that performs spatial processing and SOP (IFFT) –mapping from frequency to time domain; TSFP output is a parallel set of digital time domain signals fed to modulation and RF System block 40 and radiated visa transmit antenna array 50: frequency domain processing and selection—spatial processing in TSFP; Frequency-to-time mapping: SOP (IFFT), and time domain transmission—modulation and antenna array stages);
receiving a second subset of the set of spatial streams, having the second quantity of spatial streams, via the second component chip ([0066]-[0069] describes a transmitter space-frequency Pre-processor (TSFP) that performs spatial processing and SOP (IFFT) –mapping from frequency to time domain; TSFP output is a parallel set of digital time domain signals fed to modulation and RF System block 40 and radiated visa transmit antenna array 50: frequency domain processing and selection—spatial processing in TSFP; Frequency-to-time mapping: SOP (IFFT), and time domain transmission—modulation and antenna array stages); and
providing, from the second component chip to the first component chip, the second subset of the set of spatial streams ([0066]-[0069] describes a transmitter space-frequency Pre-processor (TSFP) that performs spatial processing and SOP (IFFT) –mapping from frequency to time domain; TSFP output is a parallel set of digital time domain signals fed to modulation and RF System block 40 and radiated visa transmit antenna array 50: frequency domain processing and selection—spatial processing in TSFP; Frequency-to-time mapping: SOP (IFFT), and time domain transmission—modulation and antenna array stages).
Regarding claim 31, Raleigh teaches the method wherein providing the second proper subset of the set of spatial streams to the first component chip comprises one or more of:
providing the second subset of the set of spatial streams after performing discrete Fourier transform (DFT) on the second subset of the set of spatial streams, or providing the second subset of the set of spatial streams before performing demodulation on the second subset of the set of spatial streams ([0066]-[0069], Claim 7, [0010], DFT; describes a transmitter space-frequency Pre-processor (TSFP) that performs spatial processing and SOP (IFFT) –mapping from frequency to time domain; TSFP output is a parallel set of digital time domain signals fed to modulation and RF System block 40 and radiated visa transmit antenna array 50: frequency domain processing and selection—spatial processing in TSFP; Frequency-to-time mapping: SOP (IFFT), and time domain transmission—modulation and antenna array stages).
Regarding claim 32, Raleigh fails to teach the method wherein providing the second subset of the set of spatial streams to the first component chip comprises one or more of:
providing the second subset of the set of spatial streams after performing decoding on the second subset of the set of spatial streams, or providing the second subset of the set of spatial streams before performing medium access control (MAC) layer processing on the second subset of the set of spatial streams.
However, Tolga teaches the method wherein providing the second subset of the set of spatial streams to the first component chip comprises one or more of:
providing the second subset of the set of spatial streams after performing decoding on the second subset of the set of spatial streams, or providing the second subset of the set of spatial streams before performing medium access control (MAC) layer processing on the second subset of the set of spatial streams (description English translation pg. 3-4 paragraphs 3-17 & paragraphs 1-17 respectively: description of protocol layering and references to MAC/PHY-type functions in control data planes; Relevant text: “…implement WC2C communication, an MCM…may implement protocols that can be divided into a control plane and a data plane…”—directly maps to the MAC/PHY layer model; “…radio control signaling…used to establish wireless communication within a module or package, and further to define routing paths for data.” & “…data layer carries network data…according to the directives of the control layer…”; enables MAC-to-PHY and MAC-to-MAC interactions across chips).
A person of ordinary skill in the art would have been motivated to combine the teachings of Raleigh, and Tolga to arrive at a component chip for wireless communication with enhanced spatial stream capacity through modular and scalable architecture. Raleigh discloses a space-time signal processing system that leverages multiple antennas and multipath channels to significantly increase capacity, thereby motivating the use of more spatial streams to achieve higher throughput and spectral efficiency. Tolga teaches modular, multi-chiplet architectures includes 2D-3D heterogenous integration with wired and wireless die-to-die communication. This architecture addresses performance, density, and power concerns by stacking and interconnecting multiple dielets or chiplets using TSVs, EMIBs, and WC2C (wireless chip-to-chip) technology. The motivation here is to enable high performance, low latency inter-chip communication in space constrained designs.
Furthermore, this teaches the desirability and feasibility of transmitting and processing large quantities of spatial streams, which directly aligns with the purpose of Raleigh’s signal processing benefits and the flexible chiplet design of Tolga. The combination of these teaching would have been obvious because it yields a architecture composed of modular chiplets capable of handling a quantity of spatial streams that surpasses what a single chip could process alone, supported by high-speed interchip connectivity and efficient signal processing techniques. Together, they provide a clear roadmap to the claimed invention of a component chip configured to process a quantity of spatial streams exceeding the capacity of a single chip.
Regarding claim 33, Raleigh teaches the method further comprising: performing demodulation on the first subset of the set of spatial streams and the second subset of the set of spatial streams ([0066]-[0069] describes a transmitter space-frequency Pre-processor (TSFP) that performs spatial processing and SOP (IFFT) –mapping from frequency to time domain; TSFP output is a parallel set of digital time domain signals fed to modulation and RF System block 40 and radiated visa transmit antenna array 50: frequency domain processing and selection—spatial processing in TSFP; Frequency-to-time mapping: SOP (IFFT), and time domain transmission—modulation and antenna array stages).
Regarding claim 34, Raleigh teaches the method further comprising transmitting or receiving one or more of: an indication to communicate via the first quantity of spatial streams using the first component chip on a first frequency band, or an indication to communicate via the second quantity of spatial streams using the second component chip on a second frequency band that is different from the first frequency band ([0066]-[0069] describes a transmitter space-frequency Pre-processor (TSFP) that performs spatial processing and SOP (IFFT) –mapping from frequency to time domain; TSFP output is a parallel set of digital time domain signals fed to modulation and RF System block 40 and radiated visa transmit antenna array 50: frequency domain processing and selection—spatial processing in TSFP; Frequency-to-time mapping: SOP (IFFT), and time domain transmission—modulation and antenna array stages).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/MICHAEL WILLIAM ABBATINE JR./Examiner, Art Unit 2419
/Nishant Divecha/Supervisory Patent Examiner, Art Unit 2419