Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Schultz (US 10250197 B1) in view of TAKASHIMA (US 20250175129 A1), hereafter referred to as “Schultz” and “Takashima”, respectively.
Regarding claims 1 and 19, in the embodiments of Figures 1-6, Schulz discloses:
A semiconductor device (Figs. 4, 5, 6, column 22, lines 38-42, packaged RF amplifier device 600 includes a high-power semiconductor device package) comprising:
a first member (Fig. 5, substrate 406) having a first surface (surface between conductive layers 528,596);
a second member (Fig. 5, silicon substrate 510) having a second surface (surface between 510 and conductive layer 528) opposite to the first surface and including a radio-frequency amplifier circuit (column 19, lines 33-39, dies 410 and/or 480are configured to receive and convey RF signals); and
an electrically conductive bonding member between the first surface and the second surface (conductive layer 528) and bonding the first member and the second member to each other, wherein
the radio-frequency amplifier circuit includes
at least one power stage transistor (column 23, lines 53-55, Fig. 6, a silicon power transistor 640, Fig. 1, 140, Fig. 2, 240, Fig. 5, power transistor 440, Fig. 3 shows a plurality of power transistors 340, 341, 342, 343, 344),
an input wire (column 24, lines 1-4, Fig. 6, RF signal input lead 602 is electrically coupled to input terminal 620 through one or more wire bonds (e.g., corresponding to connection 103, 203, 303, 403)) that is connected to the power stage transistor and that is configured to supply an input signal to the power stage transistor (columns 5, lines 62-67 to column 6, lines 1-5, RF signal is received through input terminal 102 then amplified by the silicon transistor 140 (i.e. silicon power transistor 640)), and
an input-side circuit element (input impedance matching circuit 630 (e.g., circuit 130, 230, 330, 430)) connected to the input wire (Fig. 1, 130 shown as connected to input terminal 120 and wire bond 103) and including at least one of a passive element (column 5, lines 11-17, impedance matching circuits 130, 150 is associated with a plurality of passive components), an active element (column 5, lines 11-17 die 110 includes active devices (i.e. silicon transistor 140)), and an external connection terminal (Fig. 1, terminal 158 (i.e. terminals 237, 257, 258, 337, 357, 358 or 437, 457, 458) connected to external bias voltage source 164),
the bonding member includes a first conductor pattern (Fig. 5, build-up layers 512, column 18, lines 37-42, build-up layers 512 may include, for example, a plurality of interleaved dielectric layers and patterned conductive layers) covering the power stage transistor in plan view (Fig. 5, 512 covers power transistor 440), and
However, Schultz is silent in teaching the input-side circuit element (Schultz, Figs. 4 and 6, 430 and 630) is outside the first conductor pattern in plan view.
Takashima teaches, in the embodiment of Figure 5 and 7,
the input-side circuit element (paragraph [0086], capacitive component 65, bonding wires 71 and 72 function as inductors) is outside the first conductor pattern (pads 42 and 43 as shown as line patterned on semiconductor chips 40a, 40b, and 40c) in plan view (as shown in Figs. 5 and 7).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to modify the input-side circuit element as taught by Schultz (Figs. 4 and 6, 430 and 630) to be outside of the first conductor pattern as taught by Takashima to achieve a desired characteristic impedance and electrical length (Takashima, paragraph [0039], lines 1-8), thereby suggesting the obviousness of such a modification.
Allowable Subject Matter
Claims 14-17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
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/MALANE LIENG/Examiner, Art Unit 2843
/ANDREA LINDGREN BALTZELL/Supervisory Patent Examiner, Art Unit 2843