DETAILED ACTION
This Office Action is in response to the Response to Restriction/Election filed 15 January 2026. Claims 1-18 are pending in this application. Claims 4, 6 are withdrawn from consideration and Claims 17-18 are newly added. Claims 1-3, 5, 7-18 are examined in this office action.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Species 1 in the reply filed on 15 January 2026 is acknowledged. The traversal is on the ground(s) that the office has failed to articulate the species are distinct and lack the same or corresponding technical feature. This is not found persuasive because applicant’s argument uses the wrong standard for determining when a restriction is appropriate. Applicant’s application is a continuation of a PCT (also known as a bypass application). A continuation of a PCT is a US national application (See MPEP 1895) and is therefore subject to the standards of US national applications with regards to restrictions. For Us national applications, that standard is whether the species are mutually exclusive (See MPEP 806.04(f))). Applicant has not provided any argument on why the restricted species/subspecies do not contain mutually exclusive features as recited in the Requirement for Restriction/Election filed 26 November 2025.
The requirement is still deemed proper and is therefore made FINAL.
Applicant's election with traverse of SubSpecies A in the reply filed on 15 January 2026 is acknowledged. The traversal is on the ground(s) that the two SubSpecies are not mutually exclusive because one can have both S/D regions and LDD regions. This is found persuasive.
The requirement with regard to SubSpecies A and B is withdrawn.
Drawings
Figure 1 should be designated by a legend such as --Prior Art-- because only that which is old is illustrated. See MPEP § 608.02(g). Corrected drawings in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. The replacement sheet(s) should be labeled “Replacement Sheet” in the page header (as per 37 CFR 1.84(c)) so as not to obstruct any portion of the drawing figures. If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The disclosure is objected to because of the following informalities:
Applicant's specification says “Specifically, the annealing time of the annealing process may be controlled at 0.5 h-2 h. For example, the annealing time may be 5 S, 30 S, 45 s, 1 min, 5 min, 10 min, 15 min, 20 min, 30 min, 45 min, 1 h, 1.25 h, 1.5 h, 1.75 h, etc., which may be determined according to the doping concentration of the source/drain region required to be formed.” ([0067]) This is inconsistent, as 0.5 h is 30 minutes; however, the specification lists examples of time below 30 minutes.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 5 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Applicant’s specification says “Specifically, the annealing time of the annealing process may be controlled at 0.5 h-2 h. For example, the annealing time may be 5 S, 30 S, 45 s, 1 min, 5 min, 10 min, 15 min, 20 min, 30 min, 45 min, 1 h, 1.25 h, 1.5 h, 1.75 h, etc., which may be determined according to the doping concentration of the source/drain region required to be formed.” ([0067]) This is inconsistent, as 0.5 h is 30 minutes; however, the specification lists examples of time below 30 minutes. Claim 5 recites a time constraint of “0.5h-2h” in line 4 of the claim. Because of the specification, it is unclear what times are meant to be included by the term “0.5h-2h” (is it 30 min- 2 hours or does it include 5 S, 30 S, 45 s, 1 min, 5 min, 10 min, 15 min, 20 min, 30 min, 45 min, 1 h, 1.25 h, 1.5 h, 1.75 h, etc.)
In order to be consistent with the broadest reasonable interpretation of the claim, the limitation is being interpreted as consistent with the specification examples, which include times down to 5 sec. This is broader than the normal meaning of 0.5h which is 30 minutes.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2, 7-8, 10, 13, 15-16 is/are rejected under 35 U.S.C. 102a(1) as being anticipated by Tsai et. al (US 2018/0175170 A1).
Regarding Claim 1, Tsai discloses (as shown in Fig. 1, 2A-7A) A method for manufacturing a fin transistor structure ([0013] method 100 fabricates an integrated circuit device that includes a FinFET device), comprising:
providing a substrate ([0015] In FIG. 2A and FIG. 2B, FinFET device 200 includes a substrate (wafer) 202.), a fin part ([0016] A fin structure 204) protruding from a top surface of the substrate (202); ([0016] A fin structure 204 is disposed over substrate 202.)
forming an isolation layer ([0019] An isolation feature(s) 210) on the substrate (202) ([0019] An isolation feature(s) 210 is formed over and/or in substrate 202 to isolate various regions, such as various device regions, of FinFET device 200), a top surface of the isolation layer (210) being lower than a top of the fin part (204), so that an upper part of the fin part (204) is exposed above the isolation layer (210); (See Fig. A, showing the top surface of the isolation features 210 being lower than the top surface of the fin structure 204)
and performing doping processing ([0026] Using SPD source/drain features to laterally and vertically dope source region 207 and drain region 208) on the upper part of the fin part (204) by a diffusion process ([0025] In FIGS. 6A-6C, an annealing process is performed. The annealing process causes dopant from SPD source/drain features 240 to diffuse into fin structure 204), to form at least one of a source region ([0026] source region 207) or a drain region ([0026] drain region 208) in the upper part of the fin part (204). ([0026] Using SPD source/drain features to laterally and vertically dope source region 207 and drain region 208)
Regarding Claim 2, Tsai further discloses (as shown in Fig. 1, 2A-7A) wherein performing doping processing on the upper part of the fin (204) part comprises:
arranging a diffusion region, the diffusion region surrounding a periphery of the upper part of the fin part (204); ([0023] For example, a selective epitaxial growth (SEG) process is performed to grow a semiconductor material on exposed portions of fin structure 204, thereby forming epitaxial source/drain features 240 over source region 207 and drain region 208. Epitaxial source/drain features 240 are heavily doped with n-type dopants and/or p-type dopants, such that epitaxial source/drain features 240 are configured to function as solid phase diffusion (SPD) layers.)
and performing diffusion doping processing on the upper part of the fin part (204) located in the diffusion region. ([0025] The annealing process causes dopant from SPD source/drain features 240 to diffuse into fin structure 204, particularly into source region 207 and drain region 208.)
Regarding Claim 7, Tsai further discloses (as shown in Fig. 6C) wherein a doping element for the doping processing comprises one or more of phosphorus, boron, arsenic, lead, aluminum and indium. ([0024] SPD source/drain features 240 can have a phosphorous dopant…where FinFET device 200 is configured as a p-type device (for example, having a p-channel), SPD source/drain features 240 include silicon germanium (SiGe) doped with boron, other p-type dopant, or combinations thereof (for example, forming a Si:Ge:B epitaxial layer)) ([0025] In FIGS. 6A-6C, an annealing process is performed. The annealing process causes dopant from SPD source/drain features 240 to diffuse into fin structure 204)
Regarding Claim 8, Tsai further discloses wherein performing doping processing on the upper part of the fin part (204) comprises: forming a Lightly Doped Drain (LDD) region extending inward from an outer wall of the upper part of the fin part by a preset thickness, so as to form at least one of the source region or the drain region. ([0022] Implantation, diffusion, and/or annealing processes may be performed to form lightly doped source and drain (LDD) features in fin structure 204 before and/or after forming seal spacers 232, offset spacers 234, and/or dummy spacers 236. )
Regarding Claim 10, Tsai further discloses (as shown in Fig. 6A) wherein performing doping processing on the upper part of the fin part (204) comprises: forming a doped region ([0026] in FIG. 6B and FIG. 6C, dopant diffuse vertically from SPD source/drain features 240 disposed over top surface 242 into fin structure 204, and dopant diffuse laterally from SPD source/drain features 240 disposed over side surface 244 and side surface 246 into fin structure 204. Source region 207 and drain region 208 are thus uniformly doped to form heavily doped source/drain (HDD) features 250 in fin structure 204.)
occupying a whole thickness of the upper part of the fin part, ([0026] In some implementations, a doping concentration in HDD features 250 is substantially the same across a width of HDD features 250 (for example, from sidewall surface 244 to sidewall surface 246). In some implementations, a doping concentration in HDD features 250 is substantially the same across a depth of heavily doped features 250 (for example, from top surface 242 to a boundary 252 of HDD features 250 (note that, in some implementations, HDD features 250 may extend from top surface 242 to substrate 202)).)(See Fig. 6A, showing the HDD feature 250 occupies the area of the fin above the isolation features 210)
so as to form at least one of the source region or the drain region. ([0026] Source region 207 and drain region 208 are thus uniformly doped to form heavily doped source/drain (HDD) features 250 in fin structure 204.)
Regarding Claim 13, Tsai further discloses (as shown in Fig. 6A) wherein the upper part of the fin part (204) comprises a top region and a bottom region, (See An. Fig. 6A below)
the bottom region being close to the top surface of the substrate (202), (See An. Fig. 6, showing the bottom portion of the upper part of the fin is located closer to the top surface of the substrate 202)
the top region being located above the bottom region, (See An. Fig. 6, showing the top portion of the upper part of the fin located on the bottom portion of the upper part of the fin)
and at least one of the source region or the drain region (250) being located in the top region. (See An. Fig. 6A, showing the HDD source/drain region 250 being located, at least in part, in the top portion of the upper part of the fin)
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Regarding Claim 15, Tsai further discloses (as shown in Figs. 3A-4A) wherein before performing doping processing on the upper part of the fin part, the method further comprises:
forming a gate structure on the upper part of the fin part; ([0020] In FIG. 3A and FIG. 3B, a gate structure 220 is formed over fin structure 204.)
and performing doping processing on a region, exposed outside the gate structure, of the upper part of the fin part. ([0020] Gate structure 220 interposes source region 207 and drain region 208.) ([0025] The annealing process causes dopant from SPD source/drain features 240 to diffuse into fin structure 204, particularly into source region 207 and drain region 208. )
Regarding Claim 16, Tsai further discloses (as shown in Figs. 7A) the fin transistor structure ([0030] FinFET device 200) being manufactured by the method for manufacturing a fin transistor structure of claim 1. ([0030] FinFET device 200 can undergo subsequent processing to complete fabrication. )
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tsai as applied to claim 1 above.
Regarding Claim 11, Tsai fails to disclose wherein arranging a diffusion region (240) comprises: forming a mask layer on the isolation layer (210), the mask layer being provided with a mask opening, and the mask opening exposing the upper part of the fin (204) and forming the diffusion region (240).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the application, based on the teachings of Tsai, to form a mask layer on the isolation layer (210), the mask layer being provided with a mask opening, and the mask opening exposing the upper part of the fin (204) and form the diffusion region (240). Tsai teaches that the diffusion region is formed by selective epitaxial growth of SPD source/drain features (240) ([0023] For example, a selective epitaxial growth (SEG) process is performed to grow a semiconductor material on exposed portions of fin structure 204, thereby forming epitaxial source/drain features 240 over source region 207 and drain region 208.) Selective epitaxial growth is a well-known technique that involves local growth of an epitaxial layer through a patterned dielectric mask. Therefore, it would have been obvious for the SEG process of Tsai to include a mask layer with an opening and performing the growth (formation of the diffusion region) inside of the opening.
Claim(s) 3, 5, 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tsai as applied to claim 2 above.
Regarding Claim 3, Tsai further discloses (as shown in Fig. 6A) performing annealing processing on the SPD source/drain features (240) ([0025] The annealing process causes dopant from SPD source/drain features 240 to diffuse into fin structure 204)
Tsai fails to disclose that wherein performing diffusion doping processing on the upper part of the fin part (204) located in the diffusion region comprises:
spin-coating doping gel in the diffusion region, the doping gel covering the upper part of the fin part (204);
and performing annealing processing on the doping gel.
Tsai teaches that the SPD source/drain features can be grown by any suitable SEG process. ([0024] The SEG process can implement CVD deposition techniques (for example, vapor-phase epitaxy (VPE), ultra-high vacuum CVD (UHV-CVD), LPCVD, and/or PECVD), molecular beam epitaxy, other suitable SEG processes, or combinations thereof). Spin-on Coating is a well-known form of epitaxial growth. Therefore, it would have been obvious to a person having ordinary skill in the art to use spin-on coating as the method for SEG of the SPD source/drain features.
Regarding Claim 5, Tsai further discloses wherein performing annealing processing comprises: controlling an annealing temperature in a range of 700°C-1200°C and controlling an annealing time in a range of O.5h-2h.([0035] In some implementations, the MWA process is performed with a temperature in a range from about 500° C. to about 750° C., a power in a range from about 8 kW to about 18 kW, and a time of about 150 seconds to about 300 seconds.)
Claim Interpretation Note: the term “0.5h-2h” is being interpreted as including time lower than 30 minutes based on the 112b issues listed earlier.
The claimed temperature range (700°C-1200°C) overlaps the prior art temperature range (about 500° C. to about 750° C), therefore it would have been obvious to perform the anneal in the overlapping range (700°C-750°C).
Regarding Claim 17, Tsai further discloses (as shown in Figs. 7A) wherein the doping gel (240) contains a doping element. ([0023] Epitaxial source/drain features 240 are heavily doped with n-type dopants and/or p-type dopants, such that epitaxial source/drain features 240 are configured to function as solid phase diffusion (SPD) layers.)
Claim(s) 8-9, 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tsai (‘170) as applied to claim 1 above, and further in view of Tsai et. al (US 2017/0250278 A1)
Regarding Claim 8, Tsai (‘170) further discloses forming a Lightly Doped Drain (LDD) region. ([0022] Implantation, diffusion, and/or annealing processes may be performed to form lightly doped source and drain (LDD) features in fin structure 204)
However, Tsai (‘170) fails to disclose that the Lightly Doped Drain (LDD) region extends inward from an outer wall of the upper part of the fin part by a preset thickness, so as to form at least one of the source region or the drain region.
Tsai (‘278) discloses (as shown in Fig. 4) forming a Lightly Doped Drain (LDD) ([0026] the LDD regions 117) region extending inward from an outer wall of the upper part of the fin part ([0013] semiconductor fins 102) by a preset thickness ([0023] Due to the range of arriving angles of the plasma ions, the doped regions 116 are more uniform beneath the outer profiles 141 of the semiconductor fins 102.), so as to form at least one of the source region or the drain region. ([0020] A process to form the FET devices includes doping the semiconductor fins 102 to form lightly doped source and drain (LDD) regions.)
Tsai (‘170) teaches that LDD regions can be included in the FinFET device ([0022] Implantation, diffusion, and/or annealing processes may be performed to form lightly doped source and drain (LDD) features in fin structure 204) but fails to disclose the process by which the LDD regions would be formed. Tsai (‘278) teaches a process for forming LDD regions in a FinFET device. It would have been obvious to a person having ordinary skill in the art before the filing date to make the LDD regions in Tsai (‘170) by the process described in Tsai (‘278) since the process in Tsai (‘278) is known to make functional LDD regions in a FinFET.
Regarding Claim 9, Tsai (‘278) further discloses (as shown in Fig. 4) wherein the LDD region (117) is formed by a rapid annealing process. ([0026] The thermal anneal process is performed by a rapid thermal anneal (RTA) process at a temperature between about 800° C. to about 1100° C. After the thermal anneal process is performed, the LDD regions 117 are formed.)
Regarding Claim 18, Tsai (‘170) further discloses forming a Lightly Doped Drain (LDD) region. ([0022] Implantation, diffusion, and/or annealing processes may be performed to form lightly doped source and drain (LDD) features in fin structure 204)
However, Tsai (‘170) fails to disclose that the Lightly Doped Drain (LDD) region extends partially into the upper part of the fin part (204) from a surface (202).
Tsai (‘278) discloses (as shown in Fig. 4) forming a Lightly Doped Drain (LDD) ([0026] the LDD regions 117) region extending partially into the upper part of the fin part (102) from a surface (100). ([0023] Due to the range of arriving angles of the plasma ions, the doped regions 116 are more uniform beneath the outer profiles 141 of the semiconductor fins 102.) ([0020] A process to form the FET devices includes doping the semiconductor fins 102 to form lightly doped source and drain (LDD) regions.)
Tsai (‘170) teaches that LDD regions can be included in the FinFET device ([0022] Implantation, diffusion, and/or annealing processes may be performed to form lightly doped source and drain (LDD) features in fin structure 204) but fails to disclose the process by which the LDD regions would be formed. Tsai (‘278) teaches a process for forming LDD regions in a FinFET device. It would have been obvious to a person having ordinary skill in the art before the filing date to make the LDD regions in Tsai (‘170) by the process described in Tsai (‘278) since the process in Tsai (‘278) is known to make functional LDD regions in a FinFET.
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tsai as applied to claim 1 above, and further in view of Li et. al (CN 102664151 A).
Regarding Claim 12, Tsai fail to disclose wherein performing a mask layer on the substrate (202) comprises: forming a photoresist layer on the substrate (202); and carbonizing the photoresist layer to form the mask layer.
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the application, based on the teachings of Tsai, to form a photoresist layer on the substrate (202). As described above, Tsai teaches forming the diffusion regions (240) by a selective epitaxial growth, which is known to include forming a mask and opening the mask. Photoresist is a well-known masking material.
Li discloses carbonizing the photoresist layer.([0016] The carbonized photoresist is used as a protective layer during high-temperature annealing) ([0013] Set the air pressure of the high-temperature annealing furnace as the first air pressure, heat the SiC wafer for the first time, heat to the first temperature, and maintain the temperature to carbonize the protective layer)
Li teaches that using carbonized photoresist as a protective layer in future annealing processes helps to simplify manufacturing and reduce cost. ([0016] The carbonized photoresist is used as a protective layer during high-temperature annealing, and the preparation of the protective layer can be completed in a high-temperature furnace without using additional equipment, the process is simple, and the production cost is low) Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the application to carbonize the photoresist to use as a protective film in future annealing processes.
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tsai as applied to claim 1 above, and further in view of Chang et. al (US 2021/0226035 A1)
Tsai fails to disclose wherein outer wall surfaces on both sides of the bottom region (An. Fig. 6A, Bottom Portion) in a width direction are provided with isolation parts.
Chang discloses (as shown in Fig. 7) wherein outer wall surfaces on both sides of the bottom region ([0021] lower portion 128b of the fin 128) in a width direction are provided with isolation parts ([0032] fin spacers 134a). ([0021] Portions of the fin spacer layer 134 left standing over and aligned to a lower portion 128b of the fin 128 are referred to as fin spacers 134a.)
Chang teaches that the fin spacers (134a) help in controlling the size of subsequently formed source/drain regions. ([0021] The fin spacers 134a can help controlling a size of the subsequently formed source/drain regions (see FIG. 10), which will be described in further detail below.) Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the application to have outer wall surfaces on both sides of the bottom region (An. Fig. 6A, Bottom Portion) in a width direction in Tsai be provided with isolation parts as in Chang in order to control the size of subsequently formed source/drain regions.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Matsukawa et. al (“Damageless and Conformal Doping for FinFETs by Spin-Coated Phosphorous Doped Silica”; )
Matsukawa discloses (as shown in Fig. 1, 6) wherein performing diffusion doping processing on the upper part of the fin part ([Col. 1 Line 34] Si fin structure) located in the diffusion region comprises:
spin-coating doping gel in the diffusion region, the doping gel covering the upper part of the fin part ([Col. 1 Line 34-35] The Si fin structure is first spin-coated with PDS which is diluted by organic solvent);
and performing annealing processing on the doping gel. ([Col. 1 Line 38-39] Annealing for the P diffusion into the Si fin is carried out subsequently)
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JASON JAMES GREAVING whose telephone number is (703)756-5653. The examiner can normally be reached 7:30am - 5:00 pm.
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/JASON JAMES GREAVING/ Examiner, Art Unit 2893
/Britt Hanley/ Supervisory Patent Examiner, Art Unit 2893