Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
2. It would be of great assistance to the office if all incoming papers pertaining to a filed application carried the following items:
i. Application number (checked for accuracy, including series code and serial no.).
ii. Group art unit number (copied from most recent Office communication).
iii. Filing date.
iv. Name of the examiner who prepared the most recent Office action.
v. Title of invention.
vi. Confirmation number (See MPEP § 503).
Response to Arguments
3. Applicant's arguments with respect to claims have been considered but are moot in view of the new ground(s) of rejection.
4. The Examiner has pointed out particular references contained in the prior art of record within the body of this action for the convenience of the Applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages, paragraph and figures may apply. Applicant, in preparing the response, should consider fully the entire reference as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner.
5. Claim interpretation: When multiple limitations are connected with “OR”, one of the limitations doesn’t have any patentable weight since both of the limitations are optional.
Claim Rejection- 35 USC § 103
6. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5, 7, 14-18, 20-29, 31 & 34-35 are rejected under 35 U.S.C. 103 as being unpatentable over Lehtola et al (Pub No. 2019/0158046) and further in view of Hitomi et al (Pub No. 2020/0412307).
Regarding claim 1, Lehtola et al discloses a load modulation amplifier (Fig. 1 & 4) comprising: a first power amplifier (PA) configured to amplify a first portion of a radio frequency (RF) signal below a threshold level (Para. 68-70: Carrier amplification stage class AB bias amplifier amplify signal which can be lower level signals); and a second PA comprising an N stack of transistor devices configured in a cascode configuration to amplify a second portion of an RF signal that is above the threshold level (Para. 66: Cascode configuration amplifier & Fig. 1 & 4 & Para. 67-70: Amplify portion of the RF signal that is above a threshold level-class C bias inherent threshold which is higher threshold than AB bias), wherein N is a counting number that is greater than one (Fig. 1& 4: 2 stack bipolar transistor within cascode amplifier-32).
Lehtola et al does not explicitly discloses amplify a radio frequency (RF) signal below a power threshold level or above the power threshold level.
In a similar field of endeavor, Hitomi et al disclose amplification system where the amplifier to amplify a first portion of a radio frequency (RF) signal below a threshold level and amplify a second portion of an RF signal that is above the threshold level (Para. 59-60: output power of power amplifying greater than a threshold power and output power of power amplifying is less than a threshold power. Amplify signal S1 and S2).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to use the RF amplification system of Hitomi’s disclosure with the amplification control system, as taught by Lehtola. Doing so would have resulted in effectively controlling the power in wireless system to generate the desire amplified signals to adjust optimum power for better quality signal.
Regarding claim 35, Claim 35 corresponds to claim 1 and is analyzed accordingly.
Regarding claim 2 & 26, Lehtola et al is silent regarding first PA comprises transistor devices that are not stacked. Examiner taking official notice that in RF system transistor can be not stacked. (Vagher et al-Pat 7570111 disclose system using multiple transistors that are not stacked).
Therefore, it would have been obvious to one of the ordinary skilled in the art to use transistors that are not stacked to simplify the RF design.
Regarding claim 3 & 27, Lehtola et al is silent regarding first PA comprises transistor devices that are not stacked. Examiner taking official notice that in RF system transistor can be not stacked and are in common emitter configurations. (Vagher et al disclose system using multiple transistors that are not stacked).
Therefore, it would have been obvious to one of the ordinary skilled in the art to use transistors that are not stacked to simplify the RF design.
Regarding claim 4 & 28, Lehtola et al discloses comprising an output quadrature coupler configured to combine portions of an amplified version of the RF signal (Fig. 4 & 27 & Para. 113).
Regarding claim 5 & 29, Lehtola et al discloses the output quadrature coupler is terminated by a reflective short (Par. 15: Envelope tracking bias circuit coupled to the quadrature amplifier and configured to provide a bias signal to the output transistor of the cascode stage & Para. 113).
Regarding claim 7 & 31, Lehtola et al discloses the output quadrature coupler is terminated by a reflective open (Fig. 27 & 28 & Par. 15: Envelope tracking bias circuit coupled to the quadrature amplifier and configured to provide a bias signal to the output transistor of the cascode stage & Para. 113).
Regarding claim 10 & 34, Lehtola et al discloses ones of the N stack of transistor devices are cascode transistor devices coupled in common base configurations by way of base capacitances coupled to a fixed voltage node (Fig. 4 & Para. 9 & 98-99: Constant bias voltage).
Regarding claim 11, Lehtola et al discloses the fixed voltage node is ground (Fig. 4 & 27 & Para. 9 & 98-99: Constant bias voltage).
Regarding claim 14, Lehtola et al discloses the base capacitances have non-uniform capacitance values configured to maximize output power of the load modulation amplifier (Para. 99: Adjustable capacitance value & Para. 11 & 23 & 67 & 80: load modulation amplifier for max output power).
Regarding claim 15, Lehtola et al discloses the base capacitances have non-uniform capacitance values configured to maximize power-added efficiency of the load modulation amplifier (Para. 99: Adjustable capacitance value & Para. 11 & 23 & 67 & 80: load modulation amplifier for max output power).
Regarding claim 16, Lehtola et al discloses the base capacitances have non-uniform capacitance values configured to maximize linear gain of the load modulation amplifier (Para. 99: Adjustable capacitance value & Para. 33 & 115-116: linearity for the Doherty power amplifier).
Regarding claim 17, Lehtola et al discloses the first PA and the second PA are coupled in parallel (Fig. 4 & 25).
Regarding claim 18, Lehtola et al discloses the first PA is a carrier amplifier and the second PA is a peaker amplifier configured to operate as a Doherty amplifier (Para. 106: Doherty amplifier).
Regarding claim 20, Lehtola et al discloses a third PA coupled in parallel with the first PA and the second PA in a 3-way quadrature coupler configuration (Fig. 26).
Regarding claim 21, Lehtola et al discloses the third PA comprises an M stack of transistor devices configured in a cascode configuration to amplify a portion of the RF signal that is above the threshold level, wherein M is a counting number that is greater than one (Fig. 28-29 & Para. 67-70: Amplify portion of the RF signal that is above a threshold level-class C bias inherent threshold which is higher threshold than AB bias & stack bipolar transistor within cascode amplifier).
Regarding claim 22, Lehtola et al discloses the third PA is configured as a second peaker amplifier (Fig. 28-29).
Regarding claim 23, Lehtola et al the N stack of transistor devices is realized by a dual-gate field-effect transistor device (Para. 8).
Regarding claim 24, Lehtola et al the N stack of transistor devices is realized by a field-effect transistor device having a first field plate and a second field plate, wherein the second field plate is between a gate and a drain (Para. 8-10 & Fig. 28-29).
Regarding claim 25, Lehtola et al discloses a wireless communication device comprising: a baseband processor (Fig. 31: Baseband system-1405); transmit circuitry configured to receive encoded data from the baseband processor and to modulate a carrier signal with the encoded data (Para. 120-121: TX circuitry receive encoded data from the baseband processor and modulate a carrier signal & Para. 80: Load modulation of the carrier signals), wherein the transmit circuitry comprises: a first power amplifier (PA) configured to amplify a first portion of a radio frequency (RF) signal below a threshold level (Para. 68-70: Carrier amplification stage class AB bias amplifier amplify signal which can be lower level signals); and a second PA comprising an N stack of transistor devices configured in a cascode configuration to amplify a second portion of the RF signal that is above the threshold level (Para. 66: Cascode configuration amplifier & Fig. 1 & 4 & Para. 67-70: Amplify portion of the RF signal that is above a threshold level-class C bias inherent threshold which is higher threshold than AB bias), wherein N is a counting number that is greater than one (Fig. 1& 4: 2 stack bipolar transistor within cascode amplifier-32).
Lehtola et al does not explicitly discloses amplify a radio frequency (RF) signal below a threshold level or above the threshold level.
In a similar field of endeavor, Hitomi et al disclose amplification system where the amplifier to amplify a first portion of a radio frequency (RF) signal below a threshold level and amplify a second portion of an RF signal that is above the threshold level (Para. 59-60: output power of power amplifying greater than a threshold power and output power of power amplifying is less than a threshold power. Amplify signal S1 and S2).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to use the RF amplification system of Hitomi’s disclosure with the amplification control system, as taught by Lehtola. Doing so would have resulted in effectively controlling the power in wireless system to generate the desire amplified signals to adjust optimum power for better quality signal.
Claims 6 & 30 are rejected under 35 U.S.C. 103 as being unpatentable over Lehtola et al (Pub No. 2019/0158046), in view of Hitomi et al (Pub No. 2020/0412307) and further in view of Zhu et al (Pub No. 2022/0246553).
Regarding claim 6 & 30, Lehtola et al is silent regarding the output quadrature coupler is terminated by a low complex impedance that is less than 50 ohms.
Zhu discloses the output quadrature coupler is terminated by a low complex impedance that is less than 50 ohms (Para. 20: Impedance range 50 for low complex impedance).
At the time of filling, it would have been obvious to use impedance control system to adjust proper impedance in the RF circuitry.
Claims 8-9 & 32-33 are rejected under 35 U.S.C. 103 as being unpatentable over Lehtola et al (Pub No. 2019/0158046), in view of Hitomi et al (Pub No. 2020/0412307) and further in view of Chen et al (Pub No. 2017/0077966).
Regarding claim 8 & 32, Lehtola et al is silent regarding the output quadrature coupler is terminated by a high complex impedance that is greater than 50 ohms.
Chen et al discloses the output quadrature coupler is terminated by a high complex impedance that is greater than 50 ohms (Para. 46 & 52: high complex impedance that is greater than 50 ohms).
At the time of filling, it would have been obvious to use impedance control system to adjust proper impedance in the RF circuitry.
Regarding claim 9 & 33, Lehtola et al is silent regarding the output quadrature coupler is terminated by substantially 50 ohms.
Chen et al discloses the output quadrature coupler is terminated by substantially 50 ohms. (Para. 33: coupler with amplifier. also see Para. 46 & 52: high complex impedance).
At the time of filling, it would have been obvious to use impedance control system to adjust proper impedance in the RF circuitry.
Claims 12-13 are rejected under 35 U.S.C. 103 as being unpatentable over Lehtola et al (Pub No. 2019/0158046), in view of Hitomi et al (Pub No. 2020/0412307) and further in view of Pehlke David (Pub No. WO 02/054589).
Regarding claim 12, Lehtola et al discloses the base capacitances have non-uniform capacitance values configured of the load modulation amplifier (Para. 99: Adjustable capacitance value & Para. 11 & 23).
Lehtola et al is silent regarding maximize gain.
Pehlke discloses capacitance values configured to maximize gain of the load modulation amplifier (Page. 6: Dual gate FET implementation with a load modulation amplifier as a Doherty amplifier).
At the time of filling, it would have been obvious to use load modulation amplifier to control gain for better output of the system.
Regarding claim 13, Lehtola et al the base capacitances have non-uniform capacitance values configured to a mean time between failure rate of the load modulation amplifier (Para. 99: Adjustable capacitance value & Para. 11 & 23).
Lehtola et al is silent regarding maximize a mean time.
Pehlke discloses non-uniform capacitance values configured to maximize a mean time between failure rate of the load modulation amplifier (Page. 6: Dual gate FET implementation with a load modulation amplifier as a Doherty amplifier).
At the time of filling, it would have been obvious to use load modulation amplifier to control gain for better output of the system.
Claim 19 is/ are rejected under 35 U.S.C. 103 as being unpatentable over Lehtola et al (Pub No. 2019/0158046), in view of Hitomi et al (Pub No. 2020/0412307) and further in view of Burns et al (Pub No. 2006/0006945).
Regarding claim 19, Lehtola et al is silent regarding the first PA and the second PA are both configured as differential amplifiers.
Burns discloses the first PA and the second PA are both configured as differential amplifiers (Para. 47 & 28: differential amplifiers).
At the time of filing, it would have been obvious to use differential amplifier to control RF signals in the amplification stage for better quality signals.
CONCLUSION
Applicant’s amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication from the examiner should be directed to Patent Examiner Md Talukder whose telephone number is (571) 270-3222. The examiner can normally be reached on Mon-Th 8:00 am to 4:30 pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisors, Wesley Kim can be reached on 571-272-7867.
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/MD K TALUKDER/ Primary Examiner, Art Unit 2648
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