DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Foreign priority is not claimed for this application.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 05/09/2023 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Drawings
Figure 1 should be designated by a legend such as --Prior Art-- because only that which is old is illustrated. See MPEP § 608.02(g). Corrected drawings in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. The replacement sheet(s) should be labeled “Replacement Sheet” in the page header (as per 37 CFR 1.84(c)) so as not to obstruct any portion of the drawing figures. If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they do not include the following reference sign(s) mentioned in the description: Page 8, line 15 cites comparator “169” in reference to fig. 2, however, there is no 169 in this figure. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(4) because reference character “165” has been used to designate both the current control block and the operational amplifier. Page 8 lines 22-27 refer to a current control block 165 that is coupled to the operational amplifier. However, in fig. 2, the operational amplifier is labelled as 165. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The disclosure is objected to because of the following informalities:
Page 3, lines 13-14: “via a second transistor” should probably read “via a second resistor”
Page 8, line 8: “The amplifier circuit 151” should probably read “the amplifier circuit 150”
Page 8, line 15: Recites “comparator 169” but there is no 169 in fig. 2
Page 8, lines 22-27: Recites a current control block 165 that is coupled to the operational amplifier; however, number 165 is used in fig. 2 to refer to the operational amplifier
Appropriate correction is required.
Claim Objections
Claims 8 and 14 are objected to because of the following informalities:
Claim 8, line 3: “via a second transistor” should probably read “via a second resistor”
Claim 14, line 1: “wherein the processing the input voltage” should probably read “wherein processing the input voltage”
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 4, 6, 12, 15, and 17 is/are rejected under 35 U.S.C. 102(a)(1) and (a)(2) as being anticipated by US 8779859 by Su et al.
Regarding claim 1, Su teaches a cascode amplifier circuit comprising:
a power amplifier block (Fig. 5 #305) having a first transistor (Fig. 5 #310.1) and a second transistor (Fig. 5 #320);
a bias generator block coupled to the first transistor and being configured to provide a reference voltage to the power amplifier block (Fig. 5 RS1, 430.1L, 430.1U); and
a current control block (Fig. 5 #450) coupled to the second transistor (Fig. 5 #320) of the power amplifier block, the current control block being configured to adjust a gate bias to the second transistor of the power amplifier block to maintain a constant quiescent current.
Regarding claim 4, Su teaches the cascode amplifier circuit of claim 1 wherein the power amplifier block is a first power amplifier block, and the cascode amplifier circuit further includes a second power amplifier block having a third transistor (Fig. 5 #310.1R) and a fourth transistor (Fig. 5 #320R), the bias generator block being coupled to the third transistor and being configured to provide the reference voltage to the second power amplifier block (Fig. 5 RS1, 430.1L, 430.1U are coupled to #310.1R), and the current control block (Fig. 5 #450) being coupled to the fourth transistor (Fig. 5 #320R) and being configured to adjust a gate bias (Fig. 5 Vbias) to the fourth transistor based on a drain voltage between the third and fourth transistors (Fig. 5 V2).
Regarding claim 6, Su teaches the cascode amplifier of claim 4, wherein the current control block is coupled to the second and fourth transistors via a comparator (Fig. 5 OA1) configured to:
compare the drain voltage between the third and fourth transistors with a quiescent voltage provided to the current control block (Fig. 5 VDD_bias); and
adjust the gate voltage to the second and fourth transistors based on the comparison to maintain a constant quiescent current (Fig. 5; Col. 5 lines 55-67, Col. 6 lines 1-4).
Regarding claim 12, Su teaches a method for bias generation for a cascode amplifier circuit, the method comprising:
a bias generator block (Fig. 5 RS1, 430.1L, 430.1U) coupled to a first transistor (Fig. 5 #310.1) of a power amplifier block Fig. 5 #305) providing a reference voltage to the power amplifier block; and
a current control block (Fig. 5 #450) coupled to a second transistor (Fig. 5 #320) of the power amplifier block adjusting a gate bias to the second transistor of the power amplifier block to maintain a constant quiescent current.
Regarding claim 15, Su teaches the method of claim 12 wherein the power amplifier block is a first power amplifier block and the cascode amplifier circuit includes a second power amplifier block having a third transistor (Fig. 5 #310.1R) and a fourth transistor (Fig. 5 #320R), the method further comprising:
the bias generator block coupled to the second power amplifier block providing the reference voltage to the second power amplifier block (Fig. 5 RS1, 430.1L, 430.1U are coupled to #310.1R) and
the current control block (Fig. 5 #450) coupled to the second power amplifier block adjusting a gate bias to the fourth transistor (Fig. 5 #320R) based on a drain voltage between the third and fourth transistors (Fig. 5 V2).
Regarding claim 17, Su teaches the method of claim 15 further comprising:
comparing, by a comparator (Fig. 5 OA1) coupling the current control block to the second (Fig. 5 #320) and fourth transistors (Fig. 5 #320R), the drain voltage between the third and fourth transistors with a quiescent voltage provided to the current control block (Fig. 5 Vdd_bias); and
adjusting the gate voltage to the second and fourth transistors based on the comparison to maintain a quiescent current (Fig. 5; Col. 5 lines 55-67, Col. 6 lines 1-4).
Claim(s) 1-2, 7-13, and 18-20 is/are rejected under 35 U.S.C. 102(a)(1) and (a)(2) as being anticipated by US 20160241195 by Lehtola et al.
Regarding claim 1, Lehtola teaches a cascode amplifier circuit (Fig. 5) comprising:
a power amplifier block having a first transistor and a second transistor (Fig. 5 #551b and #552b);
a bias generator block coupled to the first transistor and being configured to provide a reference voltage to the power amplifier block (Fig. 5 #510); and
a current control block coupled to the second transistor of the power amplifier block, the current control block being configured to adjust a gate bias to the second transistor of the power amplifier block to maintain a constant quiescent current (Fig. 5 #520b, Par. 52).
Regarding claim 2, Lehtola teaches the cascode amplifier circuit of claim 1, wherein the bias generator block is a cascode bias generator block and is configured to:
receive an input voltage (Fig. 5 Vbatt);
process the input voltage; and
provide the reference voltage based on the processed input voltage (Par. 49, 53, 54).
Regarding claim 7, Lehtola teaches the cascode amplifier circuit of claim 1 wherein the power amplifier block includes a matching circuit (Fig. 5 #560a-c).
Regarding claim 8, Lehtola teaches the cascode amplifier circuit of claim 1 wherein the bias generator block (Fig. 5 #510) is coupled to the first transistor (Fig. 5 #551b) via a first resistor (Fig. 5 #542b), and the current control block (Fig. 5 #520b) is coupled to the second transistor (Fig. 5 #552b) via a second transistor (Fig. 5 #544b), the first and second resistors being configured to prevent radio frequency swing.
Regarding claim 9, Lehtola teaches the cascode amplifier circuit of claim 1 wherein the bias generator block includes a constant voltage source configured to provide a constant voltage to the power amplifier block (Fig. 5 Vbatt).
Regarding claim 10, Lehtola teaches a radio frequency module (Fig. 5) comprising:
a cascode amplifier circuit (Fig. 5) including:
a power amplifier block configured to provide a radio frequency signal (Fig. 5 output of cascode stages),
the power amplifier block including a first transistor and a second transistor (Fig. 5 #551b and #552b);
a bias generator block coupled to the first transistor and being configured to provide a reference voltage to the power amplifier block (Fig. 5 #510); and
a current control block coupled to the second transistor of the power amplifier block, the current control block being configured to adjust a gate bias to the second transistor of the power amplifier block to maintain a constant quiescent current (Fig. 5 #520b); and
a filter configured to filter the radio frequency signal (Par. 12).
Regarding claim 11, Lehtola teaches a wireless communication device (Fig. 5, Par. 18) comprising:
a cascode amplifier circuit (Fig. 5) including:
a power amplifier block configured to provide a radio frequency signal (Fig. 5 output of cascode stages),
the power amplifier block including a first transistor and a second transistor (Fig. 5 #551b and #552b);
a bias generator block coupled to the first transistor and being configured to provide a reference voltage to the power amplifier block (Fig. 5 #510); and
a current control block coupled to the second transistor of the power amplifier block, the current control block being configured to adjust a gate bias to the second transistor of the power amplifier block to maintain a constant quiescent current (Fig. 5 #520b); and
a filter configured to filter the radio frequency signal (Par. 12); and
an antenna configured to transmit the filtered radio frequency signal (Fig. 9 #416).
Regarding claim 12, Lehtola teaches a method for bias generation for a cascode amplifier circuit (Fig. 5), the method comprising:
a bias generator block (Fig. 5 #510) coupled to a first transistor (Fig. 5 #551b) of a power amplifier block providing a reference voltage to the power amplifier block; and
a current control block (Fig. 5 #520b) coupled to a second transistor (Fig. 5 #552b) of the power amplifier block adjusting a gate bias to the second transistor of the power amplifier block to maintain a constant quiescent current.
Regarding claim 13, Lehtola teaches the method of claim 12, wherein
the bias generator block is a cascode bias generator block and is the method further comprises the cascode bias generator block:
receiving an input voltage (Fig. 5 Vbatt);
processing the input voltage; and
providing the reference voltage based on the processed input voltage (Par. 49, 53, 54).
Regarding claim 18, Lehtola teaches the method of claim 12 wherein the power amplifier block includes a matching circuit (Fig. 5 #560a-c).
Regarding claim 19, Lehtola teaches the method of claim 12, further comprising using a first resistor (Fig. 5 #542b) coupling the bias generator block (Fig. 5 #510) to the first transistor (Fig. 5 #551b) and a second resistor (Fig. 5 #544b) coupling the current control block (Fig. 5 #520b) to the second transistor (Fig. 5 #552b) to prevent radio frequency swing.
Regarding claim 20, Lehtola teaches the method of claim 12 further comprising the bias generator block providing a constant voltage to the power amplifier block (Fig. 5 #510 is coupled to constant voltage Vbatt).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 3 and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lehtola as applied to claims 1-2, 7-13, and 18-20 above, and further in view of US 8228125 by Heijden et al.
Regarding claim 3, Lehtola teaches the cascode amplifier circuit of claim 2, but fails to teach that the cascode bias generator circuit further includes an adder configured to add an offset voltage when processing the input voltage.
However, Heijden teaches a cascode amplifier (Fig. 2, 4), wherein the cascode bias generator circuit (seen annotated figure) further includes an adder (adder node between the offset voltage source and the voltage divider) configured to add an offset voltage (Fig. 2 #29, 290) when processing the input voltage (Col. 3 lines 39-52, Col. 4 lines 32-41).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to combine Heijden with Lehtola in order to have a cascode amplifier circuit with an offset voltage to optimize impedance efficiency of the amplifier (Heijden Col. 4 lines 12-14).
Regarding claim 14, Lehtola teaches the method of claim 13, but fails to teach wherein the processing the input voltage includes an adder of the cascode bias generator circuit adding an offset voltage to the input voltage.
However, Heijden teaches a cascode amplifier circuit (Fig. 2, 4) wherein the processing the input voltage includes an adder of the cascode bias generator circuit (see annotated figure) adding an offset voltage (Fig. 2 #29, #290) to the input voltage (Col. 3 lines 39-52, Col. 4 lines 32-41).
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It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to combine Heijden with Lehtola in order to have a cascode amplifier circuit with an offset voltage to optimize impedance efficiency of the amplifier (Heijden Col. 4 lines 12-14).
Annotated Figure of Heijden
Claim(s) 5 and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Su as applied to claims 1, 4, 6, 12, 15, and 17 above, and further in view of US 7629853 by Oishi.
Regarding claim 5, Su teaches the cascode amplifier of claim 4, but fails to teach that the bias generator block is coupled to the first and third transistors via a comparator configured to:
compare the reference voltage with the drain voltage between the third and fourth transistors; and
adjust a gate voltage provided to the first and third transistors to make the drain voltage between the third and fourth transistors and a drain voltage between the first and second
transistors equal to the reference voltage.
However, Oishi teaches a cascode amplifier circuit with a bias circuit wherein the bias generator block (Fig. 5 #502, Fig.7) is coupled to the first and third transistors (Fig. 7 AUXFET2 and FET2) via a comparator (Fig. 5, 7, #50) configured to:
compare the reference voltage with the drain voltage between the third and fourth transistors (Fig. 5, 7, A(V1’)); and
adjust a gate voltage provided to the first and third transistors to make the drain voltage between the third and fourth transistors (Fig. 7 AUXFET2 and AUXFET1) and a drain voltage between the first and second
transistors equal to the reference voltage (Fig. 5, Fig. 7, Col. 4 lines 59-66).
It would have been obvious to combine Oishi with Su in order to have a cascode amplifier with a comparator coupled to the bias generator circuit. This would help stabilize the amplifier (Background section of Oishi).
Regarding claim 16, Su teaches the method of claim 15, but fails to teach comparing, by a comparator coupling the bias generator block to the first and third transistors, the reference voltage with the drain voltage between the third and fourth transistors; and adjusting a gate voltage provided to the first and third transistors to make the drain voltage between the third and fourth transistors and the drain voltage between the first and second transistors equal to the reference voltage.
However, Oishi teaches a cascode amplifier with a bias circuit that compares, by a comparator (Fig. 5, 7, #50) coupling the bias generator block to the first and third transistors (Fig. 7 AUXFET2 and FET2), the reference voltage with the drain voltage between the third and fourth transistors (Fig. 7 AUXFET1 and AUXFET 2); and
adjusting a gate voltage provided to the first and third transistors to make the drain voltage between the third and fourth transistors and the drain voltage between the first and second transistors equal to the reference voltage (Fig. 5, Fig. 7, Col. 4 lines 59-66).
It would have been obvious to combine Oishi with Su in order to have a cascode amplifier with a comparator coupled to the bias generator circuit. This would help stabilize the amplifier (Background section of Oishi).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 10291194 by Ilkov et al. teaches a cascode amplifier circuit with a bias generator block and replica transistors.
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/NAREH SHAMIRYAN/Examiner, Art Unit 2843
/ANDREA LINDGREN BALTZELL/Supervisory Patent Examiner, Art Unit 2843
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