DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
RESPONSE TO AMENDMENT
Claim rejections based on prior art
Applicant's arguments filed on 03/11/2026 with respect to claims 1-15 have been fully considered but are moot in view of newly cited reference.
REJECTIONS BASED ON PRIOR ART
Claim Rejections - 35 USC § 103
1. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
2. Claims 1-3, 5-7, 9-11 and 13-15 are rejected under 35 U.S.C. 103(a) as being unpatentable over Shiva K et al. (US pub. 2021/0405919), hereinafter, “Shiva”, in view of Lee et al. (US pub. # 2018/0113776), hereinafter, “Lee”.
At the outset, Applicant is reminded that claims subject to examination will be given their broadest reasonable interpretation in light of the supporting disclosure. In re Morris, 127 F.3d 1048, 1054-55, 44 USPQ2d 1023,1027-28 (Fed. Cir. 1997). With this in mind, the discussion will focus on how the terms and relationships between the terms in the claims are met by the references.
3. As per claims 1, 5 and 9, Shiva discloses an electronic device (storage system 100 of fig. 4, as discloses in paragraph 0049), comprising: an M.2 connector (plug connector 400) having a first pin and a second pin (see paragraph 0049); a system circuit (SATA interface 410 and PCIe interface 440, combined), having a first power supply and configured to provide a reset signal (see paragraph 0049); a protection circuit (switch positioned between connector 400 and the combination of SATA interface 410 and PCIe interface 440), coupled between the system circuit and the M.2 connector and coupled to the first pin and the second pin (see fig. 4); and a processor (storage system controller 420 and NVMe controller 450, combined), coupled to the M.2 connector and the protection circuit (see fig. 4).
Shiva fails to expressly disclose a processor configured to determine whether a module inserted into the M.2 connector is a 4G module or a 5G module, wherein in response to that the processor determines that the module inserted into the M.2 connector is the 4G module, the processor causes the protection circuit to execute a protection process, and in response to that the processor determines that the module inserted into the M.2 connector is the 5G module, the processor causes the protection circuit not to execute the protection process; wherein, in the protection process, the protection circuit blocks an electrical connection between the first pin and the first power supply of the system circuit and blocks an electrical connection between the second pin and the reset signal provided by the system circuit; wherein, when the protection process is not executed, the protection circuit allows the electrical connection between the first pin and the first power supply and allows the electrical connection between the second pin and the reset signal.
Lee discloses a processor (see paragraph 0019, which teaches switching control unit 15 being a microcontroller) configured to determine whether a module inserted into the M.2 connector [connector 11; see paragraph 0017, which discloses “the connector 11 complies with the M.2 standard”) having a first pin (pins 41, 43, 45, 47 and 49, combined; see fig. 4 and paragraph 0007) and a second pin (pins 50, 52 and 54, combined; see fig. 4)] is a 4G module (a USB 3.0 communication device, host) or a 5G module (a PCIe communication device, host) (see paragraph 0034, which discloses “moreover, if the detecting result of the third detecting operation indicates that the output signal is received by Pin 29, Pin 31, Pin 35 and Pin 37, the switching control unit 15 further judges whether the communication protocol of the host 2 is the PCIe communication protocol or the USB 3.0 communication protocol according to a second predetermined judging rule”), wherein in response to that the processor determines that the module inserted into the M.2 connector is the 4G module, the processor causes the protection circuit [see paragraphs 0033 and 0034, which teach switching control unit 15 performing the function of selecting/protecting different firmware units, particularly, different voltage ranges for respective firmware units] to execute a protection process (a USB 3.0 communication protocol) (see paragraph 0024, which discloses “FIG. 4 schematically illustrates the pin definitions connector of the M.2 connector of the electronic card of FIG. 1 according to the USB 3.0 communication protocol. When the electronic card 1 and the host 2 are in communication with each other according to the USB 3.0 communication protocol, Pin 29, Pin 31, Pin 35 and Pin 37 receive the output signal from the host 2. Consequently, the electronic card 1 is in communication with host 2 through Pin 29, Pin 31, Pin 35 and Pin 37”), and in response to that the processor determines that the module inserted into the M.2 connector is the 5G module, the processor causes the protection circuit not to execute the protection process (not executing the USB 3.0 communication protocol; see paragraph 0023, which discloses “FIG. 3 schematically illustrates the pin definitions connector of the M.2 connector of the electronic card of FIG. 1 according to the PCIe communication protocol. When the electronic card 1 and the host 2 are in communication with each other according to the PCIe communication protocol, Pin 41, Pin 43, Pin 47 and Pin 49 receive the output signal from the host 2. Consequently, the electronic card 1 is in communication with the host 2 through Pin 41, Pin 43, Pin 47 and Pin 49”. In other words, during the execution of the PCIe communication protocol, the USB 3.0 communication protocol is not executed); wherein, in the protection process (see fig. 4, which shows during an execution of the USB 3.0 communication protocol), the protection circuit blocks an electrical connection between the first pin and the first power supply of the system circuit (see fig. 4, which shows pin 41, pin 43, pin 47 or pin 49, which is part of the ‘first pin’, being on a ‘N/C” state and blocked from a power supply) and blocks an electrical connection between the second pin and the reset signal provided by the system circuit (see fig. 4, which shows pin 50, pin 52 or pin 54, which is part of the ‘second pin’, being on a ‘N/C” state and blocked from a ‘reset’ signal); wherein, when the protection process is not executed (not executing the USB 3.0 communication protocol; see figs. 2 and 3, showing the execution of SATA and PCIe, not USB in pins 29, 31, 35 and 37), the protection circuit allows the electrical connection between the first pin and the first power supply (see fig. 2, which shows SATA communication protocol, power, in pin 41, pin 43, pin 47 or pin 49) and allows the electrical connection between the second pin and the reset signal (see fig. 3, which shows, during a PCIe communication protocol, pin 50, pin 52 or pin 54, which is part of the ‘second pin’, receiving a signal that is equated to a ‘reset’ signal; again, the claim language doesn’t disclose what is a ‘reset’ signal or the source of the signal).
It would have been obvious to one having ordinary skills in the art before the effective filling date of the claimed invention to incorporate Lee’s teaching of electronic card to judge if a communication protocol of a host is a SATA communication protocol, a PCIe communication protocol or a USB3.0 communication protocol, into Shiva’s teaching of a dual-Interface storage system comprising a connector compatible with both a first host interface and a second host interface, for the benefit of automatically detecting the communication protocol of a host connected to a card and select a corresponding communication protocol.
4. As per claims 2, 6 and 10, the combination of Shiva and Lee discloses “The electronic device according to claim 1” [See rejection to claim 1 above], wherein a pin number of the first pin is 24 (see fig. 4 of Lee. Note, the number 24 is within number 41, 43 or 45), and a pin number of the second pin is 50 (see fig. 4).
5. As per claims 3, 7 and 11, the combination of Shiva and Lee discloses “The electronic device according to claim 1” [See rejection to claim 1 above], further comprising: a controller (an activated SATA interface 410 or PCIe interface 440 of Shiva), coupled between the processor and the protection circuit (see fig. 4 of Shiva) and configured to control the protection circuit according to a control flag (a signal definition, as discloses in paragraph 0035 of Lee); wherein, in response to that the processor determines that the module inserted into the M.2 connector is the 4G module, the processor sets the control flag as a 4G flag, such that the controller causes, according to the 4G flag, the protection circuit to execute the protection process; and wherein, in response to that the processor determines that the module inserted into the M.2 connector is the 5G module, the processor sets the control flag as a 5G flag, such that the controller causes, according to the 5G flag, the protection circuit not to execute the protection process (see paragraph 0035 of Lee).
6. As per claims 13-15, the combination of Shiva and Lee discloses “The computer-implemented method according to claim 9” [See rejection to claim 9 above], wherein the processor is not directly coupled to the system circuit (see fig. 4 of Shiva, which shows a data from either controller 420 or 450 being stored in storage 430 or 460 and reading that data back from the storage, passing via/through controller 420 or 450, the controller not directly ‘coupling’ to SATA interface 410 or PCIe interface 440).
7. Claims 4, 8 and 12 are rejected under 35 U.S.C. 103(a) as being unpatentable over Shiva K et al. (US pub. 2021/0405919), hereinafter, “Shiva”, in view of Lee et al. (US pub. # 2018/0113776), hereinafter, “Lee”, and further in view of Subramanian et al. (US pub. 2016/0327602), hereinafter, “Subramanian”.
8. As per claims 4, 8 and 12, the combination of Shiva and Lee discloses “The electronic device according to claim 1” [See rejection to claim 1 above], including wherein the protection circuit comprises: a switch module coupled between the first pin and the first power supply, wherein in the protection process, the switch module disconnects the electrical connection between the first pin and the first power supply (see paragraphs 0034 and 0035 of Lee), but fails to expressly discloses a tristate buffer having an input terminal and an output terminal, wherein the input terminal is coupled to the reset signal, and the output terminal is coupled to the second pin, and wherein in the protection process, the output terminal of the tristate buffer is in a high-impedance state.
Subramanian a tristate buffer (tristate buffers 506, 508, as discloses in paragraph 0040) having an input terminal and an output terminal, wherein the input terminal is coupled to the reset signal, and the output terminal is coupled to the second pin, and wherein in the protection process, the output terminal of the tristate buffer is in a high-impedance state (see paragraphs 0042 and 0043).
It would have been obvious to one having ordinary skills in the art before the effective filling date of the claimed invention to incorporate Subramanian’s teaching of a circuitry for a removable card to detect and prevent short circuits while connecting to another device, such as a host device that receives a memory card, into Shiva’s teaching of a dual-Interface storage system comprising a connector compatible with both a first host interface and a second host interface and Lee’s teaching of electronic card to judge if a communication protocol of a host is a SATA communication protocol, a PCIe communication protocol or a USB3.0 communication protocol, for the benefit of using tristate buffers to reduce short circuits in removable/connectable media.
CLOSING COMMENTS
Conclusion
a. STATUS OF CLAIMS IN THE APPLICATION
The following is a summary of the treatment and status of all claims in the application as recommended by M.P.E.P. 707.07(i):
a(1) CLAIMS REJECTED IN THE APPLICATION
Per the instant office action, claims 1-15 have received a final action on the merits.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
b. DIRECTION OF FUTURE CORRESPONDENCES
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Ernest Unelus whose telephone number is (571) 272-8596. The examiner can normally be reached on Monday to Friday 9:00 AM to 5:00 PM.
IMPORTANT NOTE
If attempts to reach the above noted Examiner by telephone are unsuccessful, the Examiner's supervisor, Mr. Idriss Alrobaye, can be reached at the following telephone number: Area Code (571) 270-1023.
The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free).
/Ernest Unelus/
Primary Examiner
Art Unit 2181
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