Prosecution Insights
Last updated: April 19, 2026
Application No. 18/167,743

POWER CONVERTER

Non-Final OA §102§103
Filed
Feb 10, 2023
Examiner
GBLENDE, JEFFREY A
Art Unit
2838
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Virginia Tech Intellectual Properties Inc. (Vtip)
OA Round
1 (Non-Final)
85%
Grant Probability
Favorable
1-2
OA Rounds
2y 5m
To Grant
94%
With Interview

Examiner Intelligence

Grants 85% — above average
85%
Career Allow Rate
680 granted / 796 resolved
+17.4% vs TC avg
Moderate +9% lift
Without
With
+8.9%
Interview Lift
resolved cases with interview
Typical timeline
2y 5m
Avg Prosecution
16 currently pending
Career history
812
Total Applications
across all art units

Statute-Specific Performance

§101
1.2%
-38.8% vs TC avg
§103
52.2%
+12.2% vs TC avg
§102
21.2%
-18.8% vs TC avg
§112
22.2%
-17.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 796 resolved cases

Office Action

§102 §103
DETAILED ACTION This action is in response to the application filed on 2/10/2023. Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Specification The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. Claim Objections Claims 9 and 12 are objected to because of the following informalities: Regarding claim 9, the limitation “the instantaneous” lacks proper antecedent basis and should be written as “an instantaneous”. Regarding claim 12, the limitation “the instantaneous” lacks proper antecedent basis and should be written as “an instantaneous”. Appropriate correction is required. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1-6, 10-11, and 14-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Zhang (US Patent 9537421). Zhang et al. discloses (see fig. 1, 2, and 6) a power converter, comprising: at least one leg (626, 628, 630) including: a first string including a plurality of switching units (608, 610), a plurality of unidirectional current switches (622, 624), a first connecting node (node between 614), a second connecting node (616), wherein the first string is operatively coupled across a first and a second bus (connection across 620 and 642), and a second string (string comprising 632 and 634) operatively coupled to the first string via the first connecting node and the second connecting node (connection to 614 and 616), wherein the second string comprises a plurality of unidirectional current switches (632 and 634) and a fourth connecting node (node between 632 and 634) operatively coupled to a fourth bus (C phase); and a controller configured to control switching of the plurality of switching units (108). Regarding claim 2, Zhang et al. discloses (see fig. 1, 2, and 16) that each unidirectional current switch comprises a diode (see diode in 320). Regarding claim 3, Zhang et al. discloses (see fig. 1, 2, and 16) that each unidirectional current switch comprises a silicon controlled rectifier (see 322), a silicon controlled rectifier with an antiparallel diode, or a silicon controlled rectifier with an antiparallel identical silicon controlled rectifier. Regarding claim 4, Zhang et al. discloses (see fig. 1, 2, and 16) that the plurality of switching units comprises a half bridge converter (see 320), a full bridge converter or a hybrid full bridge converter. Regarding claim 5, Zhang et al. discloses (see fig. 1, 2, and 16) that the first string further comprises a first branch (314) and a second branch (316), the first branch being operatively coupled to the second branch via a third connecting node (connection at 330 node). Regarding claim 6, Zhang et al. discloses (see fig. 1, 2, and 16) that the third connecting node is operatively coupled to a third bus (330 node connection to bus). Regarding claim 10, Zhang et al. discloses (see fig. 1, 2 and 6) that the first branch comprises a first set of switching units of the plurality of switching units of the first string (320) and a first unidirectional current switch of the plurality of unidirectional current switches of the first string (322), and the second branch comprises a second set of switching units of the plurality of switching units of the first string (324) and a second unidirectional current switch of the plurality of unidirectional current switches of the first string (328), wherein: the first set of switching units is operatively coupled across the first bus and to the first connecting node (320 connection between +VDC and 310), the first unidirectional current switch being operatively coupled to the first connecting node and to the third connecting node (322 connection between node 310 and node 318), and the second set of switching units is operatively coupled across the second bus and to the second connecting node (324 connection between -Vdc and 312), and the second unidirectional current switch being operatively coupled to the second connecting node and to the third connecting node (S4 connection between 318 and 312). Regarding claim 11, Zhang et al. discloses (see fig. 1, 2 and 6) that the first bus comprises a positive direct current bus (+Vdc) and the second bus comprises a negative direct current bus (-Vdc). Regarding claim 14, Zhang et al. discloses (see fig. 1, 2, and 6) that the second string comprises a first portion (S2) and a second portion (S3), the first portion being operatively coupled to the second portion via the fourth connecting node (connection node between S2 and S3), wherein: the first portion comprises a first unidirectional current switch of the plurality of unidirectional current switches of the second string (S2), and the second portion comprises a second unidirectional current switch of the plurality of unidirectional current switches of the second string (S3), wherein: the first unidirectional current switch is operatively coupled to the first connecting node and to the fourth connecting node (connection of S2 between 310 and node between S2 and S3), and the second unidirectional current switch is operatively coupled to the second connecting node and to the fourth connecting node (S3 connection between 312 and node between S2 and S3). Regarding claim 15, Zhang et al. discloses (see fig. 7 and 8) that the controller is configured to operate each of the one or more legs in a positive state or a negative state (see states in fig. 7 and 8). Regarding claim 16, Zhang et al. discloses (see fig. 1, 2, and 6) a system for power conversion, comprising: a power source (102), a load or source (106), a power converter (104), comprising: one or more legs (626, 628, 630), wherein each of the one or more legs comprises: a first string including a plurality of switching units (608, 610), a plurality of unidirectional current switches (622, 624), a first connecting node (node between 614), a second connecting node (616), wherein the first string is operatively coupled across a first and a second bus (connection across 620 and 642), and a second string (string comprising 632 and 634) operatively coupled to the first string via the first connecting node and the second connecting node (connection to 614 and 616), wherein the second string comprises a plurality of unidirectional current switches (632 and 634) and a fourth connecting node (node between 632 and 634) operatively coupled to a fourth bus (C phase); and a controller configured to control switching of the plurality of switching units (108). Regarding claim 17, Zhang et al. discloses (see fig. 1, 2, and 6) that the controller is further configured to regulate energy stored in the first string during a line cycle (see column 8 lines 23-45). Regarding claim 18, Zhang et al. discloses (see fig. 1, 2, and 6) that the second string comprises a first portion (S2) and a second portion (S3). Regarding claim 19, Zhang et al. discloses (see fig. 1, 2, and 6) that the first and second portions of the second string are operatively coupled to an alternating current phase (S2 and S3 connection to 336). Regarding claim 20, Zhang discloses (see fig. 1, 2, and 6) a power for power conversion, comprising: a power source (102), a load or source (106), a power converter (104), comprising: one or more legs (626, 628, 630), wherein each of the one or more legs comprises: a first string including a plurality of switching units (608, 610), a plurality of unidirectional current switches (622, 624), a first connecting node (node between 614), a second connecting node (616), and a third connecting node (618), wherein the first string is operatively coupled across a first and a second bus (connection across 620 and 642), and the third connecting node of the one of more legs are operatively connected to each other (618 connection to each other) and a second string (string comprising 632 and 634) operatively coupled to the first string via the first connecting node and the second connecting node (connection to 614 and 616), wherein the second string comprises a plurality of unidirectional current switches (632 and 634) and a fourth connecting node (node between 632 and 634) operatively coupled to a fourth bus (C phase); and a controller configured to control switching of the plurality of switching units (108). Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claim(s) 7-9 and 12-13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhang et al. (US Patent 9537421) in view of Takizawa (US Patent 9136775). Regarding claim 7, Zhang et al. discloses (see fig. 1, 2 and 6) that the first branch comprises a first set of switching units of the plurality of switching units of the first string (320) and a first unidirectional current switch of the plurality of unidirectional current switches of the first string (322), and the second branch comprises a second set of switching units of the plurality of switching units of the first string (324) and a second unidirectional current switch of the plurality of unidirectional current switches of the first string (328). Zhang et al. does not disclose that the first set of switching units is operatively coupled to the first connecting node and to the third connecting node, the first connecting node being operatively coupled to the first bus with the first unidirectional current switch, and the second set of switching units is operatively coupled to the second connecting node and to the third connecting node, the second connecting node being operatively coupled to the second bus with the second unidirectional current switch. Takizawa discloses (see fig. 14 and 16) that a first set of switching units is operatively coupled to a first connecting node and to a third connecting node (S2/S3 connection to node between S1/S2 and node between S3/S4), the first connecting node being operatively coupled to a first bus with a first unidirectional current switch (node between S1/S2 connected to P bus through S1), and a second set of switching units is operatively coupled to a second connecting node and to the third connecting node (S4/S5 connection to node between S5/S6 and node between S3/S4), the second connecting node being operatively coupled to a second bus with the second unidirectional current switch (node between S5/S6 connected to N bus through S6). Therefore it would have been obvious to one having ordinary skill in the art at the time the invention was filed to modify the converter of Zhang et al. to include the features of Takizawa because its used as a means to generate fewer harmonics at a low order and reduce potential switching loss regarding the switching devices, thus increasing operational efficiencies. Regarding claim 8, Zhang et al. discloses (see fig. 1, 2 and 6) that the first bus comprises a positive direct current bus (+Vdc) and the second bus comprises a negative direct current bus (-Vdc). Regarding claim 9, Zhang et al. discloses (see fig. 1, 2 and 6) that the fourth connecting node (node between 632 and 634) is operatively coupled to a fourth bus comprising an alternating current phase (C phase). Zhang et al. discloses the claimed invention except for the voltage between the first bus and the second bus being greater than the instantaneous maximal alternating current phase voltage. It would have been obvious to one having ordinary skill in the art at the time the invention was filed to have the voltage between the first bus and the second bus be greater than the instantaneous maximal alternating current phase voltage, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F2.d 272, 205 USPQ 215 (CCPA 1980). Therefore it would have been obvious to one having ordinary skill in the art at the time the invention was filed to modify the converter of Zhang et al. to include the features of having the voltage between the first bus and the second bus be greater than the instantaneous maximal alternating current phase voltage, because it provides for a reduction in component variance, which can increase operational efficiencies. Regarding claim 12, Zhang et al. discloses (see fig. 1, 2 and 6) that the fourth connecting node (node connected to 336) is operatively coupled to a fourth bus comprising an alternating current phase (336). Zhang et al. discloses the claimed invention except for the voltage between the first bus and the second bus being less than the instantaneous maximal alternating current phase voltage. It would have been obvious to one having ordinary skill in the art at the time the invention was filed to have the voltage between the first bus and the second bus be less than the instantaneous maximal alternating current phase voltage, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F2.d 272, 205 USPQ 215 (CCPA 1980). Therefore it would have been obvious to one having ordinary skill in the art at the time the invention was filed to modify the converter of Zhang et al. to include the features of having the voltage between the first bus and the second bus be less than the instantaneous maximal alternating current phase voltage, because it provides for a reduction in component variance, which can increase operational efficiencies. Regarding claim 13, Zhang et al. discloses the claimed invention except for the power factor of the power converter is between 0.87 and 1. It would have been obvious to one having ordinary skill in the art at the time the invention was filed to have the power factor of the power converter be between 0.87 and 1, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. Therefore it would have been obvious to one having ordinary skill in the art at the time the invention was filed to modify the converter of Zhang et al. to include the features of having the power factor of the power converter be between 0.87 and 1, because it provides for a reduction in component variance, which can increase operational efficiencies. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: Garces et al. (US 2015/0036398) discloses a multi-level converter system. Dong et al. (US Patent 9667167) discloses systems and methods for a multi-level power converter. Zhuang et al. (US Patent 11424694) discloses a method for controlling a shutdown wave blocking of a multi-level inverter. Any inquiry concerning this communication or earlier communications from the examiner should be directed to JEFFREY A GBLENDE whose telephone number is (571)270-5472. The examiner can normally be reached M-F 9am-5pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Monica Lewis can be reached at 571-272-1838. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /JEFFREY A GBLENDE/Primary Examiner, Art Unit 2838
Read full office action

Prosecution Timeline

Feb 10, 2023
Application Filed
Dec 06, 2025
Non-Final Rejection — §102, §103 (current)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
85%
Grant Probability
94%
With Interview (+8.9%)
2y 5m
Median Time to Grant
Low
PTA Risk
Based on 796 resolved cases by this examiner. Grant probability derived from career allow rate.

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