Prosecution Insights
Last updated: April 19, 2026
Application No. 18/167,908

MULTILAYER DIELECTRIC SUBSTRATE AND METHOD FOR MANUFACTURING MULTILAYER DIELECTRIC SUBSTRATE

Non-Final OA §103
Filed
Feb 13, 2023
Examiner
SAWYER, STEVEN T
Art Unit
2847
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Murata Manufacturing Co. Ltd.
OA Round
1 (Non-Final)
72%
Grant Probability
Favorable
1-2
OA Rounds
2y 6m
To Grant
99%
With Interview

Examiner Intelligence

Grants 72% — above average
72%
Career Allow Rate
733 granted / 1017 resolved
+4.1% vs TC avg
Strong +31% interview lift
Without
With
+30.9%
Interview Lift
resolved cases with interview
Typical timeline
2y 6m
Avg Prosecution
42 currently pending
Career history
1059
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
60.4%
+20.4% vs TC avg
§102
26.9%
-13.1% vs TC avg
§112
10.6%
-29.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1017 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election without traverse of Invention II and Species 1 (figs. 1-4) directed to claims 3, 7-9, 13, 15, 16 and 19 in the reply filed on 12/03/2025 is acknowledged. The election of Species 1 directed to figures 1-4 shows the first recess (15) being only present in the first dielectric substate and not present at all in the second dielectric substrate. Applicants’ election acknowledges the withdraw of claim 4 which is directed to Species 2 (figs. 5 & 11-12) and specifically claims “the second dielectric substrate is provided with a second recess” which is only shown in Species 2. Claims 7-9, 13, 15, 16 and 19 are all dependent off of claim 4 which has been withdrawn from consideration. Therefore the Examiner shall treat claims 7-9, 13, 15, 16 and 19 as being considered to be dependent off of claim 1 and will examine the elected claims, however amendments to the dependence of these claims are required in order to be given further consideration in future Office Actions. Additionally claim 3 states, “a plurality of first electrodes are disposed, and a first recess positioned to at least partially overlap the plurality of first electrodes in a lamination direction”. The elected Species 1-4 does not include “a plurality of first electrodes”. Figs. 1-4 show a single first electrode 120 that overlaps the recess 15. This feature is shown in non-elected species (see figs. 20 and 21) and should be considered when amending the claims. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 3, 7-9, 13, 15 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ndip et al. (US PG. Pub. 2019/0252772) in view of Baks et al. (US PG. Pub. 2016/0049723). Regarding claim 3 – Ndip teaches a multilayer dielectric substrate (figs. 2a & 3e, 20**** [title] Ndip states, “module unit having integrated antennas”), comprising: a first dielectric substrate (upper substrate, see annotated figure 3e) having a multilayer structure (see multiple layers 24a****, 25****, 28****) in which a plurality of first electrodes (28**** [paragraph 0065] Ndip states, “antenna structures 28****”) are disposed, and a first recess (24k**** [paragraph 0065] Ndip states, “cavity 24k****”) positioned to at least partially overlap the plurality of first electrodes (28****) in a lamination direction (vertical direction); a second dielectric substrate (lower substrate, see annotated figure 3e below) having a multilayer structure (see multilayer structure of lower substrate in figure 3e) in which a second electrode (fig. 2a, 22u’ [paragraph 0050] Ndip states, “redistribution plane 22u’ ”) is disposed; and a bonding material (22ug’) that bonds the first dielectric substrate and the second dielectric substrate (claimed structure shown in figures 2a & 3e) in a state where the first recess (24k****) is present between the plurality of first electrodes (28****) and the second electrode (24u’) so as to constitute at least a portion of a radio frequency circuit (claimed structure will perform this function) in which a first cavity (see cavity in recess 24k****) that includes the first recess (24k****) is formed between the plurality of first electrodes (28****) and the second electrode (24u’). Ndip does not specifically teach wherein the bonding material is different from a material comprising the first dielectric substrate and the second dielectric substrate. Baks teaches wherein the bonding material (fig. 1A, 123 [paragraph 0023] Baks states, “solder balls 123”) is different from a material comprising the first dielectric substrate (121 [paragraph 0030] Baks states, “the planar lid 121 can be fabricated from a first substrate having a metallization layer on one or both sides. The first substrate can be, for example, an organic buildup substrate, a printed circuit board laminate, a ceramic substrate”) and the second dielectric substrate (110 [paragraph 0034] Baks states, “the package carrier 110 comprises an multilayer organic carrier”). It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the multilayer dielectric substrate having a first dielectric substrate with a first electrode and a recess and a second dielectric substrate with a second electrode spaced from the first electrode by the recess and the first and second dielectric substrates being joined by a bonding material as taught by Ndip with the bonding material being different than that of the first and second dielectric substrate materials as taught by Baks because Baks states, “In this bonding process, self-alignment of the solder balls 123 of the package cover 120 to the bonding pads 113 on the package carrier 110 ensures alignment of the patch antenna elements 124-1, 124-2, 124-3, and 124-4 with the respective slots/apertures 112-1, 112-2, 112-3, and 112-4 of the ground plane 112” [paragraph 0032]. The solder ball bonding material will help ensure correct alignment of the first and second dielectric substrates. PNG media_image1.png 693 1136 media_image1.png Greyscale Regarding claim 7 – Ndip in view of Baks teach the multilayer dielectric substrate according to Claim 1/4, wherein at least one of the plurality of first electrodes or the second electrode (Ndip; fig. 2a, 22u’ [paragraph 0050 & 0047] Ndip states, “redistribution plane 22u’…The redistribution plane is not restricted to only one sheet, but may also be implemented with several sheets, in order to realize a ground line or a shielding”)) is a ground electrode, and another (28****) is a radiation electrode ([paragraph 0063] Ndip states, “antenna element 28****”) or a filter electrode. Regarding claim 8 – Ndip in view of Baks teach the multilayer dielectric substrate according to Claim 1/4, wherein at least one of the plurality of first electrodes (Ndip; fig. 2a & 3e, 28****) is a radiation electrode ([paragraph 0063] Ndip states, “antenna element 28****”) formed in a substantially rectangular shape (figure 3e shows the cross-sectional view wherein the radiation electrode 28**** being rectangular), a feed point (fig. 3a, see via connected to first electrode 28****) of the radiation electrode is disposed at a position offset from a center of the radiation electrode (28****) in a plan view of the first dielectric substrate (upper substrate shown in annotated figure 3e above), and the first recess (24k****) is formed along a side orthogonal to a polarization direction of a radio wave (see vertical wave shown in figure 3e) radiated from the radiation electrode (28****) and at a position overlapping an end portion of the radiation electrode (28****) in the plan view of the first dielectric substrate (upper substrate shown in annotated figure 3e above). Please note that the claims are directed to apparatus which must be distinguished from the prior art in term of structure rather function [MPEP 2144]. Hence, the functional limitations “the first recess is formed along a side orthogonal to a polarization direction of a radio wave radiated from the radiation electrode and at a position overlapping an end portion of the radiation electrode in the plan view of the first dielectric substrate“ which are narrative in form have not been given significant patentable weight. In order to be given patentable weight, a functional recitation must be supported by recitation in the claim of sufficient structure to warrant the presence of the functional language. In re Schreiber, 128 F.3d 1473, 1477-78, 44 USPQ2d 1429, 1431-32 (Fed. Cir. 1997) Regarding claim 9 – Ndip in view of Baks teach the multilayer dielectric substrate according to Claim 1/4, wherein the bonding material (Baks; fig. 1A, 123) comprises an electrically conductive material ([paragraph 0023] Baks states, “solder balls 123”). Regarding claim 13 – Ndip in view of Baks teach the multilayer dielectric substrate according to Claim 1/4, wherein the first cavity (Ndip; fig. 2a & 3e, 24K****) is a closed space (figure 3e shows a “closed space” in the cross sectional view) in the multilayer dielectric substrate (20****). Regarding claim 15 – Ndip in view of Baks teach the multilayer dielectric substrate according to Claim 1/4, wherein part of the bonding material (Baks; fig. 1A, 123) located on the bonding surface between the first dielectric substrate (120) and the second dielectric substrate (110) is exposed on a side of the first recess (160; figure 1A shows the bonding material 123 being adjacent and exposed to the first recess 160). Regarding claim 19 – Ndip in view of Baks teach the multilayer dielectric substrate according to Claim 1/4, wherein at least one of the plurality of first electrodes (Ndip; fig. 3e, 28****) is a radiation electrode ([paragraph 0063] Ndip states, “antenna element 28****”), and a feed point of the radiation electrode (28****) is connected to a feeder (see connection to via that extends through the first dielectric substrate) inside a via formed in a lamination direction of the multilayer dielectric substrate (claimed structure shown in figure 2a and 3e). Claim(s) 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ndip et al. in view of Baks et al. as applied to claim 1/4 above, and further in view of Liu et al. (US PG. Pub. 2020/0161766). Regarding claim 16 – Ndip in view of Baks teach the multilayer dielectric substrate according to Claim 1/4, further comprising: a via filled with a member having conductivity that sandwiches the bonding material located on the bonding surface between the first dielectric substrate and the second dielectric substrate from a first dielectric substrate side and a second dielectric substrate side. Liu teaches a multilayer dielectric substrate (fig. 1 [title] Liu states, “antenna-in-package structure and terminal”) further comprising: a via (17 [paragraph 0056] Liu states, “ground hole 17”) filled with a member having conductivity that sandwiches the bonding material (19 [paragraph 0064] Liu states, “The connector 19 may be a colloid structure, a solder ball”) located on the bonding surface between the first dielectric substrate (12) and the second dielectric substrate (14) from a first dielectric substrate side and a second dielectric substrate side (claimed structure shown in figure 1). It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the multilayer dielectric substrate as taught by Ndip in view of Baks with the conductive via sandwiching the bonding material through the first and second dielectric substrates as taught by Liu because Liu states, “the ground hole 17 is configured to provide overall signal circulation and heat dissipation for the antenna-in-package structure 10” [paragraph 0056]. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Chang (US Patent 11637381) discloses an antenna in package structure. Bulumulla et al. (US Patent 11075453) discloses a stacked antenna elements. Yu et al. (US Patent 10840578) discloses an antenna array module and manufacturing method thereof. Hayashi et al. (US PG. Pub. 2019/0363432) discloses a planar antenna. Kam et al. (US Patent 9172132) discloses an integrated antenna for RFIC package applications. Chen et al. (US PG. Pub. 2010/0327068) discloses a compact millimeter wave packages with integrated antennas. Akkermans et al. (US Patent 7728774) discloses radio frequency integrated circuit packages. Maruhashi et al. (US Patent 6903700) discloses high frequency circuit structure. Any inquiry concerning this communication or earlier communications from the examiner should be directed to STEVEN T SAWYER whose telephone number is (571)270-5469. The examiner can normally be reached M-F 8:30 am - 5pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy Thompson can be reached at 5712722342. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /STEVEN T SAWYER/Primary Examiner, Art Unit 2847
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Prosecution Timeline

Feb 13, 2023
Application Filed
Dec 18, 2025
Non-Final Rejection — §103
Mar 27, 2026
Response Filed

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
72%
Grant Probability
99%
With Interview (+30.9%)
2y 6m
Median Time to Grant
Low
PTA Risk
Based on 1017 resolved cases by this examiner. Grant probability derived from career allow rate.

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