DETAILED ACTION
This action is in response to amendments filed 1/7/2026. Claims 1-30 are pending with claims 1, 4, 11, 1-14, 18 and 20-21 having been amended.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 1/07/2026 have been fully
Applicant’s arguments with respect to the rejection(s) of claim(s) 1, 11 and 21 under 103 that Samsung Electronics Co. (GB 2468419) in view of Kang et al (US 2014/0153725) in view of Ning (US 2018/0005706) does not teach “inverting at least a portion of the cryptographic input based on the one or more randomly generated bits of the second mask to generate an inverted cryptographic input” have been fully considered and are not persuasive.
Ning (US 2018/0005706) teaches “inverting at least a portion of the cryptographic input based on the one or more randomly generated bits of the second mask to generate an inverted cryptographic input” in paragraph 0197 i.e. Next, an array of Exclusive OR gates 1235 selectively inverts the input data 1215 dependent on the state of flag bit 1245. The array of Exclusive OR gates 1235 then provides either the input data 1215 (if flag bit 1245 is not activated) or an inverted version of the input data 1215 (if flag bit 1245 is activated)).
While Applicant’s argus Ning does not teach inverting cryptographic input because Ning’s disclosure relates to “error correction methods for arrays of resistive change elements”. Ning is only brought to teaches inverting at least a portion of the cryptographic input (Samsung’s “data”) based on the one or more randomly generated bits of the second mask to generate an inverted input. Since Samsung Electronics Co. already teaches cryptographic input is just data since it is never used for any cryptographic function.
While Ning uses a flag bit this does not teaches away from the claim language of “inverting at least a portion of the cryptographic input based on the one or more randomly generated bits of the second mask to generate an inverted cryptographic input” it just shows that the cryptographic input can also not be inverted based on the flag.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-9, 11-19 and 21-30 are rejected under 35 U.S.C. 103 as being unpatentable over Samsung Electronics Co. (GB 2468419) in view of Kang et al (US 2014/0153725) in view of Ning (US 2018/0005706).
With respect to claim 1 Samsung teaches a method for security processing, the method comprising:
obtaining a cryptographic input (see figure 7 and page 13, line 30 to page 14, line 11 i.e. The XOR logic circuit 431 performs a mask operation on the data using a first pattern MASK1 (MI) and stores the output in a register 432. Similarly, the XOR logic circuit 441 performs a mask operation on the data using a second pattern MASK2 (M2) and stores the output in a register 442. Although an exclusive OR logic operation is illustrated as the mask operations of blocks 431 and 441 in FIG. 7, it will be understood that the mask operation may comprise an exclusive OR operation, an addition operation, a - subtraction operation, a multiplication operation, and/or a division operation, in which the addition, subtraction, multiplication, and division operations are performed with respect to a modulus, in accordance with various embodiments of the present invention);
obtaining a first mask and a second mask (see figure 7 and page 13, line 30 to page 14, line 11 i.e. The XOR logic circuit 431 performs a mask operation on the data using a first pattern MASK1 (MI) and stores the output in a register 432. Similarly, the XOR logic circuit 441 performs a mask operation on the data using a second pattern MASK2 (M2) and stores the output in a register 442. Although an exclusive OR logic operation is illustrated as the mask operations of blocks 431 and 441 in FIG. 7, it will be understood that the mask operation may comprise an exclusive OR operation, an addition operation, a - subtraction operation, a multiplication operation, and/or a division operation, in which the addition, subtraction, multiplication, and division operations are performed with respect to a modulus, in accordance with various embodiments of the present invention);
executing a first logic circuit using the first mask and the cryptographic input to obtain a first output (see figure 7 and page 13, line 30 to page 14, line 11 i.e. The XOR logic circuit 431 performs a mask operation on the data using a first pattern MASK1 (MI) and stores the output in a register 432. Similarly, the XOR logic circuit 441 performs a mask operation on the data using a second pattern MASK2 (M2) and stores the output in a register 442. Although an exclusive OR logic operation is illustrated as the mask operations of blocks 431 and 441 in FIG. 7, it will be understood that the mask operation may comprise an exclusive OR operation, an addition operation, a - subtraction operation, a multiplication operation, and/or a division operation, in which the addition, subtraction, multiplication, and division operations are performed with respect to a modulus, in accordance with various embodiments of the present invention);
executing a second logic circuit using the second mask and the cryptographic input to obtain a second output (see figure 7 and page 13, line 30 to page 14, line 11 i.e. The XOR logic circuit 431 performs a mask operation on the data using a first pattern MASK1 (MI) and stores the output in a register 432. Similarly, the XOR logic circuit 441 performs a mask operation on the data using a second pattern MASK2 (M2) and stores the output in a register 442. Although an exclusive OR logic operation is illustrated as the mask operations of blocks 431 and 441 in FIG. 7, it will be understood that the mask operation may comprise an exclusive OR operation, an addition operation, a - subtraction operation, a multiplication operation, and/or a division operation, in which the addition, subtraction, multiplication, and division operations are performed with respect to a modulus, in accordance with various embodiments of the present invention); and
performing a comparison of the first output and the second output to determine whether the comparison is a successful comparison (see figure 7 and page 14, lines 12 to 26; i.e. The XOR logic circuit 454 performs a mask operation on the contents of the register 452 using the contents of register 451. The output of the XOR logic circuit 454 is given by the following equation: input data XOR MI XOR input data XOR M2 = MI XOR M2. An error detector circuit 455 can compare the output of the XOR logic circuit 454 with the known result of MI XOR M2. If the output of the XOR logic circuit 454 is not MI XOR M2, then the input data on at least one branch of the dual data bus has been corrupted and an error is recognized).
While Samsung teaches the cryptograph input is XOR with the first mask and the cryptograph input is XOR with the second mask. Samsung does not explicitly teach the second mask comprising a random mask of one or more randomly generated bits; and inverting at least a portion of the cryptographic input based on the one or more randomly generated bits of the second mask to generate an inverted cryptographic input.
Kank teaches the second mask comprising a random mask of one or more randomly generated bits (see Kank paragraph 0040 i.e. The mask value generation unit 120 transmits the generated mask value M to the mask value application unit 130. The mask value M is a value that has a length of 32 bits that are randomly generated).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Samsung Electronics in view of Kank to have used Kank’s mask value generation unit to randomly generated mask bits (see Kank paragraph 0040).
Ning teaches inverting at least a portion of the cryptographic input (Samsung’s “data”) based on the one or more randomly generated bits of the second mask to generate an inverted cryptographic input (see Ning paragraph 0197 i.e. Next, an array of Exclusive OR gates 1235 selectively inverts the input data 1215 dependent on the state of flag bit 1245. The array of Exclusive OR gates 1235 then provides either the input data 1215 (if flag bit 1245 is not activated) or an inverted version of the input data 1215 (if flag bit 1245 is activated)).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Samsung Electronics in view of Lewis to have used the Exclusive OR gate of Samsung Electronics to have selectively invert the input data based on the masked data as one of many ways to selectively invert the input data base on the first or second mask as an Exclusive OR gate selectively inverts the input data based a control input bit (see Ning paragraph 0197 and 0262).
With respect to claim 2 Samsung, Kang and Ning teach the method of claim 1, wherein the first logic circuit and the second logic circuit are separate instances of a same circuit, wherein the same circuit has same side channel characteristics when executed (see figure 7 and page 13, line 30 to page 14, line 11 i.e. FIG. 7 is a block diagram that illustrates an error detection circuit in accordance with some embodiments of the present invention. Referring to FIG. 7, the error detection circuit includes a CPU 410, three logic circuits 430, 440, and 450, and a memory 420 that are configured as shown. The data bus coupled to the CPU 410 is connected in parallel to the logic circuits 430 and 440. The XOR logic circuit 431 performs a mask operation on the data using a first pattern MASK1 (MI) and stores the output in a register 432. Similarly, the XOR logic circuit 441 performs a mask operation on the data using a second pattern MASK2 (M2) and stores the output in a register 442. Although an exclusive OR logic operation is illustrated as the mask operations of blocks 431 and 441 in FIG. 7, it will be understood that the mask operation may comprise an exclusive OR operation, an addition operation, a - subtraction operation, a multiplication operation, and/or a division operation, in which the addition, subtraction, multiplication, and division operations are performed with respect to a modulus, in accordance with various embodiments of the present invention).
With respect to claim 3 Samsung, Kang and Ning teach the method of claim 1, wherein the first mask is a single bit mask, and wherein obtaining the second mask comprises inverting the first mask to obtain an inverted second mask (see page 14 lines 20-26 i.e. The XOR logic circuit 454 performs a mask operation on the contents of the register 452 using the contents of register 451. The output of the XOR logic circuit 454 is given by the following equation: input data XOR MI XOR input data KOR M2 = MI XOR M2. Anerror detector circuit 455 can compare the output of the XOR logic circuit 454 with the known result of MI XOR M2. If the output of the XOR logic circuit 454 is not MI XOR M2, then the input data on at least one branch of the dual data bus has been corrupted and an error is recognized).
With respect to claim 4 Samsung, Kang and Ning teach the method of claim 3, wherein executing the first logic circuit includes using standard logic based on the first mask to obtain the first output; and wherein executing the second logic circuit includes using inverted logic based on the inverted second mask to obtain the second output, wherein the second logic circuit inverts the cryptographic input and the second output to obtain an inverted second output (see figure 7 and page 13, line 30 to page 14, line 11 i.e. The XOR logic circuit 431 performs a mask operation on the data using a first pattern MASK1 (MI) and stores the output in a register 432. Similarly, the XOR logic circuit 441 performs a mask operation on the data using a second pattern MASK2 (M2) and stores the output in a register 442. Although an exclusive OR logic operation is illustrated as the mask operations of blocks 431 and 441 in FIG. 7, it will be understood that the mask operation may comprise an exclusive OR operation, an addition operation, a - subtraction operation, a multiplication operation, and/or a division operation, in which the addition, subtraction, multiplication, and division operations are performed with respect to a modulus, in accordance with various embodiments of the present invention).
With respect to claim 5 Samsung, Kang and Ning teach the method of claim 4, wherein determining the comparison is the successful comparison includes determining that the inverted second output is an inverted instance of the first output (see page 14 lines 20-26 i.e. The XOR logic circuit 454 performs a mask operation on the contents of the register 452 using the contents of register 451. The output of the XOR logic circuit 454 is given by the following equation: input data XOR MI XOR input data KOR M2 = MI XOR M2. Anerror detector circuit 455 can compare the output of the XOR logic circuit 454 with the known result of MI XOR M2. If the output of the XOR logic circuit 454 is not MI XOR M2, then the input data on at least one branch of the dual data bus has been corrupted and an error is recognized).
With respect to claim 6 Samsung, Kang and Ning teach the method of claim 1, wherein the cryptographic input is a cryptographic key (see page 16 lines 14-17 i.e. where D is the input data, M1 is the first pattern, A is the at least a portion of the address (addrl), K is the key (keyl), Pp" is an inverse of the permutation performed by the permutation circuit 616).
With respect to claim 7 Samsung, Kang and Ning teach the method of claim 1, wherein a first value of the first mask is a first randomly generated multi-bit mask and a second value of the second mask is a second randomly generated multi-bit mask (see figure 7 and page 13, line 30 to page 14, line 11 i.e. The XOR logic circuit 431 performs a mask operation on the data using a first pattern MASK1 (MI) and stores the output in a register 432. Similarly, the XOR logic circuit 441 performs a mask operation on the data using a second pattern MASK2 (M2) and stores the output in a register 442. Although an exclusive OR logic operation is illustrated as the mask operations of blocks 431 and 441 in FIG. 7, it will be understood that the mask operation may comprise an exclusive OR operation, an addition operation, a - subtraction operation, a multiplication operation, and/or a division operation, in which the addition, subtraction, multiplication, and division operations are performed with respect to a modulus, in accordance with various embodiments of the present invention).
With respect to claim 8 Samsung, Kang and Ning teach the method of claim 7, wherein performing the comparison to determine whether the comparison is the successful comparison includes reapplying the first mask to the first output and the second mask to the second output, and making a determination of whether the first output matches the second output (see figure 7 and page 14, lines 12 to 26; i.e. The XOR logic circuit 454 performs a mask operation on the contents of the register 452 using the contents of register 451. The output of the XOR logic circuit 454 is given by the following equation: input data XOR MI XOR input data XOR M2 = MI XOR M2. An error detector circuit 455 can compare the output of the XOR logic circuit 454 with the known result of MI XOR M2. If the output of the XOR logic circuit 454 is not MI XOR M2, then the input data on at least one branch of the dual data bus has been corrupted and an error is recognized).
With respect to claim 9 Samsung, Kang and Ning teach the method of claim 7, wherein a first quantity of bits in the first mask matches a second quantity of bits in the cryptographic input and the first output, and also matches the second quantity of bits in the cryptographic input and the second output (see figure 7 and page 14, lines 12 to 26; i.e. The XOR logic circuit 454 performs a mask operation on the contents of the register 452 using the contents of register 451. The output of the XOR logic circuit 454 is given by the following equation: input data XOR MI XOR input data XOR M2 = MI XOR M2. An error detector circuit 455 can compare the output of the XOR logic circuit 454 with the known result of MI XOR M2. If the output of the XOR logic circuit 454 is not MI XOR M2, then the input data on at least one branch of the dual data bus has been corrupted and an error is recognized).
With respect to claim 11 Samsung teaches an apparatus for security processing, the apparatus comprising: at least one memory; and at least one processor coupled to the at least one memory and configured to: obtaining a cryptographic input (see figure 7 and page 13, line 30 to page 14, line 11 i.e. The XOR logic circuit 431 performs a mask operation on the data using a first pattern MASK1 (MI) and stores the output in a register 432. Similarly, the XOR logic circuit 441 performs a mask operation on the data using a second pattern MASK2 (M2) and stores the output in a register 442. Although an exclusive OR logic operation is illustrated as the mask operations of blocks 431 and 441 in FIG. 7, it will be understood that the mask operation may comprise an exclusive OR operation, an addition operation, a - subtraction operation, a multiplication operation, and/or a division operation, in which the addition, subtraction, multiplication, and division operations are performed with respect to a modulus, in accordance with various embodiments of the present invention);
obtaining a first mask and a second mask (see figure 7 and page 13, line 30 to page 14, line 11 i.e. The XOR logic circuit 431 performs a mask operation on the data using a first pattern MASK1 (MI) and stores the output in a register 432. Similarly, the XOR logic circuit 441 performs a mask operation on the data using a second pattern MASK2 (M2) and stores the output in a register 442. Although an exclusive OR logic operation is illustrated as the mask operations of blocks 431 and 441 in FIG. 7, it will be understood that the mask operation may comprise an exclusive OR operation, an addition operation, a - subtraction operation, a multiplication operation, and/or a division operation, in which the addition, subtraction, multiplication, and division operations are performed with respect to a modulus, in accordance with various embodiments of the present invention);
executing a first logic circuit using the first mask and the cryptographic input to obtain a first output (see figure 7 and page 13, line 30 to page 14, line 11 i.e. The XOR logic circuit 431 performs a mask operation on the data using a first pattern MASK1 (MI) and stores the output in a register 432. Similarly, the XOR logic circuit 441 performs a mask operation on the data using a second pattern MASK2 (M2) and stores the output in a register 442. Although an exclusive OR logic operation is illustrated as the mask operations of blocks 431 and 441 in FIG. 7, it will be understood that the mask operation may comprise an exclusive OR operation, an addition operation, a - subtraction operation, a multiplication operation, and/or a division operation, in which the addition, subtraction, multiplication, and division operations are performed with respect to a modulus, in accordance with various embodiments of the present invention);
executing a second logic circuit using the second mask and the cryptographic input to obtain a second output (see figure 7 and page 13, line 30 to page 14, line 11 i.e. The XOR logic circuit 431 performs a mask operation on the data using a first pattern MASK1 (MI) and stores the output in a register 432. Similarly, the XOR logic circuit 441 performs a mask operation on the data using a second pattern MASK2 (M2) and stores the output in a register 442. Although an exclusive OR logic operation is illustrated as the mask operations of blocks 431 and 441 in FIG. 7, it will be understood that the mask operation may comprise an exclusive OR operation, an addition operation, a - subtraction operation, a multiplication operation, and/or a division operation, in which the addition, subtraction, multiplication, and division operations are performed with respect to a modulus, in accordance with various embodiments of the present invention); and
performing a comparison of the first output and the second output to determine whether the comparison is a successful comparison (see figure 7 and page 14, lines 12 to 26; i.e. The XOR logic circuit 454 performs a mask operation on the contents of the register 452 using the contents of register 451. The output of the XOR logic circuit 454 is given by the following equation: input data XOR MI XOR input data XOR M2 = MI XOR M2. An error detector circuit 455 can compare the output of the XOR logic circuit 454 with the known result of MI XOR M2. If the output of the XOR logic circuit 454 is not MI XOR M2, then the input data on at least one branch of the dual data bus has been corrupted and an error is recognized).
While Samsung teaches the cryptograph input is XOR with the first mask and the cryptograph input is XOR with the second mask. Samsung does not explicitly teach the second mask comprising a random mask of one or more randomly generated bits; and inverting at least a portion of the cryptographic input based on the one or more randomly generated bits of the second mask.
Kank teaches the second mask comprising a random mask of one or more randomly generated bits (see Kank paragraph 0040 i.e. The mask value generation unit 120 transmits the generated mask value M to the mask value application unit 130. The mask value M is a value that has a length of 32 bits that are randomly generated).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Samsung Electronics in view of Kank to have used Kank’s mask value generation unit to randomly generated mask bits (see Kank paragraph 0040).
Ning teaches inverting at least a portion of the cryptographic input based on the one or more randomly generated bits of the second mask to generate an inverted cryptographic input (see Ning paragraph 0197 i.e. Next, an array of Exclusive OR gates 1235 selectively inverts the input data 1215 dependent on the state of flag bit 1245. The array of Exclusive OR gates 1235 then provides either the input data 1215 (if flag bit 1245 is not activated) or an inverted version of the input data 1215 (if flag bit 1245 is activated)).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Samsung Electronics in view of Lewis to have used the Exclusive OR gate of Samsung Electronics to have selectively invert the input data based on the masked data as one of many ways to selectively invert the input data base on the first or second mask as an Exclusive OR gate selectively inverts the input data based a control input bit (see Ning paragraph 0197 and 0262).
With respect to claim 12 Samsung, Kang and Ning teach the apparatus of claim 11, wherein the first logic circuit and the second logic circuit are separate instances of a same circuit, wherein the same circuit has same side channel characteristics when executed (see figure 7 and page 13, line 30 to page 14, line 11 i.e. FIG. 7 is a block diagram that illustrates an error detection circuit in accordance with some embodiments of the present invention. Referring to FIG. 7, the error detection circuit includes a CPU 410, three logic circuits 430, 440, and 450, and a memory 420 that are configured as shown. The data bus coupled to the CPU 410 is connected in parallel to the logic circuits 430 and 440. The XOR logic circuit 431 performs a mask operation on the data using a first pattern MASK1 (MI) and stores the output in a register 432. Similarly, the XOR logic circuit 441 performs a mask operation on the data using a second pattern MASK2 (M2) and stores the output in a register 442. Although an exclusive OR logic operation is illustrated as the mask operations of blocks 431 and 441 in FIG. 7, it will be understood that the mask operation may comprise an exclusive OR operation, an addition operation, a - subtraction operation, a multiplication operation, and/or a division operation, in which the addition, subtraction, multiplication, and division operations are performed with respect to a modulus, in accordance with various embodiments of the present invention).
With respect to claim 13 Samsung, Kang and Ning teach the apparatus of claim 11, wherein the first mask is a single bit mask, and wherein to obtain the second mask the at least one processor is configured to invert the first mask to obtain an inverted second mask (see page 14 lines 20-26 i.e. The XOR logic circuit 454 performs a mask operation on the contents of the register 452 using the contents of register 451. The output of the XOR logic circuit 454 is given by the following equation: input data XOR MI XOR input data KOR M2 = MI XOR M2. Anerror detector circuit 455 can compare the output of the XOR logic circuit 454 with the known result of MI XOR M2. If the output of the XOR logic circuit 454 is not MI XOR M2, then the input data on at least one branch of the dual data bus has been corrupted and an error is recognized).
With respect to claim 14 Samsung, Kang and Ning teach the apparatus of claim 13, wherein, to execute the first logic circuit, the at least one processor is configured to use standard logic based on the first mask to obtain the first output; and wherein to execute the second logic circuit the at least one processor is configured to use inverted logic based on the inverted second mask to obtain the second output, wherein the second logic circuit inverts the inverted cryptographic input and the second output to obtain an inverted second output (see figure 7 and page 13, line 30 to page 14, line 11 i.e. The XOR logic circuit 431 performs a mask operation on the data using a first pattern MASK1 (MI) and stores the output in a register 432. Similarly, the XOR logic circuit 441 performs a mask operation on the data using a second pattern MASK2 (M2) and stores the output in a register 442. Although an exclusive OR logic operation is illustrated as the mask operations of blocks 431 and 441 in FIG. 7, it will be understood that the mask operation may comprise an exclusive OR operation, an addition operation, a - subtraction operation, a multiplication operation, and/or a division operation, in which the addition, subtraction, multiplication, and division operations are performed with respect to a modulus, in accordance with various embodiments of the present invention).
With respect to claim 15 Samsung, Kang and Ning teach the apparatus of claim 14, wherein, to perform the comparison to determine whether the comparison is the successful comparison, the at least one processor is configured to determine that the inverted second output is an inverted instance of the first output (see page 14 lines 20-26 i.e. The XOR logic circuit 454 performs a mask operation on the contents of the register 452 using the contents of register 451. The output of the XOR logic circuit 454 is given by the following equation: input data XOR MI XOR input data KOR M2 = MI XOR M2. Anerror detector circuit 455 can compare the output of the XOR logic circuit 454 with the known result of MI XOR M2. If the output of the XOR logic circuit 454 is not MI XOR M2, then the input data on at least one branch of the dual data bus has been corrupted and an error is recognized).
With respect to claim 16 Samsung, Kang and Ning teach the apparatus of claim 11, wherein the cryptographic input is a cryptographic key (see page 16 lines 14-17 i.e. where D is the input data, M1 is the first pattern, A is the at least a portion of the address (addrl), K is the key (keyl), Pp" is an inverse of the permutation performed by the permutation circuit 616).
With respect to claim 17 Samsung, Kang and Ning teach the apparatus of claim 11, wherein a first value of the first mask is a first randomly generated multi-bit mask and a second value of the second mask is a second randomly generated multi-bit mask (see figure 7 and page 13, line 30 to page 14, line 11 i.e. The XOR logic circuit 431 performs a mask operation on the data using a first pattern MASK1 (MI) and stores the output in a register 432. Similarly, the XOR logic circuit 441 performs a mask operation on the data using a second pattern MASK2 (M2) and stores the output in a register 442. Although an exclusive OR logic operation is illustrated as the mask operations of blocks 431 and 441 in FIG. 7, it will be understood that the mask operation may comprise an exclusive OR operation, an addition operation, a - subtraction operation, a multiplication operation, and/or a division operation, in which the addition, subtraction, multiplication, and division operations are performed with respect to a modulus, in accordance with various embodiments of the present invention).
With respect to claim 18 Samsung, Kang and Ning teach the apparatus of claim 17, wherein, to determine that the comparison is the successful comparison, the at least one processor is configured to reapply the first mask to the first output and the second mask to the second output, and make a determination of whether the first output matches the second output (see figure 7 and page 14, lines 12 to 26; i.e. The XOR logic circuit 454 performs a mask operation on the contents of the register 452 using the contents of register 451. The output of the XOR logic circuit 454 is given by the following equation: input data XOR MI XOR input data XOR M2 = MI XOR M2. An error detector circuit 455 can compare the output of the XOR logic circuit 454 with the known result of MI XOR M2. If the output of the XOR logic circuit 454 is not MI XOR M2, then the input data on at least one branch of the dual data bus has been corrupted and an error is recognized).
With respect to claim 19 Samsung, Kang and Ning teach the apparatus of claim 17, wherein a first quantity of bits in the first mask matches a second quantity of bits in the cryptographic input and the first output, and also matches the second quantity of bits in the cryptographic input and the second output (see figure 7 and page 14, lines 12 to 26; i.e. The XOR logic circuit 454 performs a mask operation on the contents of the register 452 using the contents of register 451. The output of the XOR logic circuit 454 is given by the following equation: input data XOR MI XOR input data XOR M2 = MI XOR M2. An error detector circuit 455 can compare the output of the XOR logic circuit 454 with the known result of MI XOR M2. If the output of the XOR logic circuit 454 is not MI XOR M2, then the input data on at least one branch of the dual data bus has been corrupted and an error is recognized).
With respect to claim 21 Samsung teaches a non-transitory computer-readable medium having stored thereon instructions that, when executed by one or more processors, cause the one or more processors to: obtaining a cryptographic input (see figure 7 and page 13, line 30 to page 14, line 11 i.e. The XOR logic circuit 431 performs a mask operation on the data using a first pattern MASK1 (MI) and stores the output in a register 432. Similarly, the XOR logic circuit 441 performs a mask operation on the data using a second pattern MASK2 (M2) and stores the output in a register 442. Although an exclusive OR logic operation is illustrated as the mask operations of blocks 431 and 441 in FIG. 7, it will be understood that the mask operation may comprise an exclusive OR operation, an addition operation, a - subtraction operation, a multiplication operation, and/or a division operation, in which the addition, subtraction, multiplication, and division operations are performed with respect to a modulus, in accordance with various embodiments of the present invention);
obtaining a first mask and a second mask (see figure 7 and page 13, line 30 to page 14, line 11 i.e. The XOR logic circuit 431 performs a mask operation on the data using a first pattern MASK1 (MI) and stores the output in a register 432. Similarly, the XOR logic circuit 441 performs a mask operation on the data using a second pattern MASK2 (M2) and stores the output in a register 442. Although an exclusive OR logic operation is illustrated as the mask operations of blocks 431 and 441 in FIG. 7, it will be understood that the mask operation may comprise an exclusive OR operation, an addition operation, a - subtraction operation, a multiplication operation, and/or a division operation, in which the addition, subtraction, multiplication, and division operations are performed with respect to a modulus, in accordance with various embodiments of the present invention);
executing a first logic circuit using the first mask and the cryptographic input to obtain a first output (see figure 7 and page 13, line 30 to page 14, line 11 i.e. The XOR logic circuit 431 performs a mask operation on the data using a first pattern MASK1 (MI) and stores the output in a register 432. Similarly, the XOR logic circuit 441 performs a mask operation on the data using a second pattern MASK2 (M2) and stores the output in a register 442. Although an exclusive OR logic operation is illustrated as the mask operations of blocks 431 and 441 in FIG. 7, it will be understood that the mask operation may comprise an exclusive OR operation, an addition operation, a - subtraction operation, a multiplication operation, and/or a division operation, in which the addition, subtraction, multiplication, and division operations are performed with respect to a modulus, in accordance with various embodiments of the present invention);
executing a second logic circuit using the second mask and the cryptographic input to obtain a second output (see figure 7 and page 13, line 30 to page 14, line 11 i.e. The XOR logic circuit 431 performs a mask operation on the data using a first pattern MASK1 (MI) and stores the output in a register 432. Similarly, the XOR logic circuit 441 performs a mask operation on the data using a second pattern MASK2 (M2) and stores the output in a register 442. Although an exclusive OR logic operation is illustrated as the mask operations of blocks 431 and 441 in FIG. 7, it will be understood that the mask operation may comprise an exclusive OR operation, an addition operation, a - subtraction operation, a multiplication operation, and/or a division operation, in which the addition, subtraction, multiplication, and division operations are performed with respect to a modulus, in accordance with various embodiments of the present invention); and
performing a comparison of the first output and the second output to determine whether the comparison is a successful comparison (see figure 7 and page 14, lines 12 to 26; i.e. The XOR logic circuit 454 performs a mask operation on the contents of the register 452 using the contents of register 451. The output of the XOR logic circuit 454 is given by the following equation: input data XOR MI XOR input data XOR M2 = MI XOR M2. An error detector circuit 455 can compare the output of the XOR logic circuit 454 with the known result of MI XOR M2. If the output of the XOR logic circuit 454 is not MI XOR M2, then the input data on at least one branch of the dual data bus has been corrupted and an error is recognized).
While Samsung teaches the cryptograph input is XOR with the first mask and the cryptograph input is XOR with the second mask. Samsung does not explicitly teach the second mask comprising a random mask of one or more randomly generated bits; and inverting at least a portion of the cryptographic input based on the one or more randomly generated bits of the second mask.
Kank teaches the second mask comprising a random mask of one or more randomly generated bits (see Kank paragraph 0040 i.e. The mask value generation unit 120 transmits the generated mask value M to the mask value application unit 130. The mask value M is a value that has a length of 32 bits that are randomly generated).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Samsung Electronics in view of Kank to have used Kank’s mask value generation unit to randomly generated mask bits (see Kank paragraph 0040).
Ning teaches inverting at least a portion of the cryptographic input based on the one or more randomly generated bits of the second mask to generate an inverted cryptographic input (see Ning paragraph 0197 i.e. Next, an array of Exclusive OR gates 1235 selectively inverts the input data 1215 dependent on the state of flag bit 1245. The array of Exclusive OR gates 1235 then provides either the input data 1215 (if flag bit 1245 is not activated) or an inverted version of the input data 1215 (if flag bit 1245 is activated)).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Samsung Electronics in view of Lewis to have used the Exclusive OR gate of Samsung Electronics to have selectively invert the input data based on the masked data as one of many ways to selectively invert the input data base on the first or second mask as an Exclusive OR gate selectively inverts the input data based a control input bit (see Ning paragraph 0197 and 0262).
With respect to claim 22 Samsung, Kang and Ning teach the non-transitory computer-readable medium of claim 21, wherein the first logic circuit and the second logic circuit are separate instances of a same circuit, wherein the same circuit has same side channel characteristics when executed (see figure 7 and page 13, line 30 to page 14, line 11 i.e. FIG. 7 is a block diagram that illustrates an error detection circuit in accordance with some embodiments of the present invention. Referring to FIG. 7, the error detection circuit includes a CPU 410, three logic circuits 430, 440, and 450, and a memory 420 that are configured as shown. The data bus coupled to the CPU 410 is connected in parallel to the logic circuits 430 and 440. The XOR logic circuit 431 performs a mask operation on the data using a first pattern MASK1 (MI) and stores the output in a register 432. Similarly, the XOR logic circuit 441 performs a mask operation on the data using a second pattern MASK2 (M2) and stores the output in a register 442. Although an exclusive OR logic operation is illustrated as the mask operations of blocks 431 and 441 in FIG. 7, it will be understood that the mask operation may comprise an exclusive OR operation, an addition operation, a - subtraction operation, a multiplication operation, and/or a division operation, in which the addition, subtraction, multiplication, and division operations are performed with respect to a modulus, in accordance with various embodiments of the present invention).
With respect to claim 23 Samsung, Kang and Ning teach the non-transitory computer-readable medium of claim 21, wherein the first mask is a single bit mask, and wherein obtaining the second mask comprises inverting the first mask to obtain an inverted second mask (see page 14 lines 20-26 i.e. The XOR logic circuit 454 performs a mask operation on the contents of the register 452 using the contents of register 451. The output of the XOR logic circuit 454 is given by the following equation: input data XOR MI XOR input data KOR M2 = MI XOR M2. Anerror detector circuit 455 can compare the output of the XOR logic circuit 454 with the known result of MI XOR M2. If the output of the XOR logic circuit 454 is not MI XOR M2, then the input data on at least one branch of the dual data bus has been corrupted and an error is recognized).
With respect to claim 24 Samsung, Kang and Ning teach the non-transitory computer-readable medium of claim 23, wherein executing the first logic circuit includes using standard logic based on the first mask to obtain the first output; and wherein executing the second logic circuit includes using inverted logic based on the inverted second mask to obtain the second output, wherein the second logic circuit inverts the cryptographic input and the second output to obtain an inverted second output (see figure 7 and page 13, line 30 to page 14, line 11 i.e. The XOR logic circuit 431 performs a mask operation on the data using a first pattern MASK1 (MI) and stores the output in a register 432. Similarly, the XOR logic circuit 441 performs a mask operation on the data using a second pattern MASK2 (M2) and stores the output in a register 442. Although an exclusive OR logic operation is illustrated as the mask operations of blocks 431 and 441 in FIG. 7, it will be understood that the mask operation may comprise an exclusive OR operation, an addition operation, a - subtraction operation, a multiplication operation, and/or a division operation, in which the addition, subtraction, multiplication, and division operations are performed with respect to a modulus, in accordance with various embodiments of the present invention).
With respect to claim 25 Samsung, Kang and Ning teach the non-transitory computer-readable medium of claim 24, wherein the successful comparison includes determining that the inverted second output is an inverted instance of the first output (see page 14 lines 20-26 i.e. The XOR logic circuit 454 performs a mask operation on the contents of the register 452 using the contents of register 451. The output of the XOR logic circuit 454 is given by the following equation: input data XOR MI XOR input data KOR M2 = MI XOR M2. Anerror detector circuit 455 can compare the output of the XOR logic circuit 454 with the known result of MI XOR M2. If the output of the XOR logic circuit 454 is not MI XOR M2, then the input data on at least one branch of the dual data bus has been corrupted and an error is recognized).
With respect to claim 26 Samsung, Kang and Ning teach the non-transitory computer-readable medium of claim 21, wherein the cryptographic input is a cryptographic key (see page 16 lines 14-17 i.e. where D is the input data, M1 is the first pattern, A is the at least a portion of the address (addrl), K is the key (keyl), Pp" is an inverse of the permutation performed by the permutation circuit 616).
With respect to claim 27 Samsung, Kang and Ning teach the non-transitory computer-readable medium of claim 21, wherein a first value of the first mask is a first randomly generated multi-bit mask and a second value of the second mask is a second randomly generated multi-bit mask (see figure 7 and page 13, line 30 to page 14, line 11 i.e. The XOR logic circuit 431 performs a mask operation on the data using a first pattern MASK1 (MI) and stores the output in a register 432. Similarly, the XOR logic circuit 441 performs a mask operation on the data using a second pattern MASK2 (M2) and stores the output in a register 442. Although an exclusive OR logic operation is illustrated as the mask operations of blocks 431 and 441 in FIG. 7, it will be understood that the mask operation may comprise an exclusive OR operation, an addition operation, a - subtraction operation, a multiplication operation, and/or a division operation, in which the addition, subtraction, multiplication, and division operations are performed with respect to a modulus, in accordance with various embodiments of the present invention).
With respect to claim 28 Samsung, Kang and Ning teach the non-transitory computer-readable medium of claim 27, wherein performing the successful comparison includes reapplying the first mask to the first output and the second mask to the second output, and making a determination of whether the first output matches the second output (see figure 7 and page 14, lines 12 to 26; i.e. The XOR logic circuit 454 performs a mask operation on the contents of the register 452 using the contents of register 451. The output of the XOR logic circuit 454 is given by the following equation: input data XOR MI XOR input data XOR M2 = MI XOR M2. An error detector circuit 455 can compare the output of the XOR logic circuit 454 with the known result of MI XOR M2. If the output of the XOR logic circuit 454 is not MI XOR M2, then the input data on at least one branch of the dual data bus has been corrupted and an error is recognized).
With respect to claim 29 Samsung, Kang and Ning teach the non-transitory computer-readable medium of claim 27, wherein a first quantity of bits in the first mask matches a second quantity of bits in the cryptographic input and the first output, and also matches the second quantity of bits in the cryptographic input and the second output (see figure 7 and page 14, lines 12 to 26; i.e. The XOR logic circuit 454 performs a mask operation on the contents of the register 452 using the contents of register 451. The output of the XOR logic circuit 454 is given by the following equation: input data XOR MI XOR input data XOR M2 = MI XOR M2. An error detector circuit 455 can compare the output of the XOR logic circuit 454 with the known result of MI XOR M2. If the output of the XOR logic circuit 454 is not MI XOR M2, then the input data on at least one branch of the dual data bus has been corrupted and an error is recognized).
Claims 10, 20 and 30 are rejected under 35 U.S.C. 103 as being unpatentable over Samsung Electronics Co. (GB 2468419) in view of Kang et al (US 2014/0153725) in view of Ning (US 2018/0005706) in view of Tehranipoor et al (US 2022/0180003).
With respect to claim 10 Samsung, Kang and Ning teach the method of claim 1, further comprising: making a determination that the comparison is not successful (see Samsung figure 7 and page 14, lines 12 to 26; i.e. The XOR logic circuit 454 performs a mask operation on the contents of the register 452 using the contents of register 451. The output of the XOR logic circuit 454 is given by the following equation: input data XOR MI XOR input data XOR M2 = MI XOR M2. An error detector circuit 455 can compare the output of the XOR logic circuit 454 with the known result of MI XOR M2. If the output of the XOR logic circuit 454 is not MI XOR M2, then the input data on at least one branch of the dual data bus has been corrupted and an error is recognized).
Samsung does not teach performing, based on the determination, a randomization of the first output and the second output.
Tehranipoor teaches performing, based on the determination, a randomization of the first output and the second output (see Tehranipoor paragraph 0008).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Samsung in view of Tehranipoor to have output a random value in response to a random fault which will not help may not help with the attack by guaranteeing that there is no security property violated (see Tehranipoor paragraph 0008). Therefore one would have been motivated to have output a random value in response to a fault.
With respect to claim 20 Samsung, Kang and Ning teach teaches the apparatus of claim 11, wherein the at least one processor is configured to: make a determination that the comparison is not successful (see Samsung figure 7 and page 14, lines 12 to 26; i.e. The XOR logic circuit 454 performs a mask operation on the contents of the register 452 using the contents of register 451. The output of the XOR logic circuit 454 is given by the following equation: input data XOR MI XOR input data XOR M2 = MI XOR M2. An error detector circuit 455 can compare the output of the XOR logic circuit 454 with the known result of MI XOR M2. If the output of the XOR logic circuit 454 is not MI XOR M2, then the input data on at least one branch of the dual data bus has been corrupted and an error is recognized)
Samsung and Ning does not teach perform, based on the determination, a randomization of the first output and the second output.
Tehranipoor teaches perform, based on the determination, a randomization of the first output and the second output (see Tehranipoor paragraph 0008).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Samsung in view of Tehranipoor to have output a random value in response to a random fault which will not help may not help with the attack by guaranteeing that there is no security property violated (see Tehranipoor paragraph 0008). Therefore one would have been motivated to have output a random value in response to a fault.
With respect to claim 30 Samsung, Kang and Ning teach teaches the non-transitory computer-readable medium of claim 27, having further instructions stored thereon that, when executed by the one or more processors, cause the one or more processors to: make a determination that the comparison is not successful (see Samsung figure 7 and page 14, lines 12 to 26; i.e. The XOR logic circuit 454 performs a mask operation on the contents of the register 452 using the contents of register 451. The output of the XOR logic circuit 454 is given by the following equation: input data XOR MI XOR input data XOR M2 = MI XOR M2. An error detector circuit 455 can compare the output of the XOR logic circuit 454 with the known result of MI XOR M2. If the output of the XOR logic circuit 454 is not MI XOR M2, then the input data on at least one branch of the dual data bus has been corrupted and an error is recognized).
Samsung and Ning does not teach performing, based on the determination, a randomization of the first output and the second output.
Tehranipoor teaches performing, based on the determination, a randomization of the first output and the second output (see Tehranipoor paragraph 0008).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Samsung in view of Tehranipoor to have output a random value in response to a random fault which will not help may not help with the attack by guaranteeing that there is no security property violated (see Tehranipoor paragraph 0008). Therefore one would have been motivated to have output a random value in response to a fault.
Prior Art
Trichina (US 2008/0260145) titled “Selection Of A Lookup Table With Data Masked With A Combination Of An Additive And Multiplicative Mask”.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DEVIN E ALMEIDA whose telephone number is (571)270-1018. The examiner can normally be reached on Monday-Thursday from 7:30 A.M. to 5:00 P.M. The examiner can also be reached on alternate Fridays from 7:30 A.M. to 4:00 P.M.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Rupal Dharia, can be reached on 571-272-3880. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DEVIN E ALMEIDA/Examiner, Art Unit 2492
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