Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Objections
The applicant’s amendments have overcome the previous objections which is/are consequently withdrawn.
Rejections Under 35 U.S.C. §112
Applicant’s arguments have been fully considered and are persuasive. Accordingly, the previous rejections have been withdrawn. However, the applicant’s amendments have introduced new 35 U.S.C. §112(b) issues (as indicated below).
Rejections Under 35 U.S.C. §101
Applicant's arguments have been fully considered but they are not persuasive.
… the claim recites "a parameter specifying a temporal relationship ... wherein the temporal relationship indicates a search direction in which the system starts a search for the adjacent node," with the search direction limited to forward, backward, or sametime. That is not an abstraction. It is a stored parameter value within the debug tree that directly constrains the system's operation, i.e., how and where the program starts each adjacent-node search across electronically stored error data. …
The claimed “nodes of a debug tree” describe a way to conceptualize a set of “events” (e.g. with a temporal relationship). Such conceptualization merely requires observing and evaluating the event data and can thus be performed in the human mind. Any additional elements merely describe, at a high level of generalization, how to represent that conceptualization in a computer (e.g. “storing values for … parameters for a plurality of nodes …”).
… The claim further requires accessing one or more data sources using particular values for parameters associated with each node, returning information for each node, and determining, for each node, whether the error matches the node's events. Taken together, these recited elements integrate any high-level concepts into a practical application that improves computer-implemented verification by imposing a direction controlled, parameterized search procedure rather than generic data evaluation. …
The claimed determining “whether the error matches the note’s events” describes performing an abstract judgment (e.g. do the events/error have the identified temporal relationship(s)). Any additional elements merely describe, at a high level of generalization, communication and/or data retrieval within a computing environment (e.g. “accessing … data sources … returning … information”).
Accordingly, the claim is directed to an abstract mental process of defining a set of events (e.g. “nodes of a debug tree”), and determining if the identified set of events matches another set of events (“determining [if] the first error matches”). The additional elements, amount to no more than “generally linking the use of a judicial exception to a particular technological environment or field of use” (MPEP 2106.05(h); also see e.g. Bilski, 561 U.S. at 595, 95 USPQ2d at 1010; FairWarning v. Iatric Sys., 839 F.3d 1089, 1094-95, 120 USPQ2d 1293, 1295 (Fed. Cir. 2016))
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-4, 6-14, 16-18 and 20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites:
“… wherein the temporal relationship indicates a search direction in which the system starts a search for the adjacent node …”
The remainder of the claim does not otherwise recite a “search”. Accordingly, at least in this context, it is not clear what is being searched or what it means to “start” a search in the specified “direction”.
“… the data sources comprising information describing errors generated by the system being verified corresponding to the events for the plurality of nodes …”
This language makes it unclear if the information “information describing errors corresponding to the events for the plurality of nodes” refers to, e.g., the nodes of the previously claimed debug tree or events corresponding to the received “first error”.
… determining, for each node, whether or not the first error matches events corresponding to the plurality of nodes.
This language does not particularly and distinctly indicate what it means for a “first error” to match an “events”. Note for example the claim does not indicate the “first error” comprises events or nodes and only recites a “direction” in which to “start” the “search” and no what constitutes a “match”.
Claims 13 and 17 recite languages similar to that of claim 1 and are similarly rejected.
Claims 2-3, 5-12, 14, 16-18 and 20 depend from one of independent claims 1, 13 or 17 and are rejected accordingly.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-4, 6-14, 16-18 and 20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Claim 1 recites an abstract mental process including organizing, observing and evaluating data (e.g. values for a plurality of parameters … a first error in the system … using particular values for parameters … information corresponding to the events … determining … whether or not he first error matches events”).
This judicial exception is not integrated into a practical application because the additional elements (“one or more processors”, “a non-transitory computer readable medium”) are only recited at a high level of generality and describe generic computing components. Further, the actions attributed to them (“storing”, “receiving”, “accessing”, “returning”, and “determining”) only describe generic computer functionality and thus amount to no more than instructions to implement the abstract idea using a computer.
The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception because, as noted above, the additional elements amount to no more than instructions to implement the abstract idea using a computer.
Claims 2-3, 5-10 and 12 recite further details of the data being observed and/or evaluated and thus are also directed to the abstract idea discussed above. Further, the claims do not introduce any new additional elements. Accordingly, the claims are directed to an abstract mental process without significantly more.
Claim 11 recites first and second program codes compiled into a program to perform the abstract mental process of claim 1. This describes only a generic computing function and thus amounts to no more than instructions to implement the abstract mental process using a computer. Accordingly, the claim is directed to an abstract mental process without significantly more.
Claims 13-14 and 16 recite a method for performing the abstract mental process(es) recited in claims 1-2, 4-5, and do not introduce new additional elements. Accordingly, for the reasons discussed above, the claims directed to an abstract mental process without significantly more.
Claims 17-18 and 20 recite a non-transitory computer readable medium storing instructions for performing the abstract mental process of claims 1-2 and 4-5. The additional element (non-transitory computer-readable medium” is recited only at a high level of generality and describes only generic computing components, and thus amount to no more than instructions to perform the abstract mental process using a computer. Accordingly, the claims directed to an abstract mental process without significantly more.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 5-8, 10-15 and 17-19 are rejected under 35 U.S.C. 103 as being unpatentable over US 10,204,030 to Hockett et al. (Hockett) in view of US 2003/0121027 to Hines (Hines).
Claims 1, 13 and 17: Hockett discloses a verification system comprising:
one or more processors;
a non-transitory computer-readable medium storing a program executable by the one or more processors, the program comprising sets of instructions for:
storing values for a plurality of parameters for a plurality of nodes of a debug tree (col. 10, lines 22-24 “annotates the generated nodes and branches as needed”), the debug tree comprising a root node and said plurality of nodes associated to the root node directly or through one or more other nodes (col. 10, lines 50-51 “a first node in the decision tree”, Fig. 4), wherein the parameters specify events defining electronically stored errors in a system being verified, wherein each event corresponds to a particular node of the plurality of nodes of the debug tree (e.g. col. 10, 34-38 “error code: “CEZIP1234””), and specifying a temporal relationship between the at least one node to adjacent node in the debug tree (col. 10, lines 53-58 “a time shortly before … the timestamp associated with the first node”);
receiving an input specifying a first error in the system being verified (e.g. col. 10, 34-38 “error code: “CEZIP1234” … a generated regular expression (regex) pattern”);
accessing one or more data sources using particular values for parameters associated with each node, the data sources comprising information describing errors generated by the system being verified corresponding to the events for the plurality of nodes (col. 10, lines 53-58 “open “Log2”, and search for an occurrence of “MyPattern”);
returning, for each node, information corresponding to the events (col. 10, line 61 “The search returns line 403”); and
determining, for each node, whether or not the first error matches events corresponding to the plurality of nodes (col. 11, lines 1-3 ““Error Allocating Resources” as an exact text match”).
Hockett does not disclose:
parameters for at least one node comprise a parameter specifying a temporal relationship between the at least one node and an adjacent node in the debug tree, wherein the temporal relationship indicates a search direction in which the system starts a search for the adjacent node, the search direction being one of:
forward, in which the system starts the search forward in time from the at least one node;
backward, in which the system starts the search backward in time from the at least one node; or
sametime, in which the system starts the search at the same time as the at least one node.
Hines teaches:
parameters for at least one node comprise a parameter specifying a temporal relationship between the at least one node to adjacent node in the debug tree, wherein the temporal relationship indicates a search direction in which the system starts a search for the adjacent node (par. [0461] “looking for sequences that match the expression <[[a b]]c> (viz., a and b are concurrent, and both causally precede c)”), the search direction being one of:
forward, in which the system starts the search forward in time from the at least one node (par. [0461] “a and b … causally precede c)”);
backward, in which the system starts the search backward in time from the at least one node (par. [0461] “a and b … causally precede c)”, note that this relationship is bidirectional); or
sametime, in which the system starts the search at the same time as the at least one node (par. [0461] “a and b are concurrent”).
It would have been obvious at the time of filing to include parameters specifying a temporal relationship as claimed. Those of ordinary skill in the art would have been motivated to do so to provide a mechanism for describing distributed behavior “patterns that have both causality and concurrence” (see e.g. Hines par. [0460]).
Claims 2, 14 and 18: Hockett and Hines teach the verification system of claims 1, 13 and 17, wherein the parameters for at least one node comprise a first parameter to describe a path to at least one of the data sources (Hockett col. 9, lines 63-64 ““filename”: “/tmp/log.txt”” // This is the exact file name where we are searching”) and one or more second parameters describing one or more regular expressions for searching the at least one of the data sources (Hockett col. 10, 34-38 “a generated regular expression (regex) pattern”).
Claim 3: Hockett and Hines teach the verification system of claim 2, wherein the one or more second parameters comprise a plurality of second parameters describing a plurality of regular expressions (Hockett col. 10, 34-38 “a generated regular expression (regex) pattern”), the parameters for at least one node further comprising a parameter to describe a relationship between the plurality of second parameters (Hockett col.10 , 53-58 “a time shortly before … the timestamp associated with the first node”).
Claims 5, 15 and 19: Hockett and Hines teach claims 1, 13 and 17, wherein the parameter specifying a temporal relationship between the at least one node to adjacent nodes in the debug tree include temporal relationships to other nodes defined using the following set: {FORWARD, BACKWARD, SAMETIME} indicating direction of search for the other nodes (Hockett col. 10, lines 53-58 “a time shortly before … the timestamp associated with the first node”, Hines par. [0461] “a and b are concurrent, and precede c”, note that, although not indicated by the same text string, this specifies the claimed relationships).
Claim 6: Hockett and Hines teach the verification system of claim 1, wherein the parameters for at least one node comprise a parameter specifying a timeframe for a search (Hockett col. 10, lines 53-58 “a time shortly before … the timestamp associated with the first node”).
Claim 7: Hockett and Hines teach the verification system of claim 1, wherein the system being verified is one of: a software system and a high level definition of an electronic system (Hockett col. 10, lines 34-36 “software application”).
Claim 8: Hockett and Hines teach the verification system of claim 1, wherein when the input matches at least a first portion of said events and the input does not match a second portion of said events corresponding to the plurality of nodes, and further comprising instructions for:
prompting a user to define a new event for a new node of the debug tree, wherein the user specifies new values for said parameters for the new node of the debug tree (Hockett col. 10, lines 22-26 “user annotates the generated nodes and branches as needed”).
Claim 10: Hockett and Hines teach the verification system of claim 1, wherein the root node is associated with context for said accessing and determining steps, the context comprising information specifying one or more of: database sources, log files, stored RTL signals, parameters for a test bench, and custom debug functions (e.g. Hockett col. 12, lines 41-46 “by reference to 401 and 402, knows to open “Log2”, … metadata from the first node”).
Claim 11: Hockett and Hines teach the verification system of claim 1, further comprising instructions for receiving a first program code for generating the debug tree (Hockett Fig. 3, Decision Tree Module 315) and a second program code for accessing the one or more data sources using the particular values for the parameters associated with each node (Hockett Fig. 3, Playback Module ), wherein the first program code and second program code are compiled into said program to perform said accessing, returning, and determining steps (Hockett Fig. 3, Program 300).
Claim 12: Hockett and Hines teach the verification system of claim 1, wherein the debug tree describes a set of observable events that associate an electronically recorded failure to a root cause (Hockett col. 10, 34-38 “error code: “CEZIP1234””).
Claims 4, 9, 16 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over US 10,204,030 to Hockett et al. (Hockett) in view of in view of US 2003/0121027 to Hines (Hines) in view of US 2002/0173942 to Rajsuman et al. (Rajsuman).
Claims 4, 16 and 20: Hockett and Hines teach claims 1, 13 and 17, but does not explicitly disclose the parameters for at least one node comprise a parameter to a waveform event.
Rajsuman teaches
a parameter to a waveform event (e.g. Fig. 3, “Event Waveform 58”).
It would have been obvious at the time of filing to include a parameter to a waveform event (Rajsuman Fig. 3, Event Waveform 58, Hockett col. 10, 34-38 “error code: “CEZIP1234””). Those of ordinary skill in the art would have been motivated to do so to allow for the debugging of hardware (see e.g. Rajsuman Abstract “validation of complex IC”).
Claim 9: Hockett and Hines teach the verification system of claim 8, wherein at least one of the parameters specifies whether the new event occurs before or after another event corresponding to another node of the debug tree (Hockett col. 10, lines 53-58 “a time shortly before … the timestamp associated with the first node”).
Hockett does not disclose:
the system being verified is a high level definition of an electronic system.
Rajsuman teaches
a system being verified is a high level definition of an electronic system (see e.g. Rajsuman Abstract “validation of complex IC”, par. [0003] “a high-level description language such as Verilog and VHDL”).
It would have been obvious at the time of filing to verified is a high level definition (HDL) of an electronic system (Rajsuman Abstract “validation of complex IC”). Those of ordinary skill in the art would have been motivated to do so to allow for the debugging of hardware (see e.g. Rajsuman Abstract “validation of complex IC”).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JASON D MITCHELL whose telephone number is (571)272-3728. The examiner can normally be reached Monday through Thursday 7:00am - 4:30pm and alternate Fridays 7:00am 3:30pm.
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/JASON D MITCHELL/Primary Examiner, Art Unit 2199