DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on January 12, 2026 has been entered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-7 and 9-11 and 13-16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al (U.S. Patent Pub. No. 2019/0057646; already of record) in view of Kim et al (U.S. Patent Pub. No. 2019/0164491; already of record) in view of Tseng et al (U.S. Patent Pub. No. 2018/0151115; already of record) and in view of IN et al (U.S. Patent Pub. No. 2021/0134210; already of record).
Regarding claim 1, Lin discloses a display device (14), (fig. 1, [0025]), comprising:
a display panel (14) having a plurality of gate lines (28), a plurality of data lines (26) and a plurality of subpixels (22) disposed thereon, (fig. 1, [0026-0027]);
a gate driver (18) including a scan driver (18) supplying a scan signal (Scan1) to the gate lines (28) and an emission driver (18) supplying a light emission signal (EM1) to a light emission line (314), (figs. 1 and 4, [0030 and 0040]); and
a data driver (20) which, in operation, supplies a data voltage (data signal) to the plurality of data lines (26), (figs. 1 and 4, [0028-0029 and 0040]);
wherein each of the plurality of subpixels (22) includes:
a light emitting device (304), (fig. 4, [0041]);
a driving transistor (T2) including a gate electrode, a source electrode and a drain electrode, the driving transistor, in operation, driving the light emitting device (304), (figs. 4-5, [0041 and 0047-0048]);
at least one switching transistor (T6) that is an N-type transistor (n-channel), (fig. 4, [0035]);
an EM transistor (T5) coupled between the driving transistor (T2) and the light emitting device (304), (fig. 4, [0041]); and
a capacitor (Cst) having one side connected to the gate electrode of the driving transistor (T2), (fig. 4, [0042]);
a third switching transistor (T3), (fig. 4); and
a fourth switching transistor (T1) connected to the data lines (i.e. data signal terminal 310 of fig. 4 is coupled to a respective data line 26 of fig. 1), [0042];
wherein the at least one switching transistor includes a first switching transistor (T6), (fig. 4, [0042]), and
wherein when the scan signal (Scan1) is applied, the first switching transistor (T6) is turned-on, and applies an initialization voltage (Vini) to the one side of the capacitor (Cst), (figs. 4-5, [0044]),
wherein the third switching transistor (T3) is an N type transistor and the one side of the capacitor (Cst) is connected to a source electrode of the third switching transistor (T3) through node 2, (fig. 4, [0042]).
However, Lin does not mention the second switching transistor is connected between a pre-driving voltage terminal and a node between the driving transistor and the EM transistor.
In a similar field of endeavor, Kim teaches wherein the at least one switching transistor includes a first switching transistor (T5) and a second switching transistor (T2),
wherein the second switching transistor (T2) is connected between a pre-driving voltage terminal (Vref) and a node (N1) between the driving transistor (DT) and the EM transistor (T3), and in operation, a pre-driving voltage (Vref) is applied from the pre-driving voltage terminal to the one side (N2) of the capacitor (Cst) through the second switching transistor (T2) and the driving transistor (DT), when the data voltage is not applied to the capacitor (i.e. after the sampling period SAM, the signal Scan(n-1) is at a high voltage hence the data voltage is not applied to the capacitor while the voltage Vref is applied to the transistor T2 because the signal Scan(n) is at a low voltage level), (figs. 5a-5b, [0114-0117]).
Therefore, it would have been obvious to one of ordinary skills in the art at the effective filing date of the claimed invention to modify Lin, by specifically providing the second switching transistor, as taught by Kim, for the purpose of minimizing voltage drop occurring in a line to which a voltage is applied, [0009].
However, Lin in view of Kim does not mention wherein during the entire time when the second switching transistor is turned on, the first switching transistor is turned on.
In a similar field of endeavor, Tseng teaches
wherein during the entire time when the second switching transistor (M1) is turned on, the first switching transistor (M8) is turned on (i.e. during the phase T2, the scan signal S1 turns on the switch transistor M1 while the reset control signal CS turns on the switch transistor M8), (figs. 2a and 8a, [0024 and 0054]).
Therefore, it would have been obvious to one of ordinary skills in the art at the effective filing date of the claimed invention to modify Lin in view of Kim, by specifically providing the switching switch transistor to be on during the entire time the first switching transistor is turned on, as taught by Tseng, for the purpose of having a pixel compensation circuit, [0005].
However, Lin in view of Kim and in view of Tseng does not mention wherein the first period during which the first transistor is turned on is longer than the second period during which the second transistor is turned on.
In a similar field of endeavor, IN teaches
wherein the first period (first bias period BP1) during which the first switching transistor (M8) is turned on is longer than the second period (initialization period IP) during which the second switching transistor (M7) is turned on, (figs. 2-3, [0110, 0126 and 0132]), and
wherein a first point of time (period BP1) when the first switching transistor (M8) performs the turn-on operation (i.e. during period BP1, signal S3i is at a low level, thus turning on the transistor M8) is prior to a second point of time (periods IP and CP) when the second switching transistor (M7) performs the turn-on operation (i.e. during period IP and CP, signal S1i-1 is at a low level, thus turning on transistor M7), and a third point of time (period BP2) when the second switching transistor (M7) performs the turn-off operation (i.e. during period BP2, signal S1i-1 is at a high level, thus turning off transistor M7) is prior to a fourth point of time (period EP) when the first switching transistor (M8) performs the turn-off operation (i.e. during period EP, signal S3i is at a high level, thus turning off transistor M8), (figs. 2-3, [0126, 0132 and 0138-0140]),
wherein a point of time when the second switching transistor (M7) performs the turn-off operation (i.e. transistor M7 is off during period BP1 when signal S1i-1 is at a high level) is prior to a point of time when the fourth switching transistor (M2) performs the turn-on operation (i.e. transistor M2 is on during period WP when signal S1i is at a low level, wherein the period BP1 is prior to the period WP), (figs. 2-3, [0126 and 0134]).
Therefore, it would have been obvious to one of ordinary skills in the art at the effective filing date of the claimed invention to modify Lin in view of Kim and in view of Tseng, by specifically providing the first period is turned on longer than the second period, as taught by IN, for the purpose of securing a threshold voltage compensation time of a first transistor of a pixel and periodically applying a bias voltage to the first transistor, [0007].
Regarding claim 2, Lin discloses wherein the driving transistor (T2) is an N type transistor (n-channel), (fig. 4, [0035]).
Regarding claim 3, Lin discloses wherein all of the at least one switching transistor (T6) and the EM transistor (T5) are N type transistors (n-channel), respectively, (fig. 4, [0035]).
Regarding claim 4, Lin discloses wherein all of the at least one switching transistor (T6), the EM transistor (T5) and the driving transistor (T2) are N type transistors (n-channel), respectively, (fig. 4, [0035]).
Regarding claim 5, Lin discloses wherein a first voltage (VDDEL) is applied to the drain electrode of the driving transistor (T2), (fig. 6a, [0044]).
Regarding claim 6, Lin discloses wherein the first voltage (VDDEL) is higher than the data voltage (Vdata), (fig. 6b, [0045]).
Regarding claim 7, Lin discloses wherein the first voltage (VDDEL) is higher than the data voltage (Vdata) of maximum gradation, (fig. 6b, [0039 and 0045]).
Regarding claim 9, Lin discloses wherein the gate driver (18) includes at least two scan drivers (left and right row driver circuitry 18) and at least one EM driver (i.e. driver which output emission control signal EM1), (figs. 1 and 4, [0027 and 0040]).
Regarding claim 10, Lin discloses further comprising a third switching transistor (T3), and wherein the at least two scan drivers include a first scan driver (i.e. left row driver circuitry 18) and a second scan driver (i.e. right row driver circuitry 18),
wherein when the scan signal (Scan1) supplied by the first scan driver is applied, the first switching transistor (T6) that is an N type transistor is turned-on, (figs. 5 and 6a, [0044]), and
wherein when the scan signal (Scan1) supplied by the second scan driver is applied, the third switching transistor (T3) is turned-on, (figs. 5 and 6a, [0044]).
Regarding claim 11, Lin discloses wherein the third switching transistor (T3) includes a source electrode and a drain electrode, and a first voltage (VDDEL) is applied to the drain electrode of the third switching transistor (T3), (fig. 6a, [0044]).
Regarding claim 13, Lin discloses wherein the third switching transistor (T3) is electrically connected between the gate electrode of the driving transistor (T2) and the source electrode of the driving transistor (T2), (fig. 4, [0041-0042]).
Regarding claim 14, Lin discloses further comprising a fifth switching transistor (T4) and a fourth switching transistor (T1), wherein the fourth switching transistor (T1) is connected to the data lines (310), and
wherein the fifth switching transistor (T4), in operation, performs a turn-on operation (i.e. turn on during Initialization phase) prior to the fourth switching transistor (T1), (figs. 4-5, [0043-0044]).
Regarding claim 15, Lin discloses wherein the fifth switching transistor (T4), in operation, performs a turn-off operation (i.e. turn off at time t2) prior to a point of time when the fourth switching transistor (T1) performs the turn-on operation (i.e. T1 turns on during on-bias stress phase), (figs. 4-5, [0045]).
Regarding claim 16, Lin discloses further comprising a fourth switching transistor (T1), wherein the fourth switching transistor (T1) is connected to the data lines (26), and
wherein the third switching transistor (T3), in operation, performs the turn-on operation (i.e. turn on during time t1) prior to the fourth switching transistor (i.e. transistor T1 turn on during time t2), (figs. 4-5, [0044-0045]).
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lin in view of Kim in view of Tseng in view of IN and in view of Han et al (U.S. Patent Pub. No. 2014/0139510; already of record).
Regarding claim 8, Lin discloses everything as specified above in claim 6. However, Lin in view of Kim in view of Tseng and in view of IN does not mention a driving voltage line supplying a second voltage to the source electrode of the driving transistor or to the drain electrode of the driving transistor.
In a similar field of endeavor, Han teaches wherein the display panel (110) further comprises a driving voltage line (Mi) supplying a second voltage (Vpre) to the source electrode of the driving transistor (DT), (figs. 2 and 6, [0050 and 0117]), and
wherein the second voltage (Vpre) is higher than the first voltage (VDD_i) (i.e. first driving voltage VDD_i having the first voltage level V1, which is lower than the second voltage level V2 and equal to or lower than the pre-charging voltage Vpre), (fig. 6, [0117]).
Therefore, it would have been obvious to one of ordinary skills in the art at the effective filing date of the claimed invention to modify Lin in view of Kim in view of Tseng and in view of IN, by specifically providing the driving voltage line, as taught by Han, for the purpose of increasing a current efficiency, [0012].
Response to Arguments
Applicant’s arguments, see page 6, filed December 9, 2025, with respect to the rejection(s) of claim(s) 1 under U.S.C. 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of a different interpretation of the prior art of IN, please see rejection above in claim 1 for details.
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/LONG D PHAM/Primary Examiner, Art Unit 2623