DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis ( i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale , or otherwise available to the public before the effective filing date of the claimed invention. Claims 1- 2 and 4 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Ker et al (US Patent No. 6388850). Regarding claim 1 , Ker discloses a n electrostatic breakdown protection circuit (fig. 14, Col. 8 lines 4+) included in an electronic device ( i.e., such as ESD-protection devices, see for example fig. 13, Col. 7 lines 59+ ) including an external terminal (Input Pad) and an internal circuit (100) connected to the external terminal (Input Pad) , the electrostatic breakdown protection circuit (fig. 14) comprising: a first series diode group ( Dp-Dpk ) in which n diodes (i.e., n = k) including a first diode ( Dpk ) having an anode (anode/+) connected to the external terminal (Input Pad) and a second diode ( Dp ) having a cathode (cathode/-) applied with a power supply voltage (VDD) are connected in series, where n (i.e., k) is an integer equal to or larger than 2 (i.e., k > 2) ; and a second series diode group ( Dn-Dnk ) in which n (i.e., n = k) diodes including a third diode (Dn1) having a cathode (cathode/-) connected to the external terminal (Input Pad) and a fourth diode ( Dn ) having an anode (anode/+) applied with a ground voltage (VSS) are connected in series. Regarding claim 2 , Ker discloses the electrostatic breakdown protection circuit (fig. 14, Col. 8 lines 4+), further comprising: a resistor (R) of which one end (i.e., the electronic device external end) is connected to the external terminal (Input Pad) and another end (i.e., the electronic device internal end) is connected to the internal circuit (100) ; and a capacitor ( i.e., internal capacitor Cn) of which one electrode (i.e., Cn terminals /ends ) is connected (i.e., Cn is clamped to the R via Dps and to the GND/VSS via Mrn ) to the another end of the resistor (R) and another electrode (i.e., Cn terminals /ends ) is applied (i.e., clamped/connected) with the ground voltage (VSS). Regarding claim 4 , Ker discloses the electrostatic breakdown protection circuit (fig. 14, Col. 8 lines 4+), wherein the first series diode group ( Dp-Dpk ) includes the first diode ( Dpk ) and the second diode ( Dp ) of which an anode (anode/+) is connected to a cathode (cathode/-) of the first diode ( Dpk ) , and wherein the second series diode group ( Dn-Dnk ) includes the third diode (Dn1) and the fourth diode ( Dn ) of which a cathode (cathode/-) is connected to an anode (anode/+) of the third diode (Dn1) (Note: both strings of diodes Dps and Dns are anode-to-cathode series standard configuration). Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis ( i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Ker et al (US Patent No. 6388850) in view of Shimada (US Publication No. 20170300148 ). Regarding claim 3, Ker discloses the electrostatic breakdown protection circuit (fig. 14, Col. 8 lines 4+) , wherein the electronic device (10/Input Pad) is a semiconductor device (fig. 14). Ker does not explicitly disclose wherein the external terminal is a terminal to which an electrode of a capacitor is externally attached from outside of the electronic device. Shimada discloses a capacitance measurement circuit measures each of multiple electrostatic capacitances (100a, fig. 9, para. [0103]- [0112]); wherein the external terminal (SN) is a terminal (i.e., terminal 34 extended via SW6) to which an electrode (i.e., terminal TX) of a capacitor (i.e., CM) is externally attached (i.e., CM is externally clamped to TX, SN, respectively) from outside of the electronic device (i.e., IC-4). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have optionally included the external capacitor in Ker , as taught by Shimada , as it provides the advantage of optimizing the circuit design towards dissipat ing ESD events and safeguarding sensitive components from damage. Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Ker et al (US Patent No. 6388850) in view of Ker et al ( US Publication No. 20020130390 ). Regarding claim 5 , Ker discloses the electrostatic breakdown protection circuit (fig. 14, Col. 8 lines 4+) , wherein the electronic device (10/Input Pad) is a semiconductor device (fig. 14). Ker does not explicitly disclose wherein the first diode is a first MOS transistor of which a source is connected to the external terminal and a gate is applied with the power supply voltage, wherein the second diode is a second MOS transistor of which a source is connected to a drain of the first MOS transistor and a drain and a gate are applied with the power supply voltage, wherein the third diode is a third MOS transistor of which a source is connected to the external terminal and a gate is applied with the ground voltage, and wherein the fourth diode is a fourth MOS transistor of which a source is connected to a drain of the third MOS transistor and a drain and a gate are applied with the ground voltage. Ker discloses an ESD protection circuit with low input capacitance, suitable for an I/O pad (fig. 19, para. [0057]); wherein the first diode (MD p3 ) is a first MOS transistor (MD p3 / P MOS) of which a source (S) is connected to the external terminal (30/Pad) and a gate (G) is applied with the power supply voltage (VDDA) , wherein the second diode (MDp2) is a second MOS transistor (MDp2/PMOS) of which a source (S) is connected to a drain (D) of the first MOS transistor (MDp3/PMOS) and a drain (D) and a gate (G) are applied with the power supply voltage (VDDA) , wherein the third diode (MDn2) is a third MOS transistor (MDn2/NMOS) of which a source (S) is connected to the external terminal (30/Pad) and a gate (G) is applied with the ground voltage (VSSA) , and wherein the fourth diode (MDn3) is a fourth MOS transistor (MDn3/NMOS) of which a source (S) is connected to a drain (D) of the third MOS transistor (MDn2/NMOS) and a drain (D) and a gate (G) are applied with the ground voltage (VSSA). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have optionally included the MOS device in Ker , as taught by K er , as it provides the advantage of optimizing the circuit design towards reverse-polarity protection and absorbing spikes from inductive loads, acting as a freewheeling diode. Claims 6-7 are rejected under 35 U.S.C. 103 as being unpatentable over Ker et al (US Patent No. 6388850) in view of Tsai et al (US Publication No. 20080018473 ). Regarding claim 6 , Ker discloses the electrostatic breakdown protection circuit (fig. 14, Col. 8 lines 4+) . Ker does not explicitly disclose wherein the electronic device includes a communication circuit that performs wireless communication conforming to a short-range wireless communication standard. Tsai discloses t echniques for protecting components of an RFID tag from electrostatic discharge (50, fig. 2A, para. [0034]- [0041]) ; wherein the electronic device (56) includes a communication circuit (55) that performs wireless communication (i.e., such as antenna 54) conforming to a short-range wireless communication standard (i.e., such as a 2.45 GHz RFID tag, see for example para. [0034]). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have optionally included the RFID-technology in Ker , as taught by Tsai , as it provides the advantage of optimizing the circuit design towards allow ing rapid and accurate data capture of multiple items simultaneously . Regarding claim 7 , Ker in view of Tsai and the teachings of Ker as modified by Tsai have been discussed above. Tsai further discloses (50, fig. 2A, para. [0034]- [0041]), wherein the electronic device (56) is an IC tag (i.e., such as a 2.45 GHz RFID tag, see for example para. [0034]) that receives power wirelessly (i.e., via antenna 54). Allowable Subject Matter Claims 8-10 are allowed. The following is an examiner’s statement of reasons for allowance: Regarding claim 8 , Ker does not teach or suggest; a capacitance sensor device, comprising: a sensor capacitor of which a capacitance changes according to changes in an environment; a first external terminal to which an electrode of the sensor capacitor is externally attached; a first electrostatic breakdown protection circuit which is connected to the first external terminal; a first capacitance circuit which has a first reference capacitance; and a determination circuit which includes a first relay terminal and a second relay terminal, supplies a charging current from the first relay terminal to the sensor capacitor via the first electrostatic breakdown protection circuit and the first external terminal, supplies a charging current from the second relay terminal to the first capacitance circuit, and then compares a magnitude of a potential of the first relay terminal with a magnitude of a potential of the second relay terminal to detect the capacitance of the sensor capacitor or detect whether there is a change in the capacitance of the sensor capacitor, wherein the first electrostatic breakdown protection circuit includes: a first diode of which an anode is connected to the first external terminal, a second diode of which a cathode receives a power supply voltage and an anode is connected to a cathode of the first diode, a third diode of which a cathode is connected to the first external terminal, and a fourth diode of which an anode receives a ground voltage and a cathode is connected to an anode of the third diode. Claims 9-10 are allowed, as they depend on allowed claim 8. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to FILLIN "Examiner name" \* MERGEFORMAT MUAAMAR Q AL-TAWEEL whose telephone number is FILLIN "Phone number" \* MERGEFORMAT (571)270-0339 . The examiner can normally be reached FILLIN "Work Schedule?" \* MERGEFORMAT 0730-1700 . Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, FILLIN "SPE Name?" \* MERGEFORMAT Thienvu V Tran can be reached at FILLIN "SPE Phone?" \* MERGEFORMAT (571) 270- 1276 . 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