DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they include the following reference character not mentioned in the description: “R1” (Figs. 3-4). Corrected drawing sheets in compliance with 37 CFR 1.121(d), or amendment to the specification to add the reference character(s) in the description in compliance with 37 CFR 1.121(b) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claims 3-7 are objected to because of the following informality: Claims 3 (see line 2) and 4 (see line 2) use the term “said” to refer to previously introduced elements. The claims also use the term “the” to refer to previously introduced elements. Either used of the term “said” should be replaced with “the” or vice versa to ensure consistency of claim terminology. Claims 5-7 are likewise objected to under this logic by virtue of their dependency on claim 4. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-9 and 12-13 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 1 and 12 recite the limitation "the resistance" in lines 5 and 4, respectively. There is insufficient antecedent basis for this limitation in the claims. Amending the limitation to “a resistance” is sufficient to overcome this rejection, which is how the claims will be treated for examination purposes. Claims 2-9 and 13 are likewise rejected under this logic by virtue of their dependencies on claims 1 and 12, respectively.
Claim 6 recites the limitation “resistor” in line 2. There is insufficient antecedent basis for this limitation in the claim. Amending the limitation to “the resistor” is sufficient to overcome this rejection, which is how the claim will be treated for examination purposes. Claim 7 is likewise rejected under this logic by virtue of its dependency on claim 6.
Claim 13 recites the limitations “first and second transistor” in line 2 and “the first and second transistors” in line 4. There is insufficient antecedent basis for these limitations in the claim. Amending the limitations to “a first transistor and a second transistor” and “the first transistor and the second transistor”, respectively, is sufficient to overcome this rejection, which is how the claim will be treated for examination purposes.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3 and 8-12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Williams (Patent Number US 4,574,249 A), hereafter referred to as Williams.
Regarding claim 1, Williams discloses:
A transimpedance amplifier circuit (Williams, Figs. 38-39) comprising: a transimpedance amplifier (Fig. 38, “NIR 10”) with an input node (Fig. 38, see input of NIR 10) for receiving an input current (Fig. 38, consider current output from photodiode); a variable shunt resistance (Fig. 38, RS) connected to the input node (Fig. 38, see connection between RS and NIR 10); and a controller (Fig. 38, AGC) operable to controllably vary an open-loop transimpedance gain of the transimpedance amplifier (Col. 19, lines 27-29) and also the resistance of the variable shunt resistance so as to vary a closed-loop transimpedance gain of the transimpedance amplifier (Col. 19, lines 37-40).
Regarding claim 2, Williams further discloses:
wherein the transimpedance amplifier comprises an input transistor (Williams, Fig. 39, Q1) with a control terminal connected to the input node (Fig. 39, see connection between gate of Q1 and input of amplifier), the input transistor being in series with a first transistor (Fig. 39, see connection between Q1 and 38, see also Col. 20, lines 48-52 [38 is a transistor amplifier]) in a first circuit branch (Fig. 39, see connection between Q1 and 38) and wherein the controller is operable to controllably vary a control current injected into the first circuit branch to controllably vary the open-loop transimpedance gain (Col. 20, lines 34-35).
Regarding claim 3, Williams further discloses:
comprising a control transistor (Williams, Fig. 39, Element 38, see also Col. 20, lines 48-52 [38 is a transistor amplifier]) configured to be controlled by a control voltage from the controller to provide said control current (Fig. 39, see connection between controller 30 and transistor 38 with voltage V2, see also Col. 20, lines 34-35).
Regarding claim 8, Williams further discloses:
wherein the controller is configured to vary the closed-loop transimpedance gain of the transimpedance amplifier based on an indication of input current at the input node (Williams, Col. 19, lines 37-40).
Regarding claim 9, Williams further discloses:
An optical receiver comprising the transimpedance amplifier circuit of claim 1 (Williams, Fig. 38) and a photodetector (Fig. 38, see photodetector) configured to receive an input optical signal (Fig. 38, see input into photodetector) and output a photocurrent to the input node of the transimpedance amplifier (Fig. 38, see connection between photodetector and NIR 10).
Regarding claim 10, Williams discloses:
A transimpedance amplifier circuit (Williams, Fig. 38) comprising: a transimpedance amplifier (Fig. 38, “NIR 10”) with an input node for receiving an input current (Fig. 38, see input of NIR 10); a variable shunt resistance (Fig. 38, RS) connected to the input node (Fig. 38, see connection between RS and NIR 10).
Regarding claim 11, Williams discloses:
A transimpedance amplifier circuit (Williams, Figs. 38-39) comprising: a transimpedance amplifier (Fig. 38, “NIR 10”) with an input node (Fig. 38, see input of NIR 10) for receiving an input current (Fig. 38, consider current output from photodiode), the transimpedance amplifier comprising an input transistor (Williams, Fig. 39, Q1) in series with a cascode transistor (Fig. 39, see connection between Q1 and 38, see also Col. 20, lines 48-52 [38 is a transistor amplifier]) in a first circuit branch (Fig. 39, see connection between Q1 and 38) and a second transistor (Fig. 39, Element 38) configured to inject a controllably variable control current into the first circuit branch to vary an open-loop transimpedance gain of the transimpedance amplifier (Col. 20, lines 34-35).
Regarding claim 12, Williams discloses:
A transimpedance amplifier circuit (Williams, Figs. 38-39) comprising: a transimpedance amplifier (Fig. 38, “NIR 10”) with an input node (Fig. 38, see input of NIR 10) for receiving an input current (Fig. 38, consider current output from photodiode); a variable shunt resistance (Fig. 38, RS) connected to the input node (Fig. 38, see connection between RS and NIR 10); and a controller (Fig. 38, AGC) operable to controllably vary the resistance of the variable shunt resistance so as to vary a closed-loop transimpedance gain of the transimpedance amplifier (Col. 19, lines 37-40).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4-7 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Williams as applied to claims 3 and 12, respectively, above, and further in view of Kaczman et al. “A Single-Chip 10-Band WCDMA/HSDPA 4-Band GSM/EDGE SAW-less CMOS Receiver With DigRF 3G Interface and +90 dBm IIP2”.
Regarding claim 4, Williams fails to disclose:
further comprising a second transistor in series with said control transistor in a second circuit branch, wherein the variable shunt resistance comprises a resistor connected between the input node and a node of the second circuit branch between the second transistor and the control transistor.
However, Kaczman teaches further comprising a second transistor (Kaczman, Fig. 9, see left transistor coupled to Vcmfb) in series with said control transistor in a second circuit branch (Fig. 9, see connection between left transistor coupled to Vcmfb and left transistor coupled to AGC_STEP), wherein the variable shunt resistance comprises a resistor (Fig. 9, R3) connected between the input node (Fig. 9, see connection between R3 and iRF(t)+) and a node of the second circuit branch between the second transistor and the control transistor (Fig. 9, see connection between left transistor coupled to Vcmfb and left transistor coupled to AGC_STEP via R3).
Williams and Kaczman are both considered to be analogous to the claimed invention because they are in the same field of improving amplifiers. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Williams to incorporate the teachings of Kaczman to include the gain control circuitry of Kaczman in the amplifier of Williams, which would have the effect of providing a wide range of gain control (Kaczman, Page 10, Col. 1, lines 11-14).
Regarding claim 5, Williams fails to disclose:
further comprising a control loop configured to control the second transistor to maintain a DC voltage across the resistor equal to zero.
However, Kaczman further teaches further comprising a control loop (Kaczman, Fig. 9, see loop from right edge of R3 through op amp and left transistor coupled to Vcmfb to left edge of R3) configured to control the second transistor to maintain a DC voltage across the resistor equal to zero (Page 10, Col. 2, lines 23-30).
Williams and Kaczman are both considered to be analogous to the claimed invention because they are in the same field of improving amplifiers. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Williams to incorporate the teachings of Kaczman to include the gain control circuitry of Kaczman in the amplifier of Williams, which would have the effect of providing a wide range of gain control (Kaczman, Page 10, Col. 1, lines 11-14).
Regarding claim 6, Williams fails to disclose:
wherein the control loop comprises an op-amp connected in parallel with resistor.
However, Kaczman further teaches wherein the control loop comprises an op-amp (Kaczman, Fig. 9, see op amp with output coupled to Vcmfb) connected in parallel with resistor (Fig. 9, see connection between R3 and op amp with output coupled to Vcmfb).
Williams and Kaczman are both considered to be analogous to the claimed invention because they are in the same field of improving amplifiers. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Williams to incorporate the teachings of Kaczman to include the gain control circuitry of Kaczman in the amplifier of Williams, which would have the effect of providing a wide range of gain control (Kaczman, Page 10, Col. 1, lines 11-14).
Regarding claim 7, Williams fails to disclose:
wherein the controller is configured to set the control voltage to zero to provide a high-gain mode and is configured to set the control voltage to a non-zero bias voltage to provide a low-gain mode.
However, Kaczman further teaches wherein the controller is configured to set the control voltage to zero to provide a high-gain mode (Kaczman, Fig. 9, consider control voltage AGC_STEP, see also Page 10, Col. 2, lines 7-8) and is configured to set the control voltage to a non-zero bias voltage to provide a low-gain mode (Fig. 9, consider control voltage AGC_STEP, see also Page 10, Col. 2, lines 8-9).
Williams and Kaczman are both considered to be analogous to the claimed invention because they are in the same field of improving amplifiers. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Williams to incorporate the teachings of Kaczman to include the gain control circuitry of Kaczman in the amplifier of Williams, which would have the effect of providing a wide range of gain control (Kaczman, Page 10, Col. 1, lines 11-14).
Regarding claim 13, Williams further discloses:
comprising a circuit branch having first and second transistor in series (Williams, Fig. 39, see connection between Q1 and 38), and wherein the controller is configured to control a current through the first transistor so as to control the variable shunt resistance (Col. 19, lines 37-40 and 44-49), but fails to disclose wherein the variable shunt resistance comprises a shunt resistor coupled between the input node and a node located between the first and second transistors.
However, Kaczman teaches wherein the variable shunt resistance comprises a shunt resistor (Kaczman, Fig. 9, R3) coupled between the input node (Fig. 9, see connection between R3 and iRF(t)+) and a node located between the first and second transistors (Fig. 9, see connection between left transistor coupled to Vcmfb and left transistor coupled to AGC_STEP via R3).
Williams and Kaczman are both considered to be analogous to the claimed invention because they are in the same field of improving amplifiers. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Williams to incorporate the teachings of Kaczman to include the gain control circuitry of Kaczman in the amplifier of Williams, which would have the effect of providing a wide range of gain control (Kaczman, Page 10, Col. 1, lines 11-14).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Iotti et al. (Patent Publication Number US 2024/0195373 A1) discloses (Fig. 4) a cascode transimpedance amplifier.
Ito et al. (Patent Publication Number JP 2013/115562 A) discloses (Figs. 5/7) a transimpedance amplifier with an input variable shunt resistance.
Visocchi et al. (Patent Number US 6,297,701 B1) discloses (Fig. 6) a cascode transimpedance amplifier.
Smoot (Patent Number US 4,565,974 A) discloses (Fig. 3) a transimpedance amplifier with an input variable shunt resistance.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Lance T Bartol whose telephone number is (703)756-1267. The examiner can normally be reached Monday - Thursday 6:30 a.m. - 4:00 p.m. CT, Alternating Fridays 6:30 - 3:00.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrea Lindgren Baltzell can be reached at 571-272-5918. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/LANCE TORBJORN BARTOL/Examiner, Art Unit 2843
/ANDREA LINDGREN BALTZELL/Supervisory Patent Examiner, Art Unit 2843