Prosecution Insights
Last updated: April 19, 2026
Application No. 18/171,214

SWITCHED MODE POWER SUPPLY (SMPS)

Final Rejection §103
Filed
Feb 17, 2023
Examiner
ROSARIO BENITEZ, GUSTAVO A
Art Unit
2838
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Nxp Usa Inc.
OA Round
4 (Final)
81%
Grant Probability
Favorable
5-6
OA Rounds
2y 9m
To Grant
99%
With Interview

Examiner Intelligence

Grants 81% — above average
81%
Career Allow Rate
597 granted / 733 resolved
+13.4% vs TC avg
Strong +25% interview lift
Without
With
+25.3%
Interview Lift
resolved cases with interview
Typical timeline
2y 9m
Avg Prosecution
39 currently pending
Career history
772
Total Applications
across all art units

Statute-Specific Performance

§101
0.5%
-39.5% vs TC avg
§103
49.3%
+9.3% vs TC avg
§102
28.1%
-11.9% vs TC avg
§112
21.0%
-19.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 733 resolved cases

Office Action

§103
DETAILED ACTION This office action is in response to the amendment filed on 02/17/2016. Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Specification The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. Claim(s) 1 and 3-4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Liu et al. SAR-Controlled Adaptive Off-Time Technique Without Sensing Resistor for Achieving High Efficiency and Accuracy LED Lighting System in view of Fang US 2022/0311338. Regarding Claim 1, Liu teaches (Figures 6-12) A switched mode power supply (at fig. 7), comprising: an inductor (L) configured to supply an inductor current to a load (Co and LED); a charging circuit (Mn, Mdiode, controller and sensing circuit) configured to increase the inductor current during a primary stroke time window (phase 1, Fig. 6), and to decrease the inductor current during a secondary stroke time window (phase 2, Fig. 6); wherein the charging circuit (Mn, Mdiode, controller and sensing circuit) includes a current sensing element (sensing circuit) and a switch (Mn); wherein a first end of the current sensing element is coupled to a first end of the switch (with right side of input of the current sensing circuit at sw node) and a second end of the current sensing element is coupled to a ground potential (Fig. 12 the system is connected to ground); and wherein a second end (bottom terminal of Mn) of the switch (Mn) is coupled to the inductor (L, with the inductor current) and wherein the switch is between the current sensing element and the inductor (see figure below the inductor is in the top portion of the drawing with respect to the switch Mn and the current sensing circuit below the main switch with respect to said switch), wherein the charging circuit is configured to end the primary stroke when the inductor current reaches a high current limit (Ipeak); wherein the charging circuit is configured to set the secondary stroke time window to a predicted duration (off time); wherein the charging circuit is configured to automatically start the primary stroke after the predicted duration (On time after the off time) and measure the inductor current at the end of a detection window (Vsense Figure 6 and 12, also see Section IV, C); wherein if the inductor current is below a low limit at the end of the detection window (Vsense < Vref2), then the charging circuit is configured to shorten the predicted duration (the long off time is made shorten); and wherein if the inductor current is above the low limit at the end of the detection window (Vsense>Vref2), then the charging circuit is configured to lengthen the predicted duration (the short off time is made longer). (For Example See Sections III and IV) PNG media_image1.png 328 906 media_image1.png Greyscale Liu does not teach and wherein the charging circuit is configured to begin the detection window following a leading edge blanking time at the start of the primary stroke time window, the leading edge blanking time having a duration set to mitigate a voltage spike across the current sensing element at the start of the primary stroke time window. Fang teaches (Figures 2-3) wherein the charging circuit (10, HS and LS) is configured to begin the detection window (stage 2-3 in fig. 2) following a leading edge blanking time (stage 1, fig. 2) at the start of the primary stroke time window (see par. 27-29, when the current sensed is for the HS switch), the leading edge blanking time (Tb or stage1) having a duration set to mitigate a voltage spike across the current sensing element at the start of the primary stroke time window (par. 36). (For Example: Par. 32-36) It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Liu to include and wherein the charging circuit is configured to begin the detection window following a leading edge blanking time at the start of the primary stroke time window, the leading edge blanking time having a duration set to mitigate a voltage spike across the current sensing element at the start of the primary stroke time window, as taught by Fang to improve the quality of the sensed signal by removing spikes and noise. Regarding Claim 3, Liu teaches (Figures 6-12) wherein the low current limit (Vref2) can be set between a level close to zero (see Fig. 6 and See fig.14) and a level close to the high current limit (Ipeak). (For Example See Sections III and IV) Regarding Claim 4, Liu teaches (Figures 6-12) wherein the charging circuit is configured to measure the inductor current (with the current sense circuit) during the primary stroke time window (section IV letter C, mentions that the sensing circuit activates the sense mosfet Msense when the VPWM is high ); and wherein the charging circuit is configured not to measure the inductor current during the secondary stroke time window (during the off time the VPWM is low). (For Example See Sections III and IV) Regarding Claim 6, Liu teaches (Figures 6-12) wherein the controller (controller Fig. 7) is configured to measure the inductor current using the current sensing element (see section III with respect to figs. 5-6). (For Example See Sections III and IV) Regarding Claim 7, Liu teaches (Figures 6-12) wherein during the primary stroke (phase 1) the switch is configured to both conduct the inductor current and enable the current sensing element to measure the inductor current (see fig. 6 and section IV letter C). (For Example See Sections III and IV) Regarding Claim 8, Liu teaches (Figures 6-12) wherein during the secondary stroke (phase 2) the switch does not conduct the inductor current and thus the current sensing element cannot measure the inductor current (Section IV letter C the Msense is activated with the High PWM signal). (For Example See Sections III and IV) Regarding Claim 9, Liu teaches (Figures 6-12) wherein a controller (controller of fig. 7) is configured to set the switch to a closed state during the primary stroke (phase 1 and on time), and to set the switch to an open state during the secondary stroke (phase 2 and off time). (For Example See Sections III and IV) Regarding Claim 10, Liu teaches (Figures 6-12) wherein the current sensing element is a resistor (Fig. 12 and rsense). (For Example See Sections III and IV) Regarding Claim 12, Liu teaches (Figures 6-12) wherein a controller (Controller of fig. 7) is configured to derive the inductor current from a voltage across the resistor (rsense, fig. 7). (For Example See Sections III and IV) Regarding Claim 13, Liu teaches (Figures 6-12) wherein the load (Co and led) is a capacitor (Co) charged by the inductor current from the charging circuit. (For Example See Sections III and IV) Claim(s) 2 and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Liu and Fang and further in view of Becerra US 5886512. Regarding Claim 2, Liu teaches (Figures 6-12) the SMPS . Liu does not teach wherein the SMPS is operating in a continuous conduction mode (CCM). Becerra teaches (Figure 5) wherein the SMPS is operating in a continuous conduction mode (CCM). It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Liu to include wherein the SMPS is operating in a continuous conduction mode (CCM), as taught by Becerra to provide a switching converter having a wide input voltage operating range suitable for enabling low voltage power. Regarding Claim 14, Liu teaches (Figures 6-12) wherein a first end of the capacitor (Co) is coupled to the inductor (L). Liu does not teach a second end of the capacitor is coupled to a diode. Becerra teaches (Figure 5) a second end of the capacitor (CL) is coupled to a diode (Dfw or DL). It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Liu to include a second end of the capacitor is coupled to a diode, as taught by Becerra to provide a switching converter having a wide input voltage operating range suitable for enabling low voltage power. Claim(s) 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Liu and Fang and further in view Becerra9 US 5886512 (embodiment of figure 9). Regarding Claim 15, Liu teaches (Figures 6-12) the SMPS . Liu does not teach wherein the charging circuit includes a switch, a diode, and a capacitor; wherein the inductor is a first inductor; further comprising a second inductor coupled to the first inductor so as to form a transformer; wherein the first inductor is coupled to the switch; and wherein the second inductor is coupled to the diode and to the capacitor. Becerra9 teaches (Figure 9) wherein the charging circuit includes a switch (s), a diode (d4), and a capacitor (cl); wherein the inductor is a first inductor (TXI); further comprising a second inductor coupled to the first inductor so as to form a transformer; wherein the first inductor is coupled to the switch (s and TXl); and wherein the second inductor is coupled to the diode and to the capacitor (See Fig. 9). It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Liu to include wherein the charging circuit includes a switch, a diode, and a capacitor; wherein the inductor is a first inductor; further comprising a second inductor coupled to the first inductor so as to form a transformer; wherein the first inductor is coupled to the switch; and wherein the second inductor is coupled to the diode and to the capacitor, as taught by Becerra9 to provide a switching converter having a wide input voltage operating range suitable for enabling low voltage power. Response to Arguments Applicant's arguments filed 02/17/2026 have been fully considered but they are not persuasive. Applicant argued that “In setting forth the basis of the rejection, the Office Action relies on Liu as disclosing all the elements of claim 1 as previously pending. However, Applicant submits that Liu does not support the propositions for which it is cited. For example, the Office Action (at pages 3-4) opines…” However, Liu teaches in Figure 12 the claim subject matter because of the structure presented between the elements. First, the inductor current is sent to the main switch Mn and crosses both terminals when in the on state this means that the bottom terminal of the main switch is connected to the inductor and the top terminal is connected to the current sensing circuitry at the SW node (see figure below). PNG media_image2.png 450 798 media_image2.png Greyscale Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to GUSTAVO A ROSARIO-BENITEZ whose telephone number is (571)270-7888. The examiner can normally be reached M-F 9AM-5PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, MONICA LEWIS can be reached at 5712721838. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /GUSTAVO A ROSARIO-BENITEZ/Primary Examiner, Art Unit 2838
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Prosecution Timeline

Feb 17, 2023
Application Filed
Feb 19, 2025
Non-Final Rejection — §103
May 28, 2025
Response Filed
Jul 28, 2025
Final Rejection — §103
Sep 05, 2025
Response after Non-Final Action
Oct 20, 2025
Request for Continued Examination
Oct 29, 2025
Response after Non-Final Action
Nov 13, 2025
Non-Final Rejection — §103
Feb 17, 2026
Response Filed
Mar 06, 2026
Final Rejection — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

5-6
Expected OA Rounds
81%
Grant Probability
99%
With Interview (+25.3%)
2y 9m
Median Time to Grant
High
PTA Risk
Based on 733 resolved cases by this examiner. Grant probability derived from career allow rate.

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