Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Interpretation The following is a quotation of 35 U.S.C. 112(f): (f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof. The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph: An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof. This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are: the “core assignment optimizer” required in claim s 1-14 . Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof. If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. Claim Objections Claim 1 is objected to because of the following informalities: The recited “An apparatus” should be “An apparatus comprising . ” Appropriate correction is required. Claims 1-7 are objected to because of the following informalities: The recited “a core assignment optimizer to select” should be “a core assignment optimizer configured to select” (and similar variations). Appropriate correction is required. Claims 8-14 are objected to because of the following informalities: the “operating system” and “core assignment optimizer” should be “ configured ” to perform the recited operations. Appropriate correction is required. Claim 13 is objected to because of the following informalities: “that” in line 2 should be “ than . ” Appropriate correction is required. Claim 16 is objected to because of the following informalities: The recited “determining system configuration” should be “determining a system configuration . ” Appropriate correction is required. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b ) CONCLUSION.— The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the appl icant regards as his invention. Claim s 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Regarding claim 1, it recites “a power/performance profile;” however, it cannot be determined whether “power/performance” refers to “ power[ [/]] and performance” or “power[[/]] or performance,” therefore, the claim is ambiguous and the metes and bounds cannot be determined. Claims 2-20 require commensurate subject matter; therefore, they are indefinite for the same reason. Appropriate correction is required. Claim Rejections - 35 USC § 101 35 U.S.C. 101 reads as follows: Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title. Claims 1 -20 is/are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more. See table below for rationale of rejection. Claim 1: Treated Under: Explanation: An apparatus: Step 1 – MPEP § 2106.03 The claim falls into a statutory category of subject matter. a first core; a second core, Step 2B – MPEP § 2106.05( d ) The cores amount to well-understood routine convention activity (MPEP § 2106.05(d)) – See Specification at paragraph [0002], “ Today's computing systems may include an increasing number of devices, including devices with multiple processing units, input/output (I/O) devices, system on a chip (SoC) devices , multiple die packaged in a single device, and the like .” wherein a power/performance profile of the first core is different from a power/performance profile of the second core Step 2B – MPEP § 2106.05(d) The power/performance profile amounts to well-understood routine convention activity (MPEP § 2106.05(d)) – See Specification at paragraph [0002], “ Assigning workloads to processing engines is complex due to system power and performance constraints. Further complexity is introduced with the use of heterogeneous processing engines, each with their own power/performance profile .” and a core assignment optimizer to select one of the first core and the second core to perform a workload, wherein the core assignment optimizer to select the one of the first core and the second core based on one or more of user preferences, the power/performance profile of the first core, the power/performance profile of the second core, a system power budget, system thermal characteristics, and usage data of the first core and the second core. Step 2A Prong 1 – MPEP § 2106.04(a)(2) A human operator could mentally select a core to perform a workload based on viewing data on a terminal regarding preferences. Further, relying on “a core assignment optimizer” amounts to mere instructions to apply an exception. See MPEP § 2106.05(f). Regarding claim 2, it recites additional heuristic profiling , which can be performed in the human mind (mentally) by viewing dynamically updated data on a terminal and generating a mental opinion of the performance of the core . Accordingly, claim 2 is ineligible. Regarding claim 3, it further recites a storage unit to store profile information, which amounts to well-understood, routine, conventional activity . See MPEP § 2106.05( d ) (citing Versata Dev. Group, Inc. v. SAP Am., Inc. , 793 F.3d 1306, 1334, 115 USPQ2d 1681, 1701 (Fed. Cir. 2015); OIP Techs., 788 F.3d at 1363, 115 USPQ2d at 1092-93 ) . Accordingly, claim 3 is ineligible. Regarding claim 4, further refines the user preferences; however, a human operator can select cores based on any type of user preference by viewing data on a terminal . Accordingly, claim 4 is ineligible. Regarding claim 5, further recites selecting a core based on a higher usage level; however, a human operator can select a core based on a mentally determined higher usage level by viewing data on a terminal . Accordingly, claim 5 is ineligible. Regarding claim 6, is directed toward well-understood routine conventional activity, as indicated by the specification at paragraph [0003], where it is disclosed that “[m] any systems today allow a user to choose between performance and energy efficiency or even a balance between the two, without any understanding of the underlying hardware .” Accordingly, claim 6 is ineligible. Regarding claim 7, it is directed to an abstract idea because a human operator could mentally determine to exclude preferences that fall outside static system parameters. Accordingly, claim 7 is ineligible. Regarding claims 8-20 , they correspond to claims 1-7 . Therefore, they are rejected for the same reasons. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis ( i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness . Claim (s) 1 , 2, 5, 6, 8, 9, 12, 13, 15, 17, 19, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Singh (US 9,424,092) and further in view of Gorbatov (US 2014/0189301) . Regarding claim 1 , Singh teaches: An apparatus: a first core (col. 5:32-33, “ the processing system 104 is depicted as having performance oriented cores 202 ”) ; a second core (col. 5:33, “ and power efficient cores 204 ”) , wherein a power/performance profile of the first core is different from a power/performance profile of the second core (col. 5:34-37, “ The performance oriented cores 202 are representative of cores designed for high performance and the power efficient cores 204 are representative of cores designed to consume low power ”) ; and a core assignment optimizer (col. 6:20-22, “ the thread scheduler module 128 represents functionality operable to manage allocation of the processing workload across available processing resources ”) to select one of the first core and the second core to perform a workload (col. 6:30-33, “ The thread scheduler module 128 may be configured to assign and apply thread policies 208 to allocate work among a subset of heterogeneous cores made available by the power manager module 126 ”) , wherein the core assignment optimizer to select the one of the first core and the second core based on one or more of user preferences (col. 10:64-65, “ cores associated with a thread's assigned preferences may be selected first ”) , the power/performance profile of the first core (col. 6:39-43, “ The thread policies are configured to account for asymmetric properties of the heterogeneous cores, such as different performance capabilities, processing efficiencies, and power usage characteristics associated with different types of cores ”) , the power/performance profile of the second core (col. 6:39-43, “ The thread policies are configured to account for asymmetric properties of the heterogeneous cores, such as different performance capabilities, processing efficiencies, and power usage characteristics associated with different types of cores ”) , a system power budget (col. 7:39-42, “ in a low battery state one or more performance oriented cores may be parked in an idle state to conserve power and/or one or more power efficient cores may be unparked into active states to service the workload ”) , system thermal characteristics (col. 7:43-44, “ any type of core that reaches a temperature threshold may be parked to avoid overheating and damage ”) , and usage data of the first core and the second core ( col. 10:1-3, “ the thread scheduler module 128 may operate to evaluate priority, core utilizations, workload and other considerations to place the thread ” ) . Singh does not teach as clearly as Gorbatov teaches : a system power budget ( ¶ 39, “ The available energy/thermal budget evaluation logic is operable to evaluate available energy and/or thermal budgets of the processor and to determine to allow the migration if the migration fits within the available energy and/or thermal budgets ” ) . It would have been obvious to a person having ordinary skill in the art, at the effective filing date of the invention, to have applied the known technique of a system power budget , as taught by Gorbatov , in the same way to the core assignment optimizer , as taught by Singh . Both inventions are in the field of thermal/power management in core assignment , and combining them would have predictably resulted in an apparatus to “ harness the benefits provided by the heterogeneity of the cores ,” as indicated by Gorbatov ( ¶ 5 ). Regarding claim 2, Singh teaches: The apparatus of claim 1, the core assignment optimizer further to perform heuristic profiling of the first core and the second core (col. 7:14-16, “ An operational context for a processing system having heterogeneous cores including power efficient cores and performance oriented cores is periodically analyzed (block 302) ;” the heuristic profiling is disclosed as dynamic profiling , which Singh teaches by periodically analyzing operational context which can include thermal conditions) . Regarding claim 5, Singh teaches: The apparatus of claim 1, wherein the core assignment optimizer to select the first core if the second core has a higher usage level than the first core ( col. 2:43-46, “ power usage may be optimized by intelligently switching between different cores, using power efficient cores more often, and/or placing unused or underutilized cores into idle states whenever possible ” and col. 10:63-65, “ unparked and idle cores may be targeted over parked or active cores and cores associated with a thread's assigned preferences may be selected first ”) . Regarding claim 6, Singh teaches: The apparatus of claim 1, wherein the first core has higher performance characteristics than the second core and wherein the second core has lower power usage characteristics than the first core (col. 2:29-31, “ heterogeneous cores including power efficient cores and performance oriented cores ”) . Claims 8, 9, 12, 13, 15, 17, and 19 recite commensurate subject matter as claims 1, 2, 5, and 6. Therefore, they are rejected for the same reasons. Regarding claim 20, Singh teaches: The method of claim 19, wherein the system conditions monitored include one of current thermal conditions (col. 4:13-16, “ This may involve analyzing factors including . . . thermal conditions ”) , current resource availability (col. 7:21-25, “ the operational context may reflect . . . power availability (e.g., battery level, power supply connection, etc.) ”) , and usage statistics of the first core and the second core (col. 10:1-3, “ the thread scheduler module 128 may operate to evaluate priority, core utilizations, workload and other considerations to place the thread ”) . Claim (s) 3 , 10, and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Singh and Gorbatov , as applied above, and further in view of Phuong (US 2015/0301914) . Regarding claim 3, Singh and Gorbatov do not teach; however, Phuong teaches : at least one storage unit to store the power/performance profile of the first core and the power/performance profile of the second core (“ an apparatus is provided comprising: memory configured to store a power profile and a power budget ”) . It would have been obvious to a person having ordinary skill in the art, at the effective filing date of the invention, to have applied the known technique of at least one storage unit to store the power/performance profile of the first core and the power/performance profile of the second core , as taught by Phuong, in the same way to power/performance profile , as taught by Singh and Gorbatov . Both inventions are in the field of power and performance management of computing systems, and combining them would have predictably resulted in “ managing power consumption during a power-on-self-test (POST) sequence ,” as indicated by Phuong (¶ 1). Claim 10 recites commensurate subject matter as claim 3. Therefore, it is rejected for the same reason. Regarding claim 16, Gorbatov teaches: The method of claim 15, wherein the determining and communicating system capabilities includes determining system configuration including a total number of cores and the type of cores (¶ 21, “ numerous specific details are set forth (e.g., specific types and numbers of heterogeneous compute elements, logic implementations and microarchitectural details, logic partitioning/integration details, power/thermal budget criteria, sequences of operations, types and interrelationships of system components, and the like) ”) . Singh and Gorbatov do not teach; however, Phuong teaches: storing the system configuration (“ an apparatus is provided comprising: memory configured to store a power profile and a power budget ”) . It would have been obvious to a person having ordinary skill in the art, at the effective filing date of the invention, to have applied the known technique of storing the system configuration , as taught by Phuong, in the same way to power/performance profile, as taught by Singh and Gorbatov . Both inventions are in the field of power and performance management of computing systems, and combining them would have predictably resulted in “ managing power consumption during a power-on-self-test (POST) sequence ,” as indicated by Phuong (¶ 1). Claim (s) 4 , 11, and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Singh and Gorbatov , as applied above, and further in view of Hicok (US 2014/0181501) . Regarding claim 4, Singh and Gorbatov do not teach; however, Hicok teaches: the user preferences include a voltage and speed setting of the first core to be set by a user (¶ 23, “ Each core 140 may operate within a corresponding voltage-frequency (VF) domain, distinct from other VF domains. For example, circuitry associated with core 140(0) may operate on a first voltage and first operating frequency associated with VF domain 210(0), while circuits associated with core 140(N) may operate on a second voltage and a second frequency associated with VF domain 210(N) ”) . It would have been obvious to a person having ordinary skill in the art, at the effective filing date of the invention, to have applied the known technique of the user preferences include a voltage and speed setting of the first core to be set by a user , as taught by Hicok , in the same way to the user preferences, as taught by Singh and Gorbatov . Both inventions are in the field of power and performance management of computing systems, and combining them would have predictably resulted in “ a heterogeneous multiprocessor design for power-efficient and area-efficient computing ,” as indicated by Hicok (¶ 2). Claim(s) 11 and 17 recite(s) commensurate subject matter as claim(s) 4. Therefore, it/they is/are rejected for the same reasons. Claim (s) 7 and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Singh and Gorbatov , as applied above, and further in view of Zagacki (US 7,308,590) . Regarding claim 7, Singh and Gorbatov do not teach; however, Zagacki teaches: the core assignment optimizer to exclude the user preferences if the user preferences are outside static system parameters (col. 3:20-26, “ at operation 201, it is determined whether a command, such as one that writes a value to an MSR register, is intended for a machine register controlling the operating voltage and/or core/bus frequency ratio of the processor. If so, it is then determined whether the core/bus ratio requested is within the allowable range for the processor at operation 205. If not, a fault condition is indicated at operation 207 ”) . It would have been obvious to a person having ordinary skill in the art, at the effective filing date of the invention, to have applied the known technique of the core assignment optimizer to exclude the user preferences if the user preferences are outside static system parameters , as taught by Zagacki , in the same way to the core assignment optimizer, as taught by Singh and Gorbatov . Both inventions are in the field of power and performance management of computing systems, and combining them would have predictably resulted in “ dynamically controlling an operating voltage of a microprocessor based on the processor core/bus frequency ,” as indicated by Zagacki (col. 1:8-10). Claim(s) 14 recite(s) commensurate subject matter as claim(s) 7. Therefore, it/they is/are rejected for the same reasons. Claim (s) 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Singh and Gorbatov , as applied above, and further in view of Bertran (US 10,599,432 ) . Regarding claim 18, Singh and Gorbatov do not teach; however, Bertran teaches: determining a power and performance profile of the first core based on varying workloads and operating conditions (col. 7 : 2-8 , “ the micro-benchmark generator 116 of FIG. 1 can use the instrumentation 134 of FIG. 1 to monitor the SMT processor 202 of FIG. 2 while executing one or more threads 210 based on the instruction sequences 126. The desired stressmark type of the stressmark types 124 may be one of: a power metric, a noise metric, an energy metric, a speed metric ”) . It would have been obvious to a person having ordinary skill in the art, at the effective filing date of the invention, to have applied the known technique of determining a power and performance profile of the first core based on varying workloads and operating conditions , as taught by Bertran , in the same way to the static core profiling, as taught by Singh and Gorbatov . Both inventions are in the field of power and performance management of computing systems, and combining them would have predictably resulted in “ dynamically controlling an operating voltage of a microprocessor based on the processor core/bus frequency ,” as indicated by Bertran (col. 1:8-10). Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Andrus (US 10,417,054) discloses “ scheduling threads on a processor that has at least two different core types, such as an asymmetric multiprocessing system ” (abstract), which relates to the disclosed heterogenous core scheduling method. Naveh (US 10,185,566) discloses “[a] task controller, which may be included in or coupled to the multicore processor, can cause dynamic migration of a first process scheduled by the OS to the first core to the second core transparently to the OS ” (abstract), which relates to the disclosed heterogenous core scheduling method. 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