DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
Claims 1-20 are pending, of which all pending claims are rejected.
Specification
Applicant is reminded of the proper content of an abstract of the disclosure.
A patent abstract is a concise statement of the technical disclosure of the patent and should include that which is new in the art to which the invention pertains. The abstract should not refer to purported merits or speculative applications of the invention and should not compare the invention with the prior art.
If the patent is of a basic nature, the entire technical disclosure may be new in the art, and the abstract should be directed to the entire disclosure. If the patent is in the nature of an improvement in an old apparatus, process, product, or composition, the abstract should include the technical disclosure of the improvement. The abstract should also mention by way of example any preferred modifications or alternatives.
Where applicable, the abstract should include the following: (1) if a machine or apparatus, its organization and operation; (2) if an article, its method of making; (3) if a chemical compound, its identity and use; (4) if a mixture, its ingredients; (5) if a process, the steps.
Extensive mechanical and design details of an apparatus should not be included in the abstract. The abstract should be in narrative form and generally limited to a single paragraph within the range of 50 to 150 words in length.
See MPEP § 608.01(b) for guidelines for the preparation of patent abstracts.
The abstract of the disclosure is objected to because it is too short. The abstract should be limited to a single paragraph on a separate sheet within the range of 50 to 150 words. Correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 1 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite as the recited limitation “generating multiple execution variants of the quantum circuit by applying a first symmetry of one or more symmetries to the quantum circuit” is unclear because the expression "applying a first symmetry of one or more symmetries" does not have a well-recognized unambiguous meaning to a skilled person in the field and because the claim wording does not unambiguously express what is intended, e.g. what entity contains the symmetry (circuit, device, problem ... ), how they are represented, etc. It would appear that this feature could be clarified by including the additional features of dependent claim 3 which define it is a set of symmetries of the quantum computation, and claim 10, which lists possible symmetries, including, e.g. qubit assignments (i.e. mapping of logical qubits to physical qubits); gate decompositions etc. Claims 11 and 16 are also rejected for the same reasons as claim 1.
Claims 3, 4 and 13 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out the feature "selecting one or more symmetry". The claims attempt to define the subject-matter in terms of the result to be achieved, which merely amounts to a statement of the underlying problem, without providing the technical features necessary for achieving this result. "Selecting one or more symmetry" is the result, but does not specify how, or by which entity (i.e. is it the computer that selects, or the user?) the symmetry is selected. Especially, in claim 4, it is unclear how the symmetries are picked such that they reduce error correlation.
Claims 5, 14 and 18 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out the feature "output probability distribution of the computation". It is not clear or unambiguous from the claim wording alone in how the "output probability distribution of the computation" is determined, as this appears to be the final result that one would like to obtain; but that result is not available yet. Additionally, it is unclear how the output probability is used to select an aggregation process.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2, 11-12 and 16-17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tannu et al., "Ensemble of Diverse Mappings: Improving Reliability of Quantum Computers by Orchestrating Dissimilar Mistakes", PROCEEDINGS OF THE 52ND ANNUAL IEEE/ACM INTERNATIONAL SYMPOSIUM ON MICROARCHITECTURE, (MICRO-52), October 12, 2019, pp. 253-265. (hereinafter Tannu).
Regarding claim 1, Tannu teaches, a computer-implemented method (Tannu: ‘ [Figure. 5] & [section 5.2]) comprising, generating a quantum circuit by compiling a quantum program corresponding to a defined quantum computation (Tannu: "In the first step, a compiler generates the best initial mapping and SWAP schedule for a given input program using coupling map (network topology) of a quantum computer and the error rate characterization data” [section 5.2]); generating multiple execution variants of the quantum circuit by applying a first symmetry of one or more symmetries to the quantum circuit; causing quantum hardware (Tannu: ‘IBM Quantum computer with fourteen qubits [section 4.2]) to execute each one of the multiple execution variants; receiving multiple measurement datasets indicative of computation outputs for respective ones of the multiple execution variants (Tannu: "In the second step, we use the initial mapping, and find all the isomorphic sub-graphs for the given quantum computer, and rank the sub-graphs as per the Estimated Success Probability (ESP). EDM picks the top "k" sub-graphs based on the ESP. In the third step, we re-compile the program by using the ensemble of initial mappings (M1, M2, Mn) to produce an ensemble of executable (E1, E2, ... , En) , and run all executable on a NISQ machine as shown in the Figure 5, to produce set of output probability distributions (O1,O2, ... On)”; the different mappings are considered. a first symmetry [section 5.2]); and determining a result of the defined quantum computation by aggregating the multiple measurement datasets (Tannu: “Finally, we merge the probability distributions of all the members in the Ensemble to generate the final result.” [section 5.2]).
Regarding claim 2, Tannu teaches, the computer-implemented method of claim 1, further comprising causing a computing device to provide the result (Tannu: ‘Figure 2(b), last step; also implied in the graphs made of the experiment results in e.g. Figures. 9 and 11, which are necessarily based on the provided result.’ [Figure 2(b)]).
Regarding claim 11, Tannu teaches, a computing system (Tannu: ‘quantum computer [section 4.2]) comprising: at least one processor; at least one memory devices storing processor-executable instructions that, in response to being executed by the at least one processor (Tannu: ‘quantum computer includes processor and memory [section 4.2]), cause the computing system at least to: generate a quantum circuit by compiling a quantum program corresponding to a defined quantum computation (Tannu: "In the first step, a compiler generates the best initial mapping and SWAP schedule for a given input program using coupling map (network topology) of a quantum computer and the error rate characterization data” [section 5.2]); generate multiple execution variants of the quantum circuit by applying a first symmetry of one or more symmetries to the quantum circuit; cause quantum hardware (Tannu: ‘IBM Quantum computer with fourteen qubits [section 4.2]) to execute each one of the multiple execution variants; receive multiple measurement datasets indicative of computation outputs for respective ones of the multiple circuit variants (Tannu: "In the second step, we use the initial mapping, and find all the isomorphic sub-graphs for the given quantum computer, and rank the sub-graphs as per the Estimated Success Probability (ESP). EDM picks the top "k" sub-graphs based on the ESP. In the third step, we re-compile the program by using the ensemble of initial mappings (M1, M2, Mn) to produce an ensemble of executable (E1, E2, ... , En) , and run all executable on a NISQ machine as shown in the Figure 5, to produce set of output probability distributions (O1,O2, ... On)”; the different mappings are considered. a first symmetry [section 5.2]); and determine a result of the defined quantum computation by aggregating the multiple measurement datasets (Tannu: “Finally, we merge the probability distributions of all the members in the Ensemble to generate the final result.” [section 5.2]).
Regarding claim 12, Tannu teaches, the computing system of claim 11, the at least one memory devices storing further processor-executable instructions that, in response to being executed, further cause the at least one processor to cause a computing device to provide the result (Tannu: ‘Figure 2(b), last step; also implied in the graphs made of the experiment results in e.g. Figures. 9 and 11, which are necessarily based on the provided result.’ [Figure 2(b)]).
Regarding claim 16, Tannu teaches, a quantum information processing (QIP) system (Tannu: ‘quantum computer [section 4.2]) comprising: at least one processor; and at least one memory device storing processor-executable instructions (Tannu: ‘quantum computer includes processor and memory [section 4.2]) that, in response to being executed by the at least one processor, cause the QIP system at least to: generate a quantum circuit by compiling a quantum program corresponding to a defined quantum computation (Tannu: "In the first step, a compiler generates the best initial mapping and SWAP schedule for a given input program using coupling map (network topology) of a quantum computer and the error rate characterization data” [section 5.2]); generate multiple execution variants of the quantum circuit by applying a first symmetry of one or more symmetries to the quantum circuit; cause quantum hardware (Tannu: ‘IBM Quantum computer with fourteen qubits [section 4.2]) to execute each one of the multiple execution variants; receive multiple measurement datasets indicative of computation outputs for respective ones of the multiple circuit variants (Tannu: "In the second step, we use the initial mapping, and find all the isomorphic sub-graphs for the given quantum computer, and rank the sub-graphs as per the Estimated Success Probability (ESP). EDM picks the top "k" sub-graphs based on the ESP. In the third step, we re-compile the program by using the ensemble of initial mappings (M1, M2, Mn) to produce an ensemble of executable (E1, E2, ... , En) , and run all executable on a NISQ machine as shown in the Figure 5, to produce set of output probability distributions (O1,O2, ... On)”; the different mappings are considered. a first symmetry [section 5.2]); and determine a result of the defined quantum computation by aggregating the multiple measurement datasets (Tannu: “Finally, we merge the probability distributions of all the members in the Ensemble to generate the final result.” [section 5.2]).
Regarding claim 17, Tannu teaches, the QIP system of claim 16, the at least one memory devices storing further processor- executable instructions that, in response to being executed, further cause the at least one processor to cause a computing device to provide the result (Tannu: ‘Figure 2(b), last step; also implied in the graphs made of the experiment results in e.g. Figures. 9 and 11, which are necessarily based on the provided result.’ [Figure 2(b)]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 3-4, 10, 13 are rejected under 35 U.S.C. 103 as being unpatentable over Tannu et al., ("Ensemble of Diverse Mappings: Improving Reliability of Quantum Computers by Orchestrating Dissimilar Mistakes", PROCEEDINGS OF THE 52ND ANNUAL IEEE/ACM INTERNATIONAL SYMPOSIUM ON MICROARCHITECTURE, (MICRO-52), October 12, 2019, pp. 253-265) in view of McClean et al. (US 2022/0414519 A1), (hereinafter Tannu-McClean).
Regarding claim 3,Tannu does not explicitly disclose, the computer-implemented method of claim 1, further comprising selecting the one or more symmetries from a set of computation-specific symmetries corresponding to the defined quantum computation.
However, McClean teaches in an analogous art, ‘selecting from one or more symmetries from a set for a circuit’ [0018] … each quantum circuit can include a plurality of quantum gates, and each of the quantum circuits can be an equivalent logical operation as each of the other quantum circuits. Each of the quantum circuits can be implemented by a different sequence of quantum gates. By selecting logically equivalent quantum circuits implemented using different sequences of quantum gates, the noise observed in the quantum circuits during measurement can be randomized. [0021] For example, in some implementations, the one or more circuit gauges implemented by the quantum system can include one or more randomized circuit gauges. For example, the one or more randomized circuit gauges can be implemented by injecting one or more random pairs of Pauli operators or single qubit gates into a quantum circuit during free space or combined with already present gates in a quantum circuit (e.g., such as idle time where quantum circuits are not acting on qubits during moments of gates). The random pair of Pauli operators or other single qubit gates can be equivalent to the identity (e.g., they are self-inverse), and can be commuted through adjacent gates until the free space is filled. By commuting the random pair of Pauli operators through a quantum gate (or gates), an equivalent logical operation can be performed but implemented in a different Gauge, such as a Pauli Gauge. The Pauli operators can be commuted through either a subset or all quantum gates in a quantum circuit (see also Fig.2).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Tannu’s teachings of ‘qubit assignment’ with McClean’s teaching of ‘selecting from one or more symmetries from a set for a circuit’ to provide a method that can implement a plurality of quantum circuits; obtaining a plurality of measurements performed for each of the quantum circuits; determining an estimated average value of an observable of interest for the quantum circuits based on the plurality of measurements. By doing so, each of the plurality of quantum circuits can be implemented by a different sequence of quantum gates as compared to each of the other quantum circuits in the plurality to thereby implement one or more circuit gauges and can be an equivalent logical operation as each of the other quantum circuits in the plurality.
Regarding claim 4, Tannu-McClean teaches, the computer-implemented method of claim 3, wherein the selecting comprises selecting a first symmetry and a second symmetry from the set of computation-specific symmetries, wherein the first symmetry and the second symmetry reduce error correlation between respective resulting execution variants (McClean: ‘selecting from one or more symmetries from a set for a circuit’ [0018, 0021] & [Fig.2]).
Regarding claim 10, Tannu-McClean teaches, the computer-implemented method of claim 1, wherein the set of computation-specific symmetries comprises at least one of a qubit assignment, gate decomposition, a permutation of commuting gates, an addition of a gate that preserves a defined state, or a change of one or more gates and measurements compensated by one or more changes in postprocessing (McClean: ‘selecting from one or more symmetries from a set for a circuit’ [0018, 0021] & [Fig.2]).
Regarding claim 13, Tannu-McClean teaches, the computing system of claim 11, the at least one memory devices storing further processor-executable instructions that, in response to being executed, further cause the at least one processor to select the one or more symmetries from a set of computation- specific symmetries corresponding to the defined quantum computation (McClean: ‘selecting from one or more symmetries from a set for a circuit’ [0018, 0021] & [Fig.2]).
Claims 5-9, 14-15 and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Tannu et al., ("Ensemble of Diverse Mappings: Improving Reliability of Quantum Computers by Orchestrating Dissimilar Mistakes", PROCEEDINGS OF THE 52ND ANNUAL IEEE/ACM INTERNATIONAL SYMPOSIUM ON MICROARCHITECTURE, (MICRO-52), October 12, 2019, pp. 253-265) in view of Macaluso et al., ("QUANTUM ENSEMBLE FOR CLASSIFICATION A PREPRINT", July 2, 2020, pp. 1-14, XP093164282, , (hereinafter Tannu-Macaluso).
Regarding claim 5, Tannu does not explicitly disclose, the computer-implemented method of claim 1, wherein the aggregating the multiple measurement datasets comprises, selecting, based on an output probability distribution corresponding to the defined computation, an aggregation process to combine the multiple measurement datasets; and applying the aggregation process to the multiple measurement datasets.
However, Macaluso teaches in an analogous art, ‘aggregation strategy and theoretical performance; majority voting’, “When considering classical implementations of ensemble algorithms, it is possible to distinguish two broad families of methods based on the strategy adopted to aggregate the predictions of the individual models. On one hand, the most popular technique used in ensemble classification is majority voting, where each classifier votes for a target class and the most frequent is then selected. On the other hand, an alternative strategy is given by simple averaging. In this case, the target probability distribution provided by individual models is considered, and the final prediction is computed as follows:….” [section 3.2].
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Tannu’s teachings of ‘qubit assignment’ with Macaluso’s teaching of ‘aggregation strategy and theoretical performance and majority voting’ to provide methods and techniques for ensemble classification. Among the multiple alternatives to build a classifier, a well-known approach is ensemble methods, where a large number of hypotheses is combined by averaging or voting rules to classify new examples. By doing so, despite the absence of a unified theory, there are many theoretical reasons for combining multiple learners, e.g. reducing the prediction error by decreasing the uncertainty on the estimates, as well as empirical evidence of the effectiveness of this approach
Regarding claim 6, Tannu-Macaluso teaches, the computer-implemented method of claim 5, wherein the aggregation process comprises componentwise averaging (Macaluso: aggregation strategy and theoretical performance; majority voting’ [section 3.2]).
Regarding claim 7, Tannu-Macaluso teaches, the computer-implemented method of claim 6, wherein the multiple measurement datasets define multiple sequences of bitstrings, and wherein applying the componentwise averaging comprises determining, over the multiple sequences of bitstrings, an average number of occurrences for each bitstring in the multiple sequence of bitstrings (Macaluso: aggregation strategy and theoretical performance; majority voting’ [section 3.2]).
Regarding claim 8, Tannu-Macaluso teaches, the computer-implemented method of claim 5, wherein the aggregation process comprises plurality voting (Macaluso: aggregation strategy and theoretical performance; majority voting’ [section 3.2]).
Regarding claim 9, Tannu-Macaluso teaches, the computer-implemented method of claim 8, wherein the multiple measurement datasets define multiple sequences of bitstrings, and wherein applying the plurality voting comprises determining, over the multiple sequences of bitstrings, a particular bitstring exhibiting a number of occurrences that exceeds a defined threshold number (Macaluso: aggregation strategy and theoretical performance; majority voting’ [section 3.2]).
Regarding claim 14, Tannu-Macaluso teaches, the computing system of claim 11, wherein aggregating the multiple measurement datasets comprises, selecting, based on an output probability distribution corresponding to the defined computation, an aggregation process to combine the multiple measurement datasets; and applying the aggregation process to the multiple measurement datasets (Macaluso: aggregation strategy and theoretical performance; majority voting’ [section 3.2]).
Regarding claim 15, Tannu-Macaluso teaches, the computing system of claim 14, wherein the aggregation process comprises one of componentwise averaging or plurality voting (Macaluso: aggregation strategy and theoretical performance; majority voting’ [section 3.2]).
Regarding claim 18, Tannu-Macaluso teaches, the computing system of claim 16, wherein aggregating the multiple measurement datasets comprises, selecting, based on an output probability distribution corresponding to the defined computation, an aggregation process to combine the multiple measurement datasets, the aggregation process one of a linear aggregation process or a non- linear aggregation process; applying the aggregation process to the multiple measurement datasets (Macaluso: aggregation strategy and theoretical performance; majority voting’ [section 3.2]).
Regarding claim 19, Tannu-Macaluso teaches, the QIP system of claim 18, wherein the quantum hardware comprises multiple trapped- atom qubits individually addressable by a continuous-wave laser beam (Tannu: “ion-trap machine and superconducting machine” [sections 2.3 & 4.3])
Regarding claim 20, Tannu-Macaluso teaches, the QIP system of claim 18, wherein the quantum hardware comprises multiple superconducting qubits individually addressable by microwave electromagnetic radiation (Tannu: “superconducting qubits” [section 2.3])
Citation of Pertinent Prior Art
It is noted that any citations to specific, pages, columns, lines, or figures in the prior art references and any interpretation of the reference should not be considered to be limiting in any way. A reference is relevant for all it contains and may be relied upon for all that it would have reasonably suggested to one having ordinary skill in the art. See MPEP 2123.
Conclusion
The following prior arts made of record, listed on form PTO-892, and not relied upon, if any, are considered pertinent to applicant's disclosure:
McClean et al. (US 2022/0029639 A1) teaches, [0007] In some implementations measuring a projective correction of a physical observable over an output quantum state of the quantum computation using the determined set of symmetry operators comprises: selecting one or more pairs of operators, wherein each pair comprises i) a respective component of the physical observable, and ii) a respective symmetry operator from the determined set of symmetry operators; for each selected pair of operators: performing the quantum computation on an initial quantum state to obtain the output quantum state, and measuring the selected pair of operators over the output quantum state to obtain a respective measurement result.
When amending the claims, Applicants are respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ENAMUL MD KABIR whose telephone number is (571)270-7256. The examiner can normally be reached on 10:00-6:30 pm.
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/ENAMUL M KABIR/
Examiner, Art Unit 2112
/ALBERT DECADY/Supervisory Patent Examiner, Art Unit 2112