DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 03/10/2026 has been entered.
Response to Amendment
Applicant’s amendment dated 03/10/2026, in which claim 1 was amended, claim 7 was cancelled, claims 8-9 were added, has been entered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Nishida et al. (US Pub. 20150371931) in view of Kim et al. (US Pat. 10304788), Shirasawa et al. (US Pub. 20050199999) and Koyanagi (US Pub. 20190164858).
Regarding claims 1, 4-5, and 8, Nishida et al. discloses in Fig. 1b, paragraph [0057]-[0068] a semiconductor module comprising:
a mounting substrate [12];
a semiconductor element [11] mounted on the mounting substrate [12];
a housing [7] configured to house the semiconductor element [11];
a sealing member [8] filled in a space inside the housing [7] to seal the semiconductor element [1];
a wiring member [13] electrically connected to the semiconductor element [11], wherein the wiring member [3] includes:
a first portion;
a second portion;
wherein: the wiring member [13] with a first end and a second end opposite to the first end includes:
the first portion and the second portion; and
a third portion,
the first portion includes the first end of the wiring member [13], the third portion includes the second end of the wiring member [13],
the second portion is a portion between the first portion and the third portion,
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Nishida et al. fails to disclose
a first sealing layer filled in a space inside the housing to seal the semiconductor element;
a second sealing layer of a resin material softer than the first sealing layer and layered on the first sealing layer; and
wherein the wiring member includes
the first portion covered with the first sealing layer; and
the second portion covered with the second sealing layer
the first portion and the third portion are covered with the first sealing layer, and the second portion is covered with the second sealing layer;
wherein a thickness of the first sealing layer is greater than a thickness of the second sealing layer;
the sealing member comprising layers of the first sealing layer and the second sealing layer.
Kim et al. discloses in Fig. 1, columns 4-7
a first sealing layer [110] filled in a space inside the housing [108] to seal the semiconductor element [104];
a second sealing layer [112] of a resin material softer than the first sealing layer [110] and layered on the first sealing layer [110]; and
wherein the wiring member [114] includes:
a first portion [116] covered with the first sealing layer [110]; and
a second portion [114] covered with the second sealing layer [112].
the first portion [116] and the third portion [118] are covered with the first sealing layer [110], and the second portion [114] is covered with the second sealing layer [112].
wherein a thickness of the first sealing layer [110] is greater than a thickness of the second sealing layer [112];
the sealing member [110 and 112] comprising layers of the first sealing layer [110] and the second sealing layer [112].
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Kim et al. into the method of Nishida et al. to include a first sealing layer filled in a space inside the housing to seal the semiconductor element; a second sealing layer of a resin material softer than the first sealing layer and layered on the first sealing layer; and wherein the wiring member includes the first portion covered with the first sealing layer; and the second portion covered with the second sealing layer; the first portion and the third portion are covered with the first sealing layer, and the second portion is covered with the second sealing layer; wherein a thickness of the first sealing layer is greater than a thickness of the second sealing layer; the sealing member comprising layers of the first sealing layer and the second sealing layer. The ordinary artisan would have been motivated to modify Nishida et al. in the above manner for the purpose of improving the reliability and lifetime of the device modules while maintaining the endurance of the substrate under a short circuit condition [column 4, lines 1-12 of Kim et al.]. Further, it would have been obvious to try one of the known methods with a reasonable expectation of success. KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Nishida et al. and Kim et al. fails to disclose
an insulating protection member configured to cover a top surface of the second sealing layer;
wherein the insulating protection member being bonded to the sealing member using the second sealing layer as an adhesive, and
the second sealing layer is entirely interposed between the first sealing layer and the insulating protection member;
wherein the insulating protection member is a plate-like member.
Shirasawa et al. discloses in Fig. 1, paragraph [0029]
a protection member [18] configured to cover a top surface of the second sealing layer [17];
wherein the protection member [18] being bonded to the sealing member [16 and 17] using the second sealing layer [17] as an adhesive, and
the second sealing layer [17] is entirely interposed between the first sealing layer [16] and the protection member [18];
wherein the protection member [18] is a plate-like member.
Koyanagi discloses in Fig. 1, paragraph [0016]
a protection member [34] is an insulating protection member [“The material of the lid 34 …is engineering plastics such, for example, as PPS resin”];
wherein the insulating protection member [34] is a plate-like member.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Shirasawa et al. and Koyanagi into the method of Nishida et al. and Kim et al. to include an insulating protection member configured to cover a top surface of the second sealing layer; wherein the insulating protection member being bonded to the sealing member using the second sealing layer as an adhesive, and the second sealing layer is entirely interposed between the first sealing layer and the insulating protection member; wherein the insulating protection member is a plate-like member. The ordinary artisan would have been motivated to modify Nishida et al. and Kim et al. in the above manner for the purpose of preventing infiltration of moisture and other matter into the resin-sealed electronic control device and improving the reliability of the resin-sealed electronic control device. Further, it would have been obvious to try one of the known methods with a reasonable expectation of success. KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Regarding claims 2-3, Nishida et al. discloses in Fig. 1b
a connection terminal [15] mounted to the housing [7], wherein the wiring member [13] includes a first wiring member that electrically connects the semiconductor element [11] and the connection terminal [15];
wherein: the semiconductor element [11] includes a first semiconductor element [11 left] and a second semiconductor element [11 right], and the wiring member [13] includes a second wiring member configured to electrically connect the first semiconductor element [11 left] and the second semiconductor element [11 right].
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Claims 1-4, 6, 8 are rejected under 35 U.S.C. 103 as being unpatentable over Nishida et al. (US Pub. 20150371931) in view of Hartung et al. (US Pub. 20180033711) Shirasawa et al. (US Pub. 20050199999) and Koyanagi (US Pub. 20190164858).
Regarding claims 1, 4, 6, 8, Nishida et al. discloses in Fig. 1b, paragraph [0057]-[0068] a semiconductor module comprising:
a mounting substrate [12];
a semiconductor element [11] mounted on the mounting substrate [12];
a housing [7] configured to house the semiconductor element [11];
a sealing member [8] filled in a space inside the housing [7] to seal the semiconductor element [1];
a wiring member [13] electrically connected to the semiconductor element [11], wherein the wiring member [3] includes:
a first portion;
a second portion;
wherein: the wiring member [13] with a first end and a second end opposite to the first end includes:
the first portion and the second portion; and
a third portion,
the first portion includes the first end of the wiring member [13], the third portion includes the second end of the wiring member [13],
the second portion is a portion between the first portion and the third portion,
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Nishida et al. fails to disclose
a first sealing layer filled in a space inside the housing to seal the semiconductor element;
a second sealing layer of a resin material softer than the first sealing layer and layered on the first sealing layer; and
wherein the wiring member includes
the first portion covered with the first sealing layer; and
the second portion covered with the second sealing layer
the first portion and the third portion are covered with the first sealing layer, and the second portion is covered with the second sealing layer;
wherein a thickness of the first sealing layer is less than a thickness of the second sealing layer;
the sealing member comprising layers of the first sealing layer and the second sealing layer.
Hartung et al. discloses in Fig. 1C, paragraph [0012]-[0053]
a first sealing layer [51] filled in a space inside the housing [6] to seal the semiconductor element [104];
a second sealing layer [52] of a resin material softer than the first sealing layer [51] and layered on the first sealing layer [51][paragraph [0049]]; and
wherein the wiring member [3] includes:
a first portion covered with the first sealing layer [51]; and
a second portion covered with the second sealing layer [52];
the first portion and the third portion are covered with the first sealing layer [51], and the second portion is covered with the second sealing layer [52];
wherein a thickness of the first sealing layer [51] is less than a thickness of the second sealing layer [52];
the sealing member [51 and 52] comprising layers of the first sealing layer [51] and the second sealing layer [52].
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Hartung et al. into the method of Nishida et al. to include a first sealing layer filled in a space inside the housing to seal the semiconductor element; a second sealing layer of a resin material softer than the first sealing layer and layered on the first sealing layer; and wherein the wiring member includes the first portion covered with the first sealing layer; and the second portion covered with the second sealing layer; the first portion and the third portion are covered with the first sealing layer, and the second portion is covered with the second sealing layer; wherein a thickness of the first sealing layer is less than a thickness of the second sealing layer; the sealing member comprising layers of the first sealing layer and the second sealing layer. The ordinary artisan would have been motivated to modify Nishida et al. in the above manner for the purpose of maintaining high mechanical strength, good adhesion and high dielectric strength while dielectrically isolating and encapsulating the interior of the module housing above the power semiconductor chips [paragraph [0044]-[0049] of Hartung et al.]. Further, it would have been obvious to try one of the known methods with a reasonable expectation of success. KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Nishida et al. and Hartung et al. fails to disclose
an insulating protection member configured to cover a top surface of the second sealing layer;
wherein the insulating protection member being bonded to the sealing member using the second sealing layer as an adhesive, and
the second sealing layer is entirely interposed between the first sealing layer and the insulating protection member.
wherein the insulating protection member is a plate-like member.
Shirasawa et al. discloses in Fig. 1, paragraph [0029]
a protection member [18] configured to cover a top surface of the second sealing layer [17];
wherein the protection member [18] being bonded to the sealing member [16 and 17] using the second sealing layer [17] as an adhesive, and
the second sealing layer [17] is entirely interposed between the first sealing layer [16] and the protection member [18];
wherein the protection member [18] is a plate-like member.
Koyanagi discloses in Fig. 1, paragraph [0016]
a protection member [34] is an insulating protection member [“The material of the lid 34 …is engineering plastics such, for example, as PPS resin”];
wherein the insulating protection member [34] is a plate-like member.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Shirasawa et al. and Koyanagi into the method of Nishida et al. and Hartung et al. to include an insulating protection member configured to cover a top surface of the second sealing layer; wherein the insulating protection member being bonded to the sealing member using the second sealing layer as an adhesive, and the second sealing layer is entirely interposed between the first sealing layer and the insulating protection member; wherein the insulating protection member is a plate-like member. The ordinary artisan would have been motivated to modify Nishida et al. and Hartung et al. in the above manner for the purpose of preventing infiltration of moisture and other matter into the resin-sealed electronic control device and improving the reliability of the resin-sealed electronic control device. Further, it would have been obvious to try one of the known methods with a reasonable expectation of success. KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Regarding claims 2-3, Nishida et al. discloses in Fig. 1b
a connection terminal [15] mounted to the housing [7], wherein the wiring member [13] includes a first wiring member that electrically connects the semiconductor element [11] and the connection terminal [15];
wherein: the semiconductor element [11] includes a first semiconductor element [11 left] and a second semiconductor element [11 right], and the wiring member [13] includes a second wiring member configured to electrically connect the first semiconductor element [11 left] and the second semiconductor element [11 right].
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Claims 1-3 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Ota et al. (US Pub. 20130009298) in view of Shirasawa et al. (US Pub. 20050199999) and Koyanagi (US Pub. 20190164858) as evidenced by Kim et al. (US Pat. 10304788)
Regarding claim 1, Ota et al. discloses in Fig. 3 a semiconductor module comprising:
a mounting substrate [1];
a semiconductor element [3 or 4] mounted on the mounting substrate [1];
a housing [8] configured to house the semiconductor element [3 or 4];
a first sealing layer [7] filled in a space inside the housing [8] to seal the semiconductor element [3 or 4];
a second sealing layer [9] of a resin material softer than the first sealing layer [7] and layered on the first sealing layer [7][silicon gel of layer [9] is softer than epoxy resin of layer [7] as evidenced in column 5, lines 33-49 and column 6, lines 34-56 of Kim et al.];
a wiring member [41, 42] electrically connected to the semiconductor element [3 or 4]; and
wherein the wiring member [41 , 42] includes:
a first portion covered with the first sealing layer [7]; and
a second portion covered with the second sealing layer [9],
a sealing member comprising layers of the first sealing layer [7] and the second sealing layer [9].
Ota et al. fails to disclose
an insulating protection member configured to cover a top surface of the second sealing layer;
wherein the insulating protection member being bonded to the sealing member using the second sealing layer as an adhesive, and
the second sealing layer is entirely interposed between the first sealing layer and the insulating protection member.
wherein the insulating protection member is a plate-like member.
Shirasawa et al. discloses in Fig. 1, paragraph [0029]
a protection member [18] configured to cover a top surface of the second sealing layer [17];
wherein the protection member [18] being bonded to the sealing member [16 and 17] using the second sealing layer [17] as an adhesive, and
the second sealing layer [17] is entirely interposed between the first sealing layer [16] and the protection member [18];
wherein the protection member [18] is a plate-like member.
Koyanagi discloses in Fig. 1, paragraph [0016]
a protection member [34] is an insulating protection member [“The material of the lid 34 …is engineering plastics such, for example, as PPS resin”];
wherein the insulating protection member [34] is a plate-like member.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Shirasawa et al. and Koyanagi into the method of Ota et al. to include an insulating protection member configured to cover a top surface of the second sealing layer; wherein the insulating protection member being bonded to the sealing member using the second sealing layer as an adhesive, and the second sealing layer is entirely interposed between the first sealing layer and the insulating protection member; wherein the insulating protection member is a plate-like member. The ordinary artisan would have been motivated to modify Ota et al. in the above manner for the purpose of preventing infiltration of moisture and other matter into the resin-sealed electronic control device and improving the reliability of the resin-sealed electronic control device. Further, it would have been obvious to try one of the known methods with a reasonable expectation of success. KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Regarding claim 2, Ota et al. discloses in Fig. 3
a connection terminal [51 or 52] mounted to the housing [8], wherein the wiring member [41, 42] includes a first wiring member that electrically connects the semiconductor element [3 and 4] and the connection terminal [51 or 52].
Regarding claim 3, Ota et al. discloses in Fig. 3
wherein: the semiconductor element [3 and 4] includes a first semiconductor element [4] and a second semiconductor element [3],
Ota et al. further discloses a connection member [5] configured to electrically connect the first semiconductor element [3] and the second semiconductor element [4].
Ota et al. fails to disclose
the wiring member includes a second wiring member configured to electrically connect the first semiconductor element and the second semiconductor element
Shirasawa et al. discloses in Fig. 1
the wiring member [15] includes a second wiring member configured to electrically connect the first semiconductor element [40b] and the second semiconductor element [40a].
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Shirasawa et al. into the method of Ota et al. to include the wiring member includes a second wiring member configured to electrically connect the first semiconductor element and the second semiconductor element. The ordinary artisan would have been motivated to modify Ota et al. in the above manner for the purpose of providing suitable alternative method for electrically connect the first semiconductor element and the second semiconductor element. Further, it would have been obvious to try one of the known methods with a reasonable expectation of success. KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Regarding claim 9, Ota et al. discloses in Fig. 3, paragraph [0024]-[0025]
a connection terminal [51 or 52] mounted to the housing [8];
wherein the second portion of the wiring member [41 and 42] includes one end of the wiring member [41 and 42], and wherein the one end of the wiring member [41 and 42] is connected to the connection terminal [51 or 52].
Response to Arguments
Applicant’s arguments with respect to claims 1-6, 8-9 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Overall, Applicant’s arguments are not persuasive. The claims stand rejected.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The cited art discloses similar materials, devices and methods.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SOPHIA T NGUYEN whose telephone number is (571)272-1686. The examiner can normally be reached 9:00am -5:00 pm, Monday-Friday.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, BRITT D HANLEY can be reached at (571)270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SOPHIA T NGUYEN/ Primary Examiner, Art Unit 2893
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