Prosecution Insights
Last updated: October 27, 2026
Application No. 18/172,580

MULTI-GPU MULTI-DISPLAY TILED RENDERING WITH OPTIMIZED VARIABLE RATE SHADING

Final Rejection §103
Filed
Feb 22, 2023
Examiner
SINHA, SNIGDHA
Art Unit
2619
Tech Center
2600 — Communications
Assignee
Intel Corporation
OA Round
2 (Final)
33%
Grant Probability
At Risk
3-4
OA Rounds
0m
Est. Remaining
59%
With Interview

Examiner Intelligence

Grants only 33% of cases
33%
Career Allowance Rate
4 granted / 12 resolved
-28.7% vs TC avg
Strong +26% interview lift
Without
With
+25.5%
Interview Lift
resolved cases with interview
Typical timeline
2y 7m
Avg Prosecution
16 currently pending
Career history
41
Total Applications
across all art units

Statute-Specific Performance

§101
0.8%
-39.2% vs TC avg
§103
70.0%
+30.0% vs TC avg
§102
13.3%
-26.7% vs TC avg
§112
10.8%
-29.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 12 resolved cases

Office Action

§103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1, 3-6, 7 and 9-12 are rejected under 35 U.S.C. 103 as being unpatentable over Grossman (US 20230386133) in view of Redshaw (US 20190139294) and further in view of Andonieh (US 20120001925) and further in view of Obert (US 20170249779). Regarding claim 1, Grossman teaches a computing system comprising: Intercept one or more commands to set a first shading rate for offscreen regions of a scene (Paragraph 31, task 506 may include several sub-tasks that may be performed by the GPU for each meshlet instance (e.g., meshlet instance M) submitted by the CPU in the command buffer for the current frame… those meshlets that are out of focus from the observer's (e.g., the camera's) point of view may be selected to have a lower level of detail (corresponding to a higher LOD value). In addition, the LOD processor may also receive input from a variable rate shading map (e.g., VRS map 256 of FIG. 2)… the LOD processor may determine the LOD value that corresponds to the detail that is visible, needed, and is important to the frame ) Set a second shading rate for the offscreen regions of the scene, wherein the second shading rate is less than the first shading rate (Paragraph 5, the first level of detail value for the visible meshlet instance and the second level of detail value for the visible meshlet instance; Paragraph 31, those meshlets that are out of focus from the observer's (e.g., the camera's) point of view may be selected to have a lower level of detail (corresponding to a higher LOD value). In addition, the LOD processor may also receive input from a variable rate shading map (e.g., VRS map 256 of FIG. 2)… the LOD processor may determine the LOD value that corresponds to the detail that is visible, needed, and is important to the frame). A memory coupled to the host processor, the memory storing a set of instructions, which when executed by the host processor (Paragraph 20, CPU 102 may execute instructions stored in memory), cause the host processor to: While Grossman fails to disclose the following, Redshaw teaches: A plurality of graphics processors (Paragraph 9, a plurality of processing engines configured to apply one or both of texturing and shading to primitive fragments); A host processor coupled to the plurality of graphics processors (Paragraph 9, a tile allocation unit configured to operate in one or more allocation modes to allocate tiles to the processing engines) On a per-graphics processor basis and a per-display basis (Paragraph 51, tiles are allocated to the processing engines 216 such that each of the processing engines 216 processes the primitive fragments of a tile allocated to that processing engine 216). Note: Redshaw teaches assigning a processing engine (processor) to a tile (display). Wherein the scene is associated with the plurality of graphics processors and a plurality of displays (Abstract, A graphics processing system processes primitive fragments using a rendering space which is sub-divided into tiles. The graphics processing system comprises processing engines configured to apply texturing and/or shading to primitive fragments). Redshaw and Grossman are both considered to be analogous to the claimed invention because they are in the same field of variable rate shading. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Grossman to incorporate the teachings of Redshaw and use a plurality of graphics processors coupled to a host processor and map processors to different displays (tiles). Doing so would have allowed for efficiently processing commands or instructions from the host by dividing the work between various regions. While the combination of Grossman and Redshaw fails to disclose the following, Andonieh teaches: Determine, separately for each graphics processor, the offscreen regions of the scene (Abstract, evaluating performance statistics for each of the processors and establishing load rendering boundaries for each of the processors). Andonieh and the combination of Grossman and Redshaw are both considered to be analogous to the claimed invention because they are in the same field of variable rate shading. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Grossman and Redshaw to incorporate the teachings of Andonieh and determine offscreen regions of the scene for each graphics processor. Doing so would have allowed for fine tuning which enables the boundaries to be established based more upon the availability/capability of particular ones of the GPUs instead of merely dividing the load evenly (Andonieh, Paragraph 91). While the combination of Grossman, Redshaw, and Andonieh fails to disclose the following, Obert teaches: Determine, separately for each display, the offscreen regions of the scene (Paragraph 16, The GPU may further rasterize a representation of each of the plurality of bounding volumes to an off-screen render target in the memory). Obert and the combination of Grossman, Redshaw, and Andonieh are both considered to be analogous to the claimed invention because they are in the same field of variable rate shading. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Grossman, Redshaw, and Andonieh to incorporate the teachings of Obert and determine offscreen regions of the scene for each display. Doing so would have allowed for customizing each display’s resources to use them effectively and not process the offscreen regions. CRM claim 7 corresponds to system claim 1. Therefore, claim 7 is rejected for the same reasons as used above. Regarding claim 3, the combination of Grossman, Redshaw, Andonieh, and Obert teaches the computing system of claim 1, wherein the instructions, when executed, further cause the host processor to identify, on the per-graphics processor basis and the per-display basis, guard bands between the offscreen regions and onscreen regions, wherein the onscreen regions and the guard bands are rendered at the first shading rate (Grossman, Paragraph 31, the meshlets closer to the periphery of the frame (i.e., the non-foveal region) may have a coarser level of detail… Since the VRS map allows for varying the shading rate for different regions of the frame, the VRS map input may also be used in selecting the right level of detail for a mesh or a meshlet). Note: Grossman teaches identifying guard band areas (close to the periphery of the frame) as well as selecting the level of detail for each meshlet. Therefore, Grossman teaches rendering the onscreen regions and guard bands at the first shading rate. Additionally, Redshaw, Andonieh, and Obert teach the per-graphics processor and per display basis. CRM claim 9 corresponds to system claim 3. Therefore, claim 9 is rejected for the same reasons as used above. Regarding claim 4, the combination of Grossman, Redshaw, Andonieh, and Obert teaches the computing system of claim 3, wherein the guard bands are identified based on shading rate tile data (Grossman, Paragraph 31, the meshlets closer to the periphery of the frame (i.e., the non-foveal region) may have a coarser level of detail… Since the VRS map allows for varying the shading rate for different regions of the frame, the VRS map input may also be used in selecting the right level of detail for a mesh or a meshlet). Note: Grossman teaches that the system can choose the correct level of detail for particular meshlets and is able to identify peripheral regions. Therefore, the guard bands are able to be identified based on shading rate tile data. CRM claim 10 corresponds to system claim 4. Therefore, claim 10 is rejected for the same reasons as used above. Regarding claim 5, the combination of Grossman, Redshaw, Andonieh, and Obert teaches the computing system of claim 1, wherein determining the offscreen regions separately for each graphics processor and each display comprises identifying the offscreen regions based on display orientation (Paragraph 31, those meshlets that are out of focus from the observer's (e.g., the camera's) point of view may be selected to have a lower level of detail (corresponding to a higher LOD value)) and size data (Paragraph 31, the distance of the projected scene from the observer (the closer the observer is to a scene the lower the LOD value)). Note: Grossman teaches that as the distance from the observer to the projected screen changes, the level of detail changes. The distance to the screen changes the size of the data that the observer is able to view. Therefore, Grossman teaches identifying offscreen regions based on size data. Additionally, Redshaw, Andonieh, and Obert teach the per-graphics processor and per display basis. CRM claim 11 corresponds to system claim 5. Therefore, claim 11 is rejected for the same reasons as used above. Regarding claim 6, the combination of Grossman, Redshaw, Andonieh, and Obert teaches the computing system of claim 5. While the combination as presented previously fails to disclose the following, Redshaw further teaches: Wherein the offscreen regions are identified further based on dispatch thread identifier data (Paragraph 51, tiles are allocated to the processing engines 216 such that each of the processing engines 216 processes the primitive fragments of a tile allocated to that processing engine 216). Note: Redshaw teaches that each processing engine is mapped to a specified tile. Therefore, Redshaw teaches identifying processing engines that are mapped to the offscreen tiles. Redshaw and the combination of Grossman, Andonieh, and Obert are both considered to be analogous to the claimed invention because they are in the same field of variable rate shading. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Grossman, Andonieh, and Obert to incorporate the teachings of Redshaw and identify offscreen regions based on dispatch thread identifier data. Doing so would have allowed for efficiently distributing commands for the correct regions based on the associated processing engine. CRM claim 12 corresponds to system claim 6. Therefore, claim 12 is rejected for the same reasons as used above. Claims 2 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Grossman in view of Redshaw and further in view of Andoniesh, and further in view of Obert as applied to claims 1, 3-6, 7 and 9-12 above and further in view of Chen (US 20220383582). Regarding claim 2, the combination of Grossman, Redshaw, Andonieh, and Obert teaches the computing system of claim 1. While the combination fails to disclose the following, Chen teaches: Wherein the instructions, when executed, further cause the host processor to execute one or more compute shaders based on the second shading rate (Paragraph 76, For example, the GPU(s) 608 may be used for General-Purpose computing on GPUs (GPGPU). The GPU(s) 608 may include hundreds or thousands of cores that are capable of handling hundreds or thousands of software threads simultaneously). Note: The applicant’s specification [0090] mentions a compute shader as interchangeable with a general-purpose graphics processing unit (GPGPU). Chen and the combination of Grossman, Redshaw, Andonieh, and Obert are both considered to be analogous to the claimed invention because they are in the same field of variable rate shading. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Grossman, Redshaw, Andonieh, and Obert to incorporate the teachings of Chen and use a compute shader (GPGPU). Doing so would have allowed for handling large volumes of commands along with large volumes of threads to process data efficiently. CRM claim 8 corresponds to system claim 2. Therefore, claim 8 is rejected for the same reasons as used above. Claims 13 and 15-20 are rejected under 35 U.S.C. 103 as being unpatentable over Grossman in view of Redshaw and further in view of Andonieh and further in view of Obert as applied to claims 1, 3-6, 7 and 9-12 above and further in view of Vaidyanathan (US 20180293760). Regarding claim 13, apparatus claim 13 corresponds to system claim 1, which is taught by the combination of Grossman, Redshaw, Andonieh, and Obert. While the combination fails to disclose the following, Vaidyanathan teaches: One or more substrates (Paragraph 135, that includes a substrate); and Logic coupled to the one or more substrates, wherein the logic is implemented at least partly in one or more of configurable or fixed-functionality hardware (Paragraph 135, transistor array and other integrated circuit/IC components) coupled to the substrate 1002. The logic 1004, which may be implemented in configurable logic and/or fixed-functionality logic hardware, includes a graphics processor 1004a, a host processor 1004b and an IO module 1004c. The logic 1004 may generally implement one or more aspects of the method). Vaidyanathan and the combination of Grossman, Redshaw, Andonieh, and Obert are both considered to be analogous to the claimed invention because they are in the same field of variable rate shading. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Grossman, Redshaw, Andonieh, and Obert to incorporate the teachings of Vaidyanathan and use a substrate along with logic implemented in hardware to execute the desired function. Doing so would have allowed for using a known way to implement variable rate shading. Regarding claim 15, the combination of Grossman, Redshaw, Andonieh, Obert, and Vaidyanathan teaches the semiconductor apparatus of claim 13, wherein the logic is further to identify, on the per-graphics processor basis and the per-display basis, guard bands between the offscreen regions and onscreen regions, wherein the onscreen regions and the guard bands are rendered at the first shading rate (Grossman, Paragraph 31, the meshlets closer to the periphery of the frame (i.e., the non-foveal region) may have a coarser level of detail… Since the VRS map allows for varying the shading rate for different regions of the frame, the VRS map input may also be used in selecting the right level of detail for a mesh or a meshlet). Note: Grossman teaches identifying guard band areas (close to the periphery of the frame) as well as selecting the level of detail for each meshlet. Therefore, Grossman teaches rendering the onscreen regions and guard bands at the first shading rate. Additionally, Redshaw, Andonieh, and Obert teach the per-graphics processor and per display basis. Regarding claim 16, the combination of Grossman, Redshaw, Andonieh, Obert, and Vaidyanathan teaches the semiconductor apparatus of claim 15, wherein the onscreen regions and the guard bands are rendered at the first shading rate (Grossman, Paragraph 31, Since the VRS map allows for varying the shading rate for different regions of the frame, the VRS map input may also be used in selecting the right level of detail for a mesh or a meshlet). Note: Grossman teaches identifying guard band areas (close to the periphery of the frame) as well as selecting the level of detail for each meshlet. Therefore, Grossman teaches rendering the onscreen regions and guard bands at the first shading rate. Regarding claim 17, the combination of Grossman, Redshaw, Andonieh, Obert, and Vaidyanathan teaches the semiconductor apparatus of claim 15, wherein the guard bands are identified based on shading rate tile data (Grossman, Paragraph 31, the meshlets closer to the periphery of the frame (i.e., the non-foveal region) may have a coarser level of detail… Since the VRS map allows for varying the shading rate for different regions of the frame, the VRS map input may also be used in selecting the right level of detail for a mesh or a meshlet). Note: Grossman teaches that the system can choose the correct level of detail for particular meshlets and is able to identify peripheral regions. Therefore, the guard bands are able to be identified based on shading rate tile data. Regarding claim 18, the combination of Grossman, Redshaw, Andonieh, Obert, and Vaidyanathan teaches the semiconductor apparatus of claim 13, wherein determining the offscreen regions separately for each graphics processor and each display comprises identifying the offscreen regions based on display orientation data (Paragraph 31, those meshlets that are out of focus from the observer's (e.g., the camera's) point of view may be selected to have a lower level of detail (corresponding to a higher LOD value)). Note: Grossman teaches that as the distance from the observer to the projected screen changes, the level of detail changes. The distance to the screen changes the size of the data that the observer is able to view. Therefore, Grossman teaches identifying offscreen regions based on size data. Additionally, Redshaw teaches the per-graphics processor and per display basis. Regarding claim 19, the combination of Grossman, Redshaw, Andonieh, Obert, and Vaidyanathan teaches the semiconductor apparatus of claim 18, wherein the offscreen regions are identified further based on display size data (Paragraph 31, the distance of the projected scene from the observer (the closer the observer is to a scene the lower the LOD value)). Note: Grossman teaches that as the distance from the observer to the projected screen changes, the level of detail changes. The distance to the screen changes the size of the data that the observer is able to view. Therefore, Grossman teaches identifying offscreen regions based on size data. Additionally, Redshaw teaches the per-graphics processor and per display basis. Regarding claim 20, the combination of Grossman, Redshaw, Andonieh, Obert, and Vaidyanathan teaches the semiconductor apparatus of claim 18, wherein the offscreen regions are identified further based on dispatch thread identifier data (Redshaw, Paragraph 51, tiles are allocated to the processing engines 216 such that each of the processing engines 216 processes the primitive fragments of a tile allocated to that processing engine 216). Note: Redshaw teaches that each processing engine is mapped to a specified tile. Therefore, Redshaw teaches identifying processing engines that are mapped to the offscreen tiles. Redshaw and the combination of Grossman, Andonieh, Obert, and Vaidyanathan are both considered to be analogous to the claimed invention because they are in the same field of variable rate shading. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Grossman, Andonieh, Obert, and Vaidyanathan to incorporate the teachings of Redshaw and identify offscreen regions based on dispatch thread identifier data. Doing so would have allowed for efficiently distributing commands for the correct regions based on the associated processing engine. Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Grossman in view of Redshaw and further in view of Andonieh and further in view of Obert and further in view of Vaidyanathan as applied to claims 13 and 15-20 above and further in view of Chen. Regarding claim 14, the combination of Grossman, Redshaw, Andonieh, Obert, and Vaidyanathan teaches the semiconductor apparatus of claim 13. While the combination fails to disclose the following, Chen teaches: Wherein the logic is to execute one or more compute shaders based on the second shading rate (Paragraph 76, For example, the GPU(s) 608 may be used for General-Purpose computing on GPUs (GPGPU). The GPU(s) 608 may include hundreds or thousands of cores that are capable of handling hundreds or thousands of software threads simultaneously). Note: The applicant’s specification [0090] mentions a compute shader as interchangeable with a general-purpose graphics processing unit (GPGPU). Chen and the combination of Grossman, Redshaw, Andonieh, Obert, and Vaidyanathan are both considered to be analogous to the claimed invention because they are in the same field of variable rate shading. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Grossman, Redshaw, Andonieh, Obert, and Vaidyanathan to incorporate the teachings of Chen and use a compute shader (GPGPU). Doing so would have allowed for handling large volumes of commands along with large volumes of threads to process data efficiently. Response to Arguments Applicant’s arguments with respect to claims 1, 7, and 13 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Andonieh teaches determining off screen regions per graphics processor and Obert teaches determining off screen regions per display. Therefore, it would have been obvious to a person of ordinary skill in the art to combine these teachings with the teachings of Grossman and Redshaw to determine offscreen regions for each graphics processor and each display. Conclusion THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to SNIGDHA SINHA whose telephone number is (571)272-6618. The examiner can normally be reached Mon-Fri. 12pm-8pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jason Chan can be reached at 571-272-3022. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /SNIGDHA SINHA/Examiner, Art Unit 2619 /JASON CHAN/Supervisory Patent Examiner, Art Unit 2619
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Prosecution Timeline

Feb 22, 2023
Application Filed
Apr 13, 2023
Response after Non-Final Action
Apr 08, 2026
Non-Final Rejection mailed — §103
Jul 07, 2026
Response Filed
Oct 15, 2026
Final Rejection mailed — §103 (current)

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Prosecution Projections

3-4
Expected OA Rounds
33%
Grant Probability
59%
With Interview (+25.5%)
2y 7m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
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