DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 1/21/2026 has been entered.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-6 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Thirunakkarasu et al. (US 20120218133).
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With respect to claim 1, Thirunakkarasu et al. (US 20120218133) discloses a single-output multiplexer (i.e. 304-A), comprising a shared capacitor circuit (the shared capacitor circuit being boost circuit 404) including a capacitor (COUT); and a first plurality of switch circuits (plurality of switch circuits being 402-1 and 402-N) coupled to the shared capacitor circuit (404) and an input power supply node (HMVD), and coupled between respective multiplexer input nodes (IN1-INN) of a plurality of multiplexer input nodes and a common multiplexer output node (OUT), wherein: the plurality of switch circuits includes a first switch circuit (i.e. 402-1) including a first n-channel pass transistor (Q4-1) configured to selectively connect, in response to activation of a first control signal (SEL1-A), a first multiplexer input signal (at IN1) on a first input node (IN1) to the common multiplexer output node (OUT) as a sole selected signal of the single-output multiplexer and the first switch circuit (402-1) is configured to , in response to the activation of the first control signal (SEL1-A): generate a first boost voltage (at boost circuit) for the first n-channel pass transistor (Q4-1) using the capacitor (COUT), wherein the first boost voltage is greater than a voltage level of the input power supply node (boost voltage is greater than HMVDD, since it is a positive 15 Volts plus the input voltage applied to the gate, see [0030]: “The assertion of select signal SEL1-A actuates switches S6-1, S7-1 and S10-1 so that the output and input terminals of cell 302-1 are coupled together through switches S7-1 and S6-1. Additionally, the top plate of boost capacitor COUT is coupled to the gate of switch Q4-1, allowing the voltage from input signal IN1 at the sampling instant plus the voltage stored on capacitor C1 (i.e., +15V) to be applied to the gate of switch Q4-1”.); and connect the first multiplexer input signal (at IN1) to the common multiplexer output node (OUT) using the first boost voltage (at boost circuit); and wherein the single-output multiplexer is configured to use the shared capacitor circuit (COUT) to generate a boost voltage (at boost circuit) for a selected n-channel pass transistor (i.e. Q4-1; if Q4-N were selected the selected switch would correspond to 402-N) of a corresponding selected switch circuit (i.e. 402-1; if Q4-N were selected the selected switch would correspond to 402-N) , of the plurality of switch circuits (402-1-402-N), that is selected by activation of a corresponding control signal (SEL1-A – SELN-A) to provide the sole selected signal of the single-output multiplexer (i.e. 304-A).
With respect to claim 2, Thirunakkarasu et al. (US 20120218133) discloses the single-output multiplexer of claim 1, wherein the shared capacitor circuit (404) is configured to perform a pre-charge operation on the capacitor in response to a determination that a first selection signal (SEL1-A) has been deactivated (See [0030]: “a sample charge signal SAMCH (which is generally provided by boost logic 302 and which generally occurs during the non-sampling phase or conversion phase). Assuming (for example) that the channel associated with cell 402-1 is selected, its input signal IN1 can be transmitted to the ADC 104 during the sampling phase of sample clock signal SAMPLE. During the non-sampling or conversion phase in this example, select signals SEL1-B to SELN-B are asserted while select signals SEL1-A to SELN-A are deasserted. This actuates switches S8-1 to S8-N to ground nodes between the input and output for each cell 302-1 to 302-N and actuates switches S9-1 to S9-N to couple the gates of switches Q4-1 to Q4-N to the negative voltage rail HMVDD (to generally ensure that switches Q4-1 to Q4-N are "off"). Additionally, switches S11 and S12 are actuated by sample charge signal SAMCH (which is generally provided by the boost logic 302) to allow the boost capacitor COUT to be charged to the voltage (i.e., +15V) on positive voltage rail HPVDD. Once boost capacitor COUT is charged, the sample charge signal SAMCH deactivates switches S11 and S12, while select signal SEL1-A (in this example) is asserted and select signals SEL1-B to SELN-B are deasserted. The assertion of select signal SEL1-A actuates switches S6-1, S7-1 and S10-1 so that the output and input terminals of cell 302-1 are coupled together through switches S7-1 and S6-1. Additionally, the top plate of boost capacitor COUT is coupled to the gate of switch Q4-1, allowing the voltage from input signal IN1 at the sampling instant plus the voltage stored on capacitor C1 (i.e., +15V) to be applied to the gate of switch Q4-1. Thus, the voltage from input signal IN1 at the sampling instant can be provided as output signal OUT of mux 304 to ADC 104. Then, during the conversion phase, select signals SEL1-A/SEL1-B to SELN-A/SELN-B are deasserted.”) .
With respect to claim 3, Thirunakkarasu et al. (US 20120218133) discloses the single-output multiplexer of claim 2, wherein the shared capacitor circuit (i.e 404) is further configured to halt the pre-charge operation in response to an activation of a second selection signal (i.e. SEL1-B), and wherein a second switch circuit (i.e. S11) is further configured, in response to the activation of the second selection signal (see [0030] selection signals in response to one another) , to: generate a second boost voltage using the capacitor( COUT), wherein the second boost voltage (HPVDD) is greater (See also [0030]) “ to allow the boost capacitor COUT to be charged to the voltage (i.e., +15V) on positive voltage rail HPVDD”) than the voltage level of the input power supply node (HMVDD), and couple, using the second boost voltage, a second input signal to the common multiplexer output node (OUT).
With respect to claim 4, Thirunakkarasu et al. (US 20120218133) discloses the single-output multiplexer of claim 1, wherein to connect the first multiplexer input signal (IN1) to the common multiplexer output node (OUT), the first switch circuit (i.e. 402-1) is configured to connect, via one or more conducting transistor channels (through Q4-1), a control terminal (gate) of the switch first n-channel pass transistor (Q4-1) to a first terminal of the capacitor (at COUT).
With respect to claim 5, Thirunakkarasu et al. (US 20120218133) discloses the single-output multiplexer of claim 1, wherein to generate the first boost voltage (at 404), the first switch circuit (i.e. 402-1) is further configured to connect, via one or more conducting transistor channels (through Q4-1 emitter to gate via closed S10-1), the first input node (IN1) to a second terminal of the capacitor (top of COUT).
With respect to claim 6, Thirunakkarasu et al. (US 20120218133) discloses the single-output multiplexer of claim 1, wherein the first switch circuit (i.e. 402-1) includes a level-shifter circuit (here, the level shifter is interpreted as the switches S6-1-S10-1 as they have the ability to switch the input signals between HMVDD and ground) coupled to a first terminal of the capacitor (at COUT ), and wherein the level-shifter circuit is configured to generate the first boost voltage based on a voltage level of the common multiplexer output node (COUT) and apply the first boost voltage to a control input of the first n-channel pass transistor (gate of Q4-1).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 7-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Thirunakkarasu et al. (US 20120218133).
With respect to claim 7, Thirunakkarasu et al. (US 20120218133) discloses a method, comprising: receiving a plurality of multiplexer input signals (In1- InN) and a plurality of selection signals (SEL1-A-SELN-B) by respective ones of a plurality of switch circuits (402-1-402-N) included in a single-output multiplexer (one output at OUT), wherein respective outputs of the plurality of switch circuits (i.e. coupled at OUT via Q4-1 or Q4-N) are coupled to a common output node (OUT) of the single-output multiplexer, wherein the plurality of switch circuits (402-1- 402-N) are coupled to a shared capacitor (COUT), and wherein a given switch circuit (one of 402-1-402N ) of the plurality of switch circuits includes an n- channel pass transistor (Q4-1-Q4-N) coupled to the common output node (at OUT is common node); and in response to activation of a particular selection signal of the plurality of selection signals (i.e. one of SEL1-A-SELN-A): generating, by a particular switch circuit (one of 402-1-402N ) of the plurality of switch circuits that corresponds to the particular selection signal and for the n-channel pass transistor (of the particular switch circuit, a boost voltage (from 404) using the shared capacitor (COUT), wherein the boost voltage is greater than a voltage level of an input power supply node (HMVDD) coupled to the plurality of switch circuits (boost voltage is greater than HMVDD, since it is a positive 15 Volts plus the input voltage applied to the gate, see [0030]: “The assertion of select signal SEL1-A actuates switches S6-1, S7-1 and S10-1 so that the output and input terminals of cell 302-1 are coupled together through switches S7-1 and S6-1. Additionally, the top plate of boost capacitor COUT is coupled to the gate of switch Q4-1, allowing the voltage from input signal IN1 at the sampling instant plus the voltage stored on capacitor C1 (i.e., +15V) to be applied to the gate of switch Q4-1”.); and connecting via the n-channel pass transistor of (i.e. one of Q4-1-A4-N) the particular switch circuit (one of 402-1-402N ) and using the boost voltage (from 404), a particular multiplexer input signal (one of In1- InN), of the plurality of multiplexer input signals (In1- InN), that is received by the particular switch circuit (one of 402-1-402N ) to the common output node (OUT).
But fails to disclose selecting a sole selected signal of the single output multiplexer.
The multiplexer of Thirunakkarasu has the ability to select multiple different types of signals of the of the single-output multiplexer such that depending on the selection chosen a sole selected signal may be selected. It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to select a single signal or multiple signals. It would be obvious expedient, i.e. "Obvious to try" – choosing from a finite number of identified, predictable solutions, with a reasonable expectation of success. Here, choosing from a finite of selection signals the predictable solution of a sole selected signal would be achieved with a reasonable expectation of success.
With respect to claim 8, the circuit above in Thirunakkarasu et al. (US 20120218133) produces
the method of claim 7, further comprising, in response to deactivating the particular selection signal (i.e. one of SEL1-A-SELN-A): disconnecting, by the particular switch circuit, the particular multiplexer input (one of IN1-INN) signal from the common output node (OUTPUT); and pre-charging the shared capacitor.
Here, per [0030], upon the deactivation of the selection signal SEL1-A-SELN-A, selection signals SEL1-B-SELN-B are activated and charges the negative voltage rail HMVDD. (“select signals SEL1-B to SELN-B are asserted while select signals SEL1-A to SELN-A are deasserted. This actuates switches S8-1 to S8-N to ground nodes between the input and output for each cell 302-1 to 302-N and actuates switches S9-1 to S9-N to couple the gates of switches Q4-1 to Q4-N to the negative voltage rail HMVDD (to generally ensure that switches Q4-1 to Q4-N are "off"). Additionally, switches S11 and S12 are actuated by sample charge signal SAMCH (which is generally provided by the boost logic 302) to allow the boost capacitor COUT to be charged to the voltage (i.e., +15V) on positive voltage rail HPVDD. Once boost capacitor COUT is charged, the sample charge signal SAMCH deactivates switches S11 and S12, while select signal SEL1-A (in this example) is asserted and select signals SEL1-B to SELN-B are deasserted”).
With respect to claim 9, the circuit above in Thirunakkarasu et al. (US 20120218133) produces method of claim 8, further comprising, in response to determining that the shared capacitor has been pre-charged (i.e. after activation of SEL1-B-SELN-B), activating a different selection signal (in response to the SEL1-B-SELN-B signals, the SEL1-A-SELN-A are again i.e asserted) of the plurality of selection signals. (See [0030]: “Once boost capacitor COUT is charged, the sample charge signal SAMCH deactivates switches S11 and S12, while select signal SEL1-A (in this example) is asserted and select signals SEL1-B to SELN-B are deasserted.”)
With respect to claim 10, the circuit above in Thirunakkarasu et al. (US 20120218133) produces the method of claim 7, wherein connecting the particular multiplexer input signal (one of IN1-INN) to the common output node (OUTPUT) includes connecting a first terminal of the shared capacitor (terminal at COUT) to a control terminal of the n-channel pass transistor (Q4-1-Q4-N at OUTPUT) included in the particular switch circuit.
With respect to claim 11, the circuit above in Thirunakkarasu et al. (US 20120218133) produces
the method of claim 10, wherein generating the boost voltage includes coupling a second terminal (at COUT) of the shared capacitor (COUT) to the particular multiplexer input signal (via Q$-1-A4N and S10-1-S10-N).
With respect to claim 12, the circuit above in Thirunakkarasu et al. (US 20120218133) produces the method of claim 7, wherein generating the boost voltage in response to the activation of the particular selection signal includes: coupling a first terminal of the shared capacitor (at COUT) to a level-shifter circuit (here, the level shifter is interpreted as the switches S6-1-S10-1 as they have the abilitiy to switch the input signals between HMVDD and ground); and coupling a second terminal of the shared capacitor to the common output node (here, second terminal is coupled to the common output node through the capacitor COUT).
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With respect to claim 13, the circuit above in Thirunakkarasu et al. (US 20120218133) produces
the method of claim 7, further comprising, generating, by an analog- to-digital converter circuit (note: figure 4 is an example of the mux in figure 3, whereas figure 3 shows the analog-to-digital converter (104)) , a plurality of bits (plurality of bits at DOUT) using the selected signal of the single-output multiplexer (output of the Mux at 304).
With respect to claim 14, Thirunakkarasu et al. (US 20120218133) discloses an apparatus, comprising: a single-output multiplexer (i.e. 304-A), including a plurality of switch circuits (plurality of switch circuits being 402-1 and 402-N) coupled to a shared capacitor (the shared capacitor COUT) and a common output node (at OUT) of the single-output multiplexer, wherein a given switch circuit (one of 402-1 and 402-N; i.e. 402-1) of the plurality of switch circuits (402-1 and 402-N) includes an n-channel pass transistor (i.e. Q4-1) coupled to the common output node (OUT), and wherein the single-output multiplexer is configured to: receive a plurality of input signals (IN1-INN) to the single-output multiplexer; receive a plurality of control signals (SEL1-A-SELN-A and SEL1-B-SELN-B); and in response to an activation of a particular control signal (i..e SEL1-A) of the plurality of control signals (SEL1-A would generate subsequent SELN-B control signals by deactivating): generate, using the shared capacitor (COUT), a boost voltage (at 404) for the n-channel pass transistor (one of Q4-1-Q4-N i.e. Q4-1) of a particular switch circuit (one of 402-1 and 402-N; i.e. 402-1) of the plurality of switch circuits that corresponds to the particular control signal; and connect, via the n-channel pass transistor (one of Q4-1-Q4-N i.e. Q4-1) of the particular switch circuit and using the boost voltage, a particular input signal (one of IN1-INN) of the plurality of input signals that corresponds to the particular control signal to the common output node (OUT); and an analog-to-digital converter circuit (see fig. 3, of which figure 4 is a configuration of the structure of fig. 3) configured to receive the signal and generate a plurality of bits (output of ADC) based on the signal (the signal being upstream thus forming the basis of “based on”): wherein the single-output multiplexer is configured to use the shared capacitor (COUT) to generate the boost voltage (at 404) for a selected n-channel pass transistor (one of Q4-1-Q4-N) of a corresponding selected switch circuit, of the plurality of switch circuits, that is selected by activation of a corresponding control signal to provide the signal of the single-output multiplexer.
But fails to disclose a particular input signal of the plurality of input signals that corresponds to the particular control signal to the common output node as a sole selected signal of the single-output multiplexer and an analog-to-digital converter circuit configured to receive the sole selected signal and generate a plurality of bits based on the sole selected signal and wherein the single-output multiplexer is configured to use the shared capacitor to generate the boost voltage for a selected n-channel pass transistor of a corresponding selected switch circuit, of the plurality of switch circuits, that is selected by activation of a corresponding control signal to provide the sole selected signal of the single-output multiplexer.
Here, the missing part is that a sole signal is selected. In the prior art reference, any single or number of signals can be selected based on the preference of the user to achieve a result. The multiplexer of Thirunakkarasu has the ability to select multiple different types of signals of the of the single-output multiplexer such that depending on the selection chosen a sole selected signal may be selected. It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to select a single signal or multiple signals. It would be obvious expedient, i.e. "Obvious to try" – choosing from a finite number of identified, predictable solutions, with a reasonable expectation of success. Here, choosing from a finite number of selection signals the predictable solution of a sole selected signal would be achieved with a reasonable expectation of success.
With respect to claim 15, Thirunakkarasu et al. (US 20120218133) produces the apparatus of claim 14, wherein the single-output multiplexer (i.e. 304-A), is further configured, in response to a deactivation of the particular control signal (in response to SELN-B, the control signals of SELN-A are activated and vice versa see [0030]), , to: disconnect the particular input signal (one of IN1-INN) from the common output node (OUT); and pre-charge the shared capacitor (COUT).
With respect claim 16, Thirunakkarasu et al. (US 20120218133) produces the apparatus of claim 15, wherein the single-output multiplexer (i.e. 304-A) is further configured, in response to a determination that the shared capacitor (COUT) has been pre-charged (the selection of control signals respond to each other such that in response to SELN-B, the control signals of SELN-A are activated and vice versa which produce the charging and discharging (or negative charging) based on the control signals see [0030] ), to respond to an activation of a different control signal of the plurality of control signals.
With respect claim 17, Thirunakkarasu et al. (US 20120218133) produces the apparatus of claim 15, wherein to pre-charge the shared capacitor, the single-output multiplexer (i.e. 304-A) is further configured to couple the shared capacitor (COUT) between an input power supply node (HPVDD) and a ground supply node (GND).
With respect claim 18, Thirunakkarasu et al. (US 20120218133) produces the apparatus of claim 14, wherein to connect the particular input signal to the common output node (OUT), the single-output multiplexer (i.e. 304-A) is further configured to connect a first terminal of the shared capacitor (at COUT) to a control terminal of the n- channel pass transistor (one of Q4-N via S10-N) included in the particular switch circuit.
With respect claim 19, Thirunakkarasu et al. (US 20120218133) produces the apparatus of
claim 18, wherein to generate the boost voltage (at 404), the single-output multiplexer (i.e. 304-A) is further configured to couple a second terminal of the shared capacitor (at COUT) to the particular input signal (one of INN).
With respect claim 20, Thirunakkarasu et al. (US 20120218133) produces the apparatus of claim 14, wherein to generate the boost voltage (at 404) in response to the activation of the particular control signal (see [0030] ), the single-output multiplexer (i.e. 304-A) is further configured to: couple a first terminal of the shared capacitor (at COUT) to a level-shifter circuit (here, the level shifter is interpreted as the switches S6-1-S10-1 as they have the ability to level shift the input signals between HMVDD and ground) included in the multiplexer; and couple a second terminal of the shared capacitor (at COUT) to the common output node (at OUT).
Response to Arguments
Applicant’s arguments with respect to claim(s) 1/21/2026 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHAREEM E ALMO whose telephone number is (571)272-5524. The examiner can normally be reached M-F (8:00am-4:00pm).
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/KHAREEM E ALMO/Examiner, Art Unit 2849