DETAILED ACTION
1. This action is in response to the Request to Continued Examination (RCE) application filed on 01/15/2026.
Notice of Pre-AIA or AIA Status
2. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
3. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Continued Examination Under 37 CFR 1.114
4. A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 01/15/2026 has been entered.
Priority
5. Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 102
6. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
7. Claim(s) 1 is rejected under 35 U.S.C. 102(a)(1) and (a)(2) as being anticipated by US Pub. No. 2009/0045870 A1; (hereinafter Imura).
Regarding claim 1, Imura [e.g., Fig. 11] discloses a circuit comprising: a first transistor coupled between an input voltage terminal and an output voltage terminal [e.g., control transistor 70 coupled between input voltage terminal 10 and output terminal 30. Examiner note: For examination purposes, the examiner will interpret the term "coupled" in its broadest sense to refer as electrical components that are coupled directly or indirectly in a way that allows for the transfer of electrical energy or signals between them], the first transistor having a first control terminal [e.g., gate of control transistor 70]; a second transistor having first and second terminals and a second control terminal [e.g., NMOS transistor 65e having drain, gate and source], the first terminal coupled to the first control terminal [e.g., first terminal of NMOS transistor 65e coupled to the control terminal of control transistor 70]; a third transistor coupled between the output voltage terminal and the second control terminal [e.g., NMOS transistor 51 coupled between the voltage output terminal 30 and gate of NMOS transistor 65e], the third transistor having a third control terminal [e.g., NMOS transistor 51 having a control terminal]; a fourth transistor coupled between the third control terminal and a ground terminal [e.g., NMOS transistor 52 coupled between gate of NMOS transistor 51 and ground], in which the fourth transistor includes a fourth control terminal [e.g., gate of NMOS transistor 52], the fourth control terminal is coupled to the third control terminal [e.g., control terminal of NMOS 52 coupled to control terminal of NMOS transistor 51], and the fourth transistor is diode-connected [e.g., gate and drain of NMOS 52 connected to each other, p.0046 recites “The gate and drain of the NMOS transistor 52 are connected with the reference voltage output terminal 30, the source thereof is connected with the ground terminal 20, and the back gate thereof is connected with the ground terminal 20.”. Examiner note: For examination purposes the examiner will interpret "transistor is diode-connected" as a NMOS transistor which has its gate and drain coupled together]; and a fifth transistor having two current terminals coupled to the second terminal and the third control terminal [e.g., NMOS transistor 63e coupled to second terminal of 65e and gate of NMOS 51], respectively, the fifth transistor including a fifth control terminal coupled to the ground terminal [e.g., back gate of NMOS transistor 63e coupled to ground].
8. Claim(s) 14 - 15 are rejected under 35 U.S.C. 102(a)(1) and (a)(2) as being anticipated by US Pub. No. 2018/01773259 A1; (hereinafter Maeland et al_Fig. 6).
Regarding claim 14, Maeland et al [e.g., Fig. 6] discloses a circuit comprising: a voltage regulator circuit [e.g., regulator 20] including: a first transistor having first and second terminals and a control terminal [e.g., M1 having gate, drain and source], the first terminal coupled to an input voltage terminal [e.g., first terminal of M1 coupled to Vin], the second terminal coupled to an output voltage terminal [e.g., second terminal coupled to Vout]; a first circuit including: a second transistor having first and second terminals and a control terminal [e.g., M4 having drain, gate and source], the first terminal of the second transistor coupled to the control terminal of the first transistor [e.g., first terminal of M4 coupled to the control terminal of M1]; and a third transistor having first and second terminals and a control terminal [e.g., M2 having drain, gate and source], the first terminal of the third transistor coupled to the output voltage terminal and the second terminal of the first transistor [e.g., first terminal of M2 coupled to Vout and second terminal of M1], the second terminal of the third transistor coupled to the control terminal of the second transistor [e.g., second terminal of M2 coupled to the control terminal of M4]; and a second circuit [e.g., rest of circuit] coupled to the second terminal of the second transistor [e.g., coupled to second terminal of M4], to the control terminal of the third transistor [e.g., coupled to the control terminal of M2], and to a voltage reference terminal [e.g., coupled to ground].
Regarding claim 15, Maeland et al [e.g., Fig. 6] a load circuit [e.g., extra output circuitry 120] having an input coupled to the output voltage terminal [e.g., input of extra output circuitry 120 coupled to output voltage terminal via transistor M1], the load circuit including a fourth transistor having a first threshold voltage [e.g., M3R] and a fifth transistor having a second threshold voltage [e.g., M2R], wherein the second transistor has the first threshold voltage, and the third transistor has the second threshold voltage [e.g., paragraph 0062 lines 3-9 recites "Extra output circuitry 120 includes transistor M1R (similar to or the same as transistor M1), capacitor C3R (similar to or the same as capacitor C2), diode- coupled transistor M2R (similar to or the same as diode-coupled transistor M2), and diode-coupled transistor M3R (similar to or the same as diode-coupled transistor M3"].
Claim Rejections - 35 USC § 103
9. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
10. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
11. Claim(s) 2, 4, 6 - 7, 9 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Imura in view of Maeland et al (hereinafter Imura and Maeland et al_Fig. 6).
Regarding claim 2, Imura discloses the claimed invention except for wherein the first transistor is a natural transistor.
Maeland et al [e.g., Fig. 6] teaches wherein the first transistor is a natural transistor [p. 0041 lines 7-8 recites “… transistor M1 has a threshold voltage of nearly zero”. Examiner note: For examination purposes, the examiner will interpret the term "natural transistor" as a transistor that "may have low threshold voltage (e.g., zero volts)" as disclosed in the specifications].
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Imura wherein the first transistor is a natural transistor as suggested by Maeland et al to reduce the threshold voltage of the transistor and as a result reducing the overall voltage drop across the transistor.
Regarding claim 4, Imura [e.g., Fig. 11] discloses wherein: the second transistor is an n-channel field effect transistor [e.g., NMOS transistor 65e].
Imura does not disclose the third transistor is a p-channel field effect transistor.
Maeland et al [e.g., Fig. 6] teaches a p-channel field effect transistor [e.g., P channel transistor M2].
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Imura with the third transistor is a p-channel field effect transistor as suggested by Maeland et al to take advantage of the features of P- channel transistor. Furthermore, it would have been obvious to one of ordinary skill in the art before the effective filing date to modify Imura with the third transistor is a p-channel field effect transistor, since it has been held that the simple substitution of one known element for another to obtain predictable results is obvious.
Regarding claim 5, Imura discloses the claimed invention except for a load circuit coupled to the output voltage terminal, the load circuit including a sixth transistor and a seventh transistor, in which: a threshold voltage of the second transistor is approximately equal to a threshold voltage of the sixth transistor; and a threshold voltage of the third transistor is approximately equal to a threshold voltage of the seventh transistor.
Maeland et al [e.g., Fig. 6] teaches a load circuit [e.g., extra output circuitry 120] coupled to the output voltage terminal [e.g., coupled to load circuit via M1], the load circuit including a sixth transistor [e.g., M3R] and a seventh transistor [e.g., M2R], in which: a threshold voltage of the second transistor is approximately equal to a threshold voltage of the sixth transistor [e.g., transistor M2R similar to M2]; and a threshold voltage of the third transistor is approximately equal to a threshold voltage of the seventh transistor [e.g., transistor M3R similar to M3, p. 0062 lines 3- 9 recites "Extra output circuitry 120 includes transistor M1R (similar to or the same as transistor M1), capacitor C3R (similar to or the same as capacitor C2), diode-coupled transistor M2R (similar to or the same as diode-coupled transistor M2), and diode- coupled transistor M3R (similar to or the same as diode-coupled transistor M3"].
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify a load circuit coupled to the output voltage terminal, the load circuit including a sixth transistor and a seventh transistor, in which: a threshold voltage of the second transistor is approximately equal to a threshold voltage of the sixth transistor; and a threshold voltage of the third transistor is approximately equal to a threshold voltage of the seventh transistor as suggested by Maeland et al to allow the output voltage to track or nearly track, and thus reduce current consumption of regulator.
Regarding claim 6, Imura discloses the claimed invention except for a sixth transistor coupled between the first control terminal and the second transistor, the sixth transistor including a sixth control terminal coupled to the output voltage terminal.
Maeland et al [e.g., Fig. 6] teaches a sixth transistor [e.g., M4] coupled between the first control terminal and the second transistor [e.g., coupled between control terminal of M1 and M3], the sixth transistor including a sixth control terminal coupled to the output voltage terminal [e.g., control terminal coupled to output voltage via M3 and M2].
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Imura with a sixth transistor coupled between the first control terminal and the second transistor, the sixth transistor including a sixth control terminal coupled to the output voltage terminal as suggested by Maeland et al to adjust, modify, or set a current flowing through transistors.
Regarding claim 7, Imura discloses the claimed invention except for wherein the sixth transistor is a natural transistor.
Maeland et al [e.g., Fig. 6] teaches a natural transistor [p. 0041 lines 7-8 recites "transistor M1 has a threshold voltage of nearly zero"].
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Imura wherein the sixth transistor is a natural transistor as suggested by Maeland et al to reduce the threshold voltage of the transistor and as a result reducing the overall voltage drop across the transistor.
Regarding claim 9, Imura [e.g., Fig. 11] discloses wherein: the fourth transistor is an n-channel field effect transistor [e.g., NMOS transistor 66].
Imura does not disclose the fifth transistor is a p-channel field effect transistor.
Maeland et al [e.g., Fig. 6] teaches a p-channel field effect transistor [e.g., P channel transistor M2].
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Imura with the fifth transistor is a p-channel field effect transistor as suggested by Maeland et al to take advantage of the features of P- channel transistor, furthermore, it would have been obvious, since it has been held that choosing from a finite number of identified, predictable solutions, with a reasonable expectation of success is obvious.
Regarding claim 13, Imura discloses the claimed invention except for a capacitor coupled between the first control terminal and the ground terminal. Maeland et al [e.g., Fig. 6] teaches a capacitor coupled between the first control terminal and the ground terminal [e.g., C1, p.0055 recites “Capacitor 105 (labeled "C1") facilitates stability of the negative feedback loop in regulator 20. More specifically, capacitor 105 adds a dominant pole to the transfer function of the negative feedback loop in regulator 20. Given the relatively high output resistance of transistor M4 (in order to have a relatively large loop gain, as discussed above), the dominant pole is placed at the gate of transistor M1, i.e., via capacitor 105"].
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Imura with a capacitor coupled between the first control terminal and the ground terminal as suggested by Maeland et al to facilitate stability in the regulator.
12. Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Maeland et al_Fig. 6 in view of Maeland et al_Fig. 5.
Regarding claim 16, Maeland et al_Fig. 6 discloses the claimed invention except for a resistor having first and second terminals, the first terminal of the resistor coupled to the second terminal of the second transistor and to the control terminal of the third transistor, the second terminal of the resistor coupled to the voltage reference terminal.
Maeland et al_Fig. 5 [e.g., Fig. 5] teaches a resistor [e.g., 116] having first and second terminals [e.g., having top and bottom terminal], the first terminal of the resistor coupled to the second terminal of the second transistor and to the control terminal of the third transistor [e.g., top terminal coupled to second terminal of M4 and to control terminal of M2 via M4], the second terminal of the resistor coupled to the voltage reference terminal [e.g., bottom terminal coupled to ground]
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Maeland et al_Fig. 6 with a resistor having first and second terminals, the first terminal of the resistor coupled to the second terminal of the second transistor and to the control terminal of the third transistor, the second terminal of the resistor coupled to the voltage reference terminal as suggested by Maeland et al_Fig. 5 to effectively make the voltage more stable with temperature.
13. Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Maeland et al_Fig. 6 in view of Imura.
Regarding claim 17, Maeland et al_Fig. 6 discloses the claimed invention except for wherein the second circuit includes: a fourth transistor having first and second terminals and a control terminal, the first terminal of the fourth transistor coupled to the second terminal of the second transistor, the second terminal of the fourth transistor coupled to the control terminal of the third transistor, the control terminal of the fourth transistor coupled to the voltage reference terminal; and a fifth transistor having first and second terminals and a control terminal, the first terminal of the fifth transistor coupled to the second terminal of the fourth transistor and to the control terminals of the third and fifth transistors, the control second terminal of the fifth transistor coupled to the voltage reference terminal.
Imura [e.g., Fig. 11] teaches wherein the second circuit [e.g., constant voltage circuit 50] includes: a fourth transistor having first and second terminals and a control terminal [e.g., NMOS 51], the first terminal of the fourth transistor coupled to the second terminal of the second transistor [e.g., first terminal of NMOS 51 coupled to second terminal of 65e when 66 is conducting], the second terminal of the fourth transistor coupled to the control terminal of the third transistor [e.g., second terminal of NMOS 51 coupled to gate of NMOS 63e], the control terminal of the fourth transistor coupled to the voltage reference terminal [e.g., back gate of NMOS 51 coupled to ground]; and a fifth transistor having first and second terminals and a control terminal [e.g., NMOS 52], the first terminal of the fifth transistor coupled to the second terminal of the fourth transistor and to the control terminals of the third and fifth transistors [e.g., first terminal of NMOS 52 coupled to second terminal of NMOS 51 and to control terminals of 63e and NMOS 51], the control second terminal of the fifth transistor coupled to the voltage reference terminal [e.g., second terminal of NMOS coupled to ground]
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Maeland et al_Fig. 6 with wherein the second circuit includes: a fourth transistor having first and second terminals and a control terminal, the first terminal of the fourth transistor coupled to the second terminal of the second transistor, the second terminal of the fourth transistor coupled to the control terminal of the third transistor, the control terminal of the fourth transistor coupled to the voltage reference terminal; and a fifth transistor having first and second terminals and a control terminal, the first terminal of the fifth transistor coupled to the second terminal of the fourth transistor and to the control terminals of the third and fifth transistors, the control second terminal of the fifth transistor coupled to the voltage reference terminal as suggested by Imura to generate a constant reference voltage within the circuit to improve control and feedback of the reference voltage circuit.
14. Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Maeland et al_Fig. 6 in view of US Pub. No. 2015/0234404 A1; (hereinafter Maeland et al_Fig. 6 and Agarwal et al).
Regarding claim 18, Maeland et al_Fig. 6 discloses wherein the voltage regulator circuit includes a third circuit including: a first current source having first and second terminals [e.g., current source 100], the first terminal of the first current source coupled to the input voltage terminal [e.g., coupled to input voltage Vin], the second terminal of the first current source coupled to the control terminal of the first transistor and to the first terminal of the second transistor [e.g., coupled to M1 and M4].
Maeland et al_Fig. 6 does not disclose a second current source having first and second terminals, the first terminal of the second current source coupled to the second terminal of the third transistor, the second terminal of the second current source coupled to the voltage reference terminal.
Agarwal [e.g., Fig. 2] teaches a second current source having first and second terminals [e.g., current source 278], the first terminal of the second current source coupled to the second terminal of the third transistor [e.g., coupled to transistor 260], the second terminal of the second current source coupled to the voltage reference terminal [e.g., second terminal coupled to ground].
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Maeland et al_Fig. 6 with a second current source having first and second terminals, the first terminal of the second current source coupled to the second terminal of the third transistor, the second terminal of the second current source coupled to the voltage reference terminal as suggested by Agarwal et al to maintain a constant total current flowing in the transistors and to maintain a constant DC bias in the transistors.
15. Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Maeland et al_Fig. 6 in view of Maeland et al_Fig. 10.
Regarding claim 19, Maeland et al_Fig. 6 discloses the claimed invention except for wherein the fourth transistor and the fifth transistor are components of a watchdog circuit.
Maeland et al [e.g., Fig. 10] teaches wherein the fourth transistor and the fifth transistor are components of a watchdog circuit [e.g., paragraph 0094 lines 1-7 recites "Regulator 20 may provide the output voltage VOUT as a supply voltage or other voltage (e.g., a reference voltage, a bias voltage, etc.) to any of the blocks or circuits shown in IC 550. In addition, regulator 20 may provide the output voltage VOUTR as a supply voltage or other voltage (e.g., a reference voltage, a bias voltage, etc.) to any of the blocks or circuits shown in IC 550"].
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Imura with wherein the fourth transistor and the fifth transistor are components of a watchdog circuit as suggested by Maeland et al to allow the circuit to remain powered throughout system operation.
Response to Arguments
16. Applicant's arguments filed 12/15/2025 have been fully considered but they are not persuasive.
Applicant(s) argue(s):
Regarding claim 1, the Office Action stated that NMOS transistor 66 of Imura corresponds to the fourth transistor of claim 1, and NMOS transistor 63e of Imura corresponds to the fifth transistor of claim 1. Id. at p. 5. Applicant respectfully disagrees. As shown in the cited FIG. 11 of Imura (reproduced below), NMOS transistor 66 of Imura is NOT diode-connected, and NMOS transistor 63e of Imura has one current terminal coupled to NMOS transistor 65e (which allegedly corresponds to the second transistor of claim 1) but does NOT have another current terminal coupled to the control terminal of NMOS transistor 51 (which allegedly corresponds to the third transistor of claim 1). Therefore, Imura at least fails to teach that "the fourth transistor is diode- connected, a fifth transistor having two current terminals coupled to the second terminal and the third control terminal, respectively" as recited in claim 1. For at least this reason, Imura fails to teach all features of claim 1. Therefore, claim 1 is patentable over Imura under 35 U.S.C. § 102.
In response, as shown in Imura Fig. 11, it can be seen that a “fourth transistor” (transistor 52 in Imura) is “diode-connected” (gate and drain coupled together). In addition, a fifth transistor (transistor 63e in Imura) it can be seen to have one current terminal (bottom terminal) coupled to “second transistor” (65e) and another current terminal “gate” coupled to control terminal of “fourth transistor” (transistor 52 in Imura) and coupled to “transistor 51 in Imura” via output terminal 30. The examiner interpret the term “current terminal” as any terminal that can allow current to flow i.e., drain, gate and source. Furthermore, the examiner interpret the term “diode-connected” in its broadest sense as a transistor that has 2 of its 3 terminals coupled together since claim lacks specific and detailed description of which terminal of the transistor is connected to which and only recites “diode-connected”. Therefore, the rejection is maintained.
17. Applicant’s arguments with respect to claim(s) 14 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Examiner’s Note
18. Examiner has cited particular paragraphs and line numbers in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figure may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art disclosed by the Examiner.
19. In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Allowable Subject Matter
20. Claims 10 - 12 and 20 - 24 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
21. The following is a statement of reasons for the indication of allowable subject matter:
22. The primary reason for the indication of the allowability of claim 10 is the inclusion therein, in combination as currently claimed as a whole, of the limitation of “… an eighth transistor; and a ninth transistor; in which: the eighth transistor is coupled between the seventh transistor and the ground terminal, the eighth transistor includes an eighth control terminal coupled to the ground terminal; and the ninth transistor is coupled between the second control terminal and the ground terminal, the ninth transistor includes a ninth control terminal coupled to the ground terminal.”
The primary reason for the indication of the allowability of claim 20 is the inclusion therein, in combination as currently claimed as a whole, of the limitation of “… and the second current source includes: an eighth transistor having a first terminal coupled to the second terminal of the third transistor, having a second terminal and having a control terminal; and a ninth transistor having a first terminal coupled to the second and control terminals of the seventh transistor, having a second terminal coupled to the second terminal of the eighth transistor, and having a control terminal coupled to the control terminal of the eighth transistor.”
Conclusion
23. Any inquiry concerning this communication or earlier communications from the examiner should be directed to ULARISLAO CORDOVA whose telephone number is (571)272-4690. The examiner can normally be reached Monday-Friday 7:30 - 5:00 ET.
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/MONICA LEWIS/ Supervisory Patent Examiner, Art Unit 2838
/ULARISLAO CORDOVA/Examiner, Art Unit 2838
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