DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 8 and 21 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yamamoto (US 20170250680).
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With respect to claim 1, figures 3a of Yamamoto (US 20170250680 discloses a circuit comprising: a transistor (SiTr1) coupled between a power input (VDDL) and a power output (OUT), a switch (OSTr2) and a resistor (R2) coupled in series (here OSTr2 is in series with R2) between the power input (at VDDL) and a control terminal of the transistor (at ND2), the resistor being coupled between a first terminal of the switch (at CT2) and the control terminal (at ND2), or between a second terminal of the switch (at ND1) and the power input (VDDL). (Note: as the coupling of the resistor is stated in the alternative either or both of the conditions can be met and read on the claim language.) (Further note between is in the space occupying, here R2 touches VDDL and ND2 touches the control terminal thus leading to OSTr2 and R2 in series and between the power input and control terminal.)
With respect to claim 8, Yamamoto (US 20170250680) discloses a circuit comprising: a transistor (SiTr1) coupled between a power input (VDDL) and a power output (OUT), and a switch (OSTr2) and a resistor (R2) coupled in series between the power input (VDDL) and a control terminal (at ND2) of the transistor (STr1)r, the switch configurable to connect the power input to the control terminal via the resistor (R2) responsive to a control terminal of the switch (VN) having a first state (OFF), and disconnect the power input from the control terminal responsive to the control terminal of the switch having a second state (ON pulled to VSSL).
With respect to claim 21, Yamamoto (US 20170250680) discloses the circuit of claim 1, wherein the switch (SiTr1) is configurable to connect the power input (at VDDL) to the control terminal via the resistor (R2) responsive to a control terminal of the switch having a first state (OFF pulled to VDDL) and disconnect the power input from the control terminal responsive to the control terminal of the switch having a second state (ON pulled to VSSL).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 6 and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yamamoto (US 20170250680) in view of Sardat (US 7737650).
With respect to claim 6, figures 3a of Yamamoto (US 20170250680 discloses the circuit of claim 1, wherein the resistor and the switch have the same current therethrough when the switch is on (when SiTr1 is off and the switch OSTr2 is on the switch OSTr2 and the transistor have the same current running through them as no current is siphoned off to the gate of SiTr1) the transistor is a first transistor (SiTr1), but fails to disclose the circuit further comprises a second transistor coupled between the power input and the power output, a control terminal of the second transistor coupled to a control terminal of the switch.
It is well known in the art to replace a single transistor with multiple transistors in parallel. See for example Sardat figures 1 and 4 (col. 4. Lines 66-67- col. 5. Lines 1-3. It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to replace the single transistor (SiTr1 of Yamamoto) with multiple transistors in parallel as taught by Sardat in figures 1 and 4, for the purpose of increasing power and allowing for higher currents.
The resulting circuit would produce the circuit of claim 6 having a second transistor (transistor in parallel of SiTR1l) coupled between the power input and the power output, with a control terminal of the second transistor coupled to a control terminal of the switch (at ND2).
With respect to claim 14, the circuit above discloses the circuit of claim 8, wherein the resistor and the switch have the same current therethrough when the switch is on (when SiTr1 is off and the switch OSTr2 is on the switch OSTr2 and the transistor have the same current running through them as no current is siphoned off to the gate of SiTr1) the transistor is a first transistor, but fails to disclose the circuit further comprises a second transistor coupled between the power input and the power output, a control terminal of the second transistor coupled to a control terminal of the switch.
It is well known in the art to replace a single transistor with multiple transistors in parallel. See for example Sardat figures 1 and 4 (col. 4. Lines 66-67- col. 5. Lines 1-3. It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to replace the single transistor (SiTr1 of Yamamoto) with multiple transistors in parallel as taught by Sardat in figures 1 and 4, for the purpose of increasing power and allowing for higher currents.
The resulting circuit would produce the circuit of claim 8 having a second transistor (transistor in parallel of SiTR1l) coupled between the power input and the power output, with a control terminal of the second transistor coupled to a control terminal of the switch (at ND2).
Allowable Subject Matter
Claims 2-5, 7, 9-13 and 22-23 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
With respect to claim 2, the prior art fails to suggest or disclose further comprising: a driver circuit having an input coupled to the low-power mode terminal, a high output slew detected input, and a drive output coupled to the control terminal of the first transistor, the driver circuit including: a third transistor having first and second terminals and a control terminal, the first terminal of the third transistor coupled to the drive output, the second terminal of the third transistor couple to a reference terminal, the control terminal of the third transistor coupled to the high output slew detected input.
Here, the third control terminal is not coupled to a slew detected input and the driver does not include a high output slew detected input.
With respect to claim 7, the prior art of record fails to suggest or disclose the circuit of claim 6, further comprising: a fourth transistor coupled between the control terminal of the first transistor and a reference terminal, the fourth transistor having a control terminal coupled to the low-power mode terminal; and a fifth transistor coupled between the control terminal of the third transistor and the reference terminal, the fifth transistor having a control terminal coupled to the low-power mode terminal.
Here the fourth and the fifth transistor control terminals are not connected to the low power mode terminal.
With respect to claim 9, the prior art of record fails to suggest or disclose the circuit of claim 8, further comprising: a driver circuit including a drive output coupled to the control terminal of the first transistor the driver circuit capable of: turning on the first transistor responsive to the low-power mode signal; and turning off the first transistor responsive to the first terminal and the control terminals of the first transistor being electrically coupled and responsive to a slew detect signal.
Here the turn off is not based on a slew detect signal.
With respect to claim 22, the prior art fails to disclose wherein the first transistor is n-type and the second transistor is p-type.
Claims 3-5 are objected to on the basis of their dependence on claim 2.
Claims 10-13 are objected to on the basis of their dependence on claim 9.
Claim 23 is objected to on the basis of its dependence on claim 22.
Claims 15-20 are allowed.
The following is an examiner’s statement of reasons for allowance:
With respect to claim 15, the prior art of record fails to suggest or disclose a circuit comprising: a battery having an output; a load circuit having an input; a controller having a switch enable output; and a high-side switch circuit having a voltage input coupled to the output of the battery, a voltage output, coupled to the input of the load circuit and a control input coupled to the switch enable output the high-side switch circuit including: a first transistor having a first terminal coupled to the voltage input, a second terminal coupled to the voltage output, and a control terminal coupled to the control input; a second transistor and a resistor coupled in series between the first terminal and the control terminal of the first transistor, the second transistor capable of electrically coupling and decoupled the first terminal and the control terminal of the first transistor responsive to a low-power mode signal; and the capable of limiting current flow from the voltage input to the control terminal control terminal of the first transistor.
Here, the high side switch circuit does not have the cited connections in combination with the circuit having a battery as disclosed. Although the module in [0074] of Yamamoto says the module may refer to a battery, the subsequent connections of the battery with respect to the controller and the switch enable input as such are not explicitly disclosed.
Response to Arguments
Applicant's arguments filed 4/29/2026 have been fully considered but they are not persuasive.
With respect to applicant’s argument Examiner alleges that the current path for 3A of Yamamoto is invalid, the Examiner points out no current path is claimed. The coupling is not the same as interpreted by the applicant, yet the coupling reads on the claims asserted by the applicant. Applicant argues R2 and OSTr2 are coupled in series between VDDL and ND1/ VSS! And not coupled in series between VDDL and ND2/ gate of SiTr1, the Examiner disagrees. R2 and OSTr2 are coupled in series between VDDL,and ND1, but also are coupled in series (R2 and CT2) and are between VDDL and the gate of ND3. This interpretation would be both broad and reasonable. As with the specific definition couple is well known but the term “between” introduces the variable claim interpretations.
With respect to 21, OSTr2 would control the switching states of the switch and would allow connections as disclosed.
With respect to claim 8, this is rejected for similar reasons with the unclarity of the introduction of between used by the applicant.
With respect to claim 8 and 14, these claims are coupled as stated. Applicant introduces the new terminology which would be met in the condition of SiTr1 being off, the current would run directly between R2 and OSTr2 with no current being siphoned off. As such, the 103 would be capable of meeting the current limitations. The increased power and higher currents of Sardat would require the same control of the replacing one transistor with transistor in parallel as such the gates would also be coupled. Applicant’s argument concerning the first and second transistors the Examiner points out the second and the switch control terminals would be coupled together wherein the first transistor is apart. As such, the replacement would read on the claimed language.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHAREEM E ALMO whose telephone number is (571)272-5524. The examiner can normally be reached M-F (8:00am-4:00pm).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Menatoallah Youssef can be reached at M-F (8:00am-4:00pm). The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KHAREEM E ALMO/Examiner, Art Unit 2849
/Menatoallah Youssef/SPE, Art Unit 2849
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