DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 1 is objected to because of the following informalities: the limitation “without directly connected” of claims 1 and 10 are grammatically incorrect and should be “without directly connecting”. Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 5-11, 13, 16-18 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chiles et al. (US 2014/0070763).
Regarding claim 1 Chiles discloses:
A noise suppression sheet comprising:
a substrate (e.g. 1002/1004 Fig.10) having a first through hole (e.g. for 1006, paragraphs [0036], [0063]); and
a conductor pattern (e.g. 1003 Fig.10) provided on one surface of the substrate, wherein the conductor pattern has a plurality of linear patterns extending in a first direction (e.g. shown Fig.10) and a connection pattern (e.g. thicker lines excluding 1006 Fig.10) connecting the plurality of linear patterns, wherein the one surface of the substrate has a clearance area surrounded by the plurality of linear patterns and having no conductor pattern (e.g. clear sections shown Fig.10), wherein a size of the clearance area in a second direction different from the first direction is larger than an arrangement pitch between the plurality of linear patterns in the second direction (e.g. shown Fig.10), and wherein the first through hole is formed in the clearance area (e.g. shown Fig.10), wherein the plurality of linear patterns include a plurality of first linear patterns (e.g. between 1006 Fig.10) each of whose positions in the second direction overlaps the clearance area (e.g. shown Fig.10) and has no direct contact with the connection pattern (e.g. shown Fig.10), a second linear pattern (e.g. lines tangent to solid lines around 1006 Fig.10) whose position in the second direction does not overlap the clearance area and is adjacent to one of the plurality of first linear patterns (e.g. shown Fig.10), and a third linear pattern whose position in the second direction does not overlap the clearance area and is adjacent to another of the plurality of first linear patterns (e.g. shown Fig.10), wherein the second linear pattern is adjacent to one of the plurality of first linear patterns belonging to the first group (e.g. shown Fig.10), wherein the third linear pattern is adjacent to one of the plurality of first linear patterns belonging to the second group (e.g. shown Fig.2, Fig.10), wherein the conductor pattern further has a first connection part connecting the first linear patterns belonging to the first group and the second linear pattern and a second connection part connecting the first linear patterns belonging to the second group and the third linear pattern (e.g. shown Fig.2/Fig.10), the first connection part and the second connection part are disposed along an outer periphery of the clearance area (e.g. shown Fig.10), and wherein the first connection part and the second connection part are electrically connected to each other via the second linear pattern (e.g. contacting around/tangential to 1006 Fig.10), the third linear pattern, and the connection pattern without directly connected to each other such that a gag (e.g. between 1006 Fig.2/Fig.10) is formed between the first connection part and the second connection part (e.g. shown Fig.2, Fig.10).
Regarding claim 5 Chiles discloses:
the plurality of linear patterns further include a plurality of fourth linear patterns each of whose one ends in the first direction is connected to the connection pattern (e.g. lines adjacent window shown Fig.10) and each of whose other ends in the first direction is opened (e.g. at the display end, shown in greater detail Fig.2) and a fifth linear pattern whose one end in the first direction protrudes beyond the connection pattern (e.g. plurality of 1003 extending beyond window shown Fig.10) and whose other end in the first direction is opened and protrudes beyond an other end of the fourth liner pattern (e.g. line shown adjacent but not touching 104 Fig.2).
Regarding claim 6 Chiles discloses:
the conductor pattern further includes a terminal conductor (e.g. 1006 Fig.10), and wherein the plurality of linear patterns further include a sixth linear pattern (e.g. 1003 line shown extending from bottom line of 1002 tangent with bottom middle 1006, terminating in top middle 1006 shown Fig.10) whose one end in the first direction is connected to the connection pattern and whose other end in the first direction is connected to the terminal conductor (e.g. shown Fig.10).
Regarding claim 7 Chiles discloses:
a part of the terminal conductor is adjacent to any of the plurality of linear patterns in the second direction (e.g. shown Fig.10).
Regarding claim 8 Chiles discloses:
one edge of the substrate in the first direction protrudes at a part thereof overlapping the terminal conductor (e.g. shown Fig.10).
Regarding claim 9 Chiles discloses:
a communication coil provided on another surface of the substrate (e.g. described paragraph [0063]).
Regarding claim 10 Chiles discloses:
An electric circuit device comprising:
a noise suppression sheet (e.g. 64 Fig.9); and
a power transmission coil (e.g. 72 Fig.9) overlapping the noise suppression sheet, wherein the noise suppression sheet comprising:
a substrate (e.g. 1002/1004 Fig.10) having a first through hole (e.g. for 1006, paragraphs [0036], [0063], 61 Fig.6);
a conductor pattern (e.g. 1003 Fig.10) provided on one surface of the substrate; and
a communication coil (e.g. described paragraphs [0054],[0063]) provided on another surface of the substrate (e.g. on 1004), wherein the conductor pattern (e.g. 1003 Fig.10) has a plurality of linear patterns extending in a first direction (e.g. shown Fig.10) and a connection pattern connecting the plurality of linear patterns (e.g. thicker lines excluding 1006 Fig.10), wherein the one surface of the substrate has a clearance area surrounded by the plurality of linear patterns and having no conductor pattern (e.g. clear sections shown Fig.10), wherein a size of the clearance area in a second direction different from the first direction is larger than an arrangement pitch between the plurality of linear patterns in the second direction (e.g. shown Fig.10), wherein the first through hole is formed in the clearance area (e.g. shown Fig.10), and wherein an opening of the power transmission coil overlaps the first through hole (e.g. shown Fig.10), wherein the plurality of linear patterns include a plurality of first linear patterns (e.g. between 1006 Fig.10) each of whose positions in the second direction overlaps the clearance area (e.g. shown Fig.10) and has no direct contact with the connection pattern (e.g. shown Fig.10), a second linear pattern (e.g. lines tangent to solid lines around 1006 Fig.10) whose position in the second direction does not overlap the clearance area and is adjacent to one of the plurality of first linear patterns (e.g. shown Fig.10), and a third linear pattern whose position in the second direction does not overlap the clearance area and is adjacent to another of the plurality of first linear patterns (e.g. shown Fig.10), wherein the second linear pattern is adjacent to one of the plurality of first linear patterns belonging to the first group (e.g. shown Fig.10), wherein the third linear pattern is adjacent to one of the plurality of first linear patterns belonging to the second group (e.g. shown Fig.2, Fig.10), wherein the conductor pattern further has a first connection part connecting the first linear patterns belonging to the first group and the second linear pattern and a second connection part connecting the first linear patterns belonging to the second group and the third linear pattern (e.g. shown Fig.2/Fig.10), the first connection part and the second connection part are disposed along an outer periphery of the clearance area (e.g. shown Fig.10), and wherein the first connection part and the second connection part are electrically connected to each other via the second linear pattern (e.g. contacting around/tangential to 1006 Fig.10), the third linear pattern, and the connection pattern without directly connected to each other such that a gag (e.g. between 1006 Fig.2/Fig.10) is formed between the first connection part and the second connection part (e.g. shown Fig.2, Fig.10).
Regarding claim 11 Chiles discloses:
a magnetic member (e.g. 84 Fig.8) disposed on a side opposite to the substrate with respect to the power transmission coil (e.g. 64 Fig.9), wherein the magnetic member has a second through hole overlapping the first through hole (e.g. overlapping middle 61 Fig.6/Fig.7).
Regarding claim 13 Chiles discloses:
the clearance area has a shape conforming to the shape of an opening of the power transmission coil (e.g. circular shown Fig.7/Fig.10).
Regarding claim 16 Chiles discloses:
the plurality of linear patterns further include a plurality of fourth linear patterns (e.g. lines adjacent window shown Fig.10) each of whose positions in the second direction overlaps the clearance area and directly contacted to the connection pattern (e.g. shown FIG.10), and wherein the plurality of first linear patterns and the plurality of fourth linear patterns are arranged in the first direction (e.g. shown Fig.2, Fig.10).
Regarding claim 17 Chiles discloses:
each of the plurality of fourth linear patterns has a first end connected to the connection pattern (e.g. shown Fig.2/Fig.10) and a second end terminated at the outer periphery of the clearance area without connected to the first and second connection parts (e.g. shown Fig.2/Fig.10).
Regarding claim 18 Chiles discloses:
a length of one of the plurality of first linear patterns in the first direction is a same as a length of one of the plurality of fourth linear patterns in the first direction (e.g. shown between 104 and 110 Fig.2, shown in upper and lower right hand corners of FIG.10)
(drawing objection all first linear patterns are shown to be half the length of fourth linear patterns)
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chiles et al. (US 2014/0070763) in view of II (US 2020/0286680).
Regarding claim 12 Chiles discloses:
The electric circuit device as claimed in claim 11
Chiles does not explicitly disclose:
the second through hole is smaller in size than the first through hole
II teaches:
the second through hole (e.g. within A3,M5 FIG.2) is smaller in size than the first through hole (e.g. within A1, M1 FIG.2).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have utilized the teachings of II as pointed out above, in Chiles, as one having ordinary skill in the art would have would have recognized the teaching, suggestion, and motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings (as pointed out above) to arrive at the claimed invention, and would have been motivated to do this with a reasonable expectation of success because such a combination and/or modification would have allowed for: “the coil unit can inhibit the magnetic body from reaching an overheated state while the amount of the magnetic body used is reduced” (paragraph [0083]).
Claim(s) 14, 15, 19, 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chiles et al. (US 2014/0070763) in view of SAKAI et al. (US 2022/0295637).
Regarding claim 14 Chiles discloses:
The noise suppression sheet as claimed in claim 1,
Chiles does not explicitly disclose:
wherein the first through hole is formed at substantially a center of the substrate
SAKAI teaches:
wherein the first through hole (e.g. 20 FIG.2) is formed at substantially a center of the substrate (e.g. shown FIG.2).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have utilized the teachings of SAKAI as pointed out above, in Chiles, as one having ordinary skill in the art would have would have recognized the teaching, suggestion, and motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings (as pointed out above) to arrive at the claimed invention, and would have been motivated to do this with a reasonable expectation of success because such a combination and/or modification would have allowed for: “excellent in the connection reliability and a method of manufacturing the same” (paragraph [0014]).
Regarding claim 15 Chiles discloses:
The noise suppression sheet as claimed in claim 14,
Chiles does not explicitly disclose:
wherein the first through hole is only through hole formed in the substrate
SAKAI teaches:
wherein the first through hole is only through hole formed in the substrate (e.g. shown FIG.2).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have utilized the teachings of SAKAI as pointed out above, in Chiles, as one having ordinary skill in the art would have would have recognized the teaching, suggestion, and motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings (as pointed out above) to arrive at the claimed invention, and would have been motivated to do this with a reasonable expectation of success because such a combination and/or modification would have allowed for: “excellent in the connection reliability and a method of manufacturing the same” (paragraph [0014]).
Regarding claim 19 Chiles discloses:
A noise suppression sheet comprising:
a conductor pattern (e.g. dark lines FIG.10) provided on one surface of the substrate (e.g. 1004 Fig.10), wherein the conductor pattern has a plurality of linear patterns extending in a first direction (e.g. shown Fig.10) and a connection pattern connecting the plurality of linear patterns (e.g. shown Fig.10), wherein the one surface of the substrate has a clearance area (e.g. clear sections shown Fig.10) surrounded by the plurality of linear patterns and having no conductor pattern, wherein a size of the clearance area in a second direction different from the first direction is larger than an arrangement pitch between the plurality of linear patterns in the second direction (e.g. shown Fig.10), and wherein the first through hole is formed in the clearance area (e.g. shown through 1006 Fig.10).
Chiles does not explicitly disclose:
a substrate having a first through hole formed at substantially a center thereof
SAKAI teaches:
a substrate having a first through hole formed at substantially a center thereof (e.g. shown FIG.2).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have utilized the teachings of SAKAI as pointed out above, in Chiles, as one having ordinary skill in the art would have would have recognized the teaching, suggestion, and motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings (as pointed out above) to arrive at the claimed invention, and would have been motivated to do this with a reasonable expectation of success because such a combination and/or modification would have allowed for: “excellent in the connection reliability and a method of manufacturing the same” (paragraph [0014]).
Regarding claim 20 Chiles discloses:
The noise suppression sheet as claimed in claim 19,
Chiles does not explicitly disclose:
wherein the first through hole is only through hole formed in the substrate
SAKAI teaches:
wherein the first through hole is only through hole formed in the substrate (e.g. shown FIG.2).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have utilized the teachings of SAKAI as pointed out above, in Chiles, as one having ordinary skill in the art would have would have recognized the teaching, suggestion, and motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings (as pointed out above) to arrive at the claimed invention, and would have been motivated to do this with a reasonable expectation of success because such a combination and/or modification would have allowed for: “excellent in the connection reliability and a method of manufacturing the same” (paragraph [0014]).
Response to Arguments
Applicant's arguments filed 2026-03-25 have been fully considered but they are not persuasive.
The rejection above points out where the art already of record discloses the argued limitations added in amendment. In addition it is unclear how whether or not the elements of the prior art form a perfect circle is relevant to the current claims of record as no circle, perfect or otherwise, is recited in the claims and limitations from the specification will not be read into the claims (MPEP 2111), although no “perfect circle” is recited in the disclosure of the present application and so it is unclear how the argument is relevant in the present case.
Applicant’s arguments with respect to the claim(s) reciting limitations regarding through hole(s) have been considered but are moot because the new grounds of rejection does not rely on any combination of references applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Any/all remaining arguments are addressed either in the body of the rejection above or in the response above and so will not be repeated here.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to THERON S MILLISER whose telephone number is (571)270-1800. The examiner can normally be reached 9-6.
Limited examiner interviews are available.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Imani N. Hayman can be reached at (571) 270-5528. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/THERON S MILLISER/Examiner, Art Unit 2841
/IMANI N HAYMAN/Supervisory Patent Examiner, Art Unit 2841
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