DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Allowable Subject Matter
The indicated allowability of claims 5-8 is withdrawn in view of the newly discovered reference(s) to Kajino (JP2013197509A) and Takeuchi (JP2005251993A). Rejections based on the newly cited reference(s) follow.
Claim 7 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 5 and 6 are rejected under 35 U.S.C. 102(a)(1) as anticipated by Kajino.
Kajino discloses the claimed invention as follows:
Claim 5. A multilayer varistor1 comprising:
a sintered compact (4; see Fig. 3 and 4; see [0017] and [0026]);
an internal electrode (3) provided inside the sintered compact;
a high-resistivity layer (5) arranged to cover the sintered compact at least partially; and
an external electrode (6 with 7) arranged to cover the high-resistivity layer partially and electrically connected to the internal electrode, wherein:
the high-resistivity layer includes a thinner region (5b as seen in Fig. 2, but at the transition between the area covered by the external electrode and the rest of the compact) having a smaller thickness than a surrounding region that surrounds the thinner region, and
the thinner region has an opening (left/right face portions as seen in Fig. 4) exposing a part of the sintered compact underlying the high-resistivity layer, and the sintered compact includes an exposed portion exposed2 through the opening.
Claim 6. The multilayer varistor of claim 5, wherein the exposed portion is surrounded with the thinner region. See footnote 2. The window formed in the glass layer 5 when firing the base electrodes 6 is surrounded by glass layer 5 having thinner portions 5b, i.e. essentially the same view as that of Fig. 2, except being the component viewed from the left/right in Fig. 3, 4 and with the terminals omitted for clarity.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kajino in view of Takeuchi.
Kajino discloses the claimed invention as follows:
Claim 8. A multilayer varistor (see footnote 1) comprising:
a sintered compact (4);
an internal electrode (3) provided inside the sintered compact;
a high-resistivity layer (5) arranged to cover the sintered compact at least partially; and
an external electrode (6 with 7) arranged to cover the high-resistivity layer partially and electrically connected to the internal electrode (see Figs. 3 and 4), wherein:
the high-resistivity layer includes a thinner region (5b) having a smaller thickness than a surrounding region (5a) that surrounds the thinner region, and
the high-resistivity layer has an arithmetic mean surface roughness equal to or 3.
Kajino does not disclose the arithmetic mean surface roughness being no less than 0.06 µm.
Takeuchi discloses a chip-type electronic component such as a varistor (see [0001]) having a body 1 with internal electrodes 2, 3, and external terminals 4, 5. In order to avoid plating elongation when plating terminal electrodes, but also in order to avoid the extra step of covering the component with glass (see [0007]), Takeuchi teaches polishing the body 1 to a roughness 0.1 μm≦Ra (see [0045]-[0047]). Depending on the minimum radius of curvature of the corners, relative to the component width W, the upper bound for Ra should be 0.5 µm, 0.6 µm or 2.0 µm, as described in [0045]-[0047]. For example, if the radius of curvature is smaller, as described in [0045] and [0046], then the upper bound for Ra is also lower. Takeuchi explains that a roughness of 0.05 µm is not desirable, because this results in poor adhesion when the silver electrode paste is baked, and the terminal electrode peels off during nickel plating (see [0044]).
In view of the teachings of Takeuchi, one of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to keep the roughness of the glass layer 5 of Kajino to at least 0.1 µm, as one of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious that the same negative effect of high smoothness may also occur with a glass layer, when baking base electrode 6. Additionally, such low roughness requires extra polishing, which would negatively impact production throughput.
Further, if Applicant disagrees Kajino anticipates the claimed upper bound of 0.9 µm for the roughness, this value is, nevertheless, deemed obvious in view of the prior art. Kajino gives an example with components having width of 500 µm (see 0.5 mm in [0058]), and also teaches the radius of curvature of the side surfaces (i.e. the edges) between 10 and 50 µm, though greater radius of curvature results in less effective volume of the functional portion (see [0030]). The ratio of the corner radius to the width is then between 10/500 and 50/500, i.e. 0.02 to 0.1. From [0045] to [0047] of Takeuchi. Based on the teachings of Kajino, one of ordinary skill in the art before the effective filing date of the claimed invention would have found obvious the claimed roughness value of 0.9 µm or less, in order to avoid plating elongation during plating of the terminals, since the ranges disclosed by Takeuchi overlap with the claimed range, for a certain range of values for the radius of curvature of the side portions. For example, for a component with a ratio of radius of curvature to component width of 0.05, Kajino teaches the thickness should be no less than 0.6 µm (see [0046]).
Response to Arguments
Applicant’s arguments have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
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/LIVIUS R. CAZAN/Primary Examiner, Art Unit 3729
1 see [0001] mentioning the invention relates to ceramic electronic component having a body mainly composed of ceramic, and [0002] giving multilayer chip varistors as an example. [0018] and [0021] further mention element body 2 and the case the component is a varistor.
2 Glass layers are formed on all surfaces of the compact 4 (see [0024] and [0040]). Face portions have thicker glass layer 5a (see [0025], preferably 2 µm or less and more than 0.1 µm (see [0037]-[0039], and side (edge) portions have thinner glass layer 5b (see Fig. 2 and [0025]), which is most preferably between 0.1 and 0.4 times the thickness of glass layer 5a, i.e. 0.2 to 0.8 µm, if layer 5a is 2 µm. See [0024]: when firing the metal paste for forming the base electrode 6, the glass diffuses into the base electrode 6, and conduction between base electrode 6 and internal electrodes 3 is ensured. It is readily apparent this means an opening is formed in the glass layer 5 at each of the two ends, where the base electrodes 6 are formed, whereby the compact 4 is exposed to the base electrodes 6.
3 Given that layer 5a is between 0.1 and 2 µm thick, the roughness value cannot be greater than the thickness of the layer, and more specifically cannot be more than half the thickness of the layer. The arithmetic mean roughness is calculated measuring the deviations of peaks and valleys from a centerline, and the layer itself must also have some thickness, i.e. it cannot be all roughness. Therefore, one of ordinary skill in the art would have found it readily apparent that for a 2 µm thick layer, the arithmetic mean surface roughness is necessarily less than 0.9 µm. Moreover, for thickness values of less than 1.8 µm, the surface roughness is inherently no more than 0.9 µm.