DETAILED ACTION
This office action is in response to the RCE filed on 10/22/2025. Claims 1-21 are pending, of which claims 1-6, 8-19 are amended, claims 7 and 20 are cancelled, and claim 21 is newly added by the current amendment.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-6, 8-19, 21 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Liu et al. (IEEE_A Transient-Enhanced Fully-Integrated LDO Regulator for SoC Application, hereinafter Liu).
Claim 1, Liu teaches an apparatus (e.g., the LDO, see Fig. 3), comprising:
a first transistor (e.g., Mp) having first and second terminals and a control terminal, the first terminal of the first transistor coupled to a power input (e.g., Vin, see Fig. 3); a second transistor (e.g., M1) having first and second terminals and a control terminal, the first terminal of the second transistor coupled to the second terminal of the first transistor (e.g., at Vout), the second terminal of the second transistor coupled to the control terminal of the first transistor (e.g., drain of M1 coupled to the gate of Mp through M2, M3/M4); an amplifier (e.g., Error Amplifier) having a first input (e.g., Vfb), a reference input (e.g., Vref), and an output (e.g., Vo), the first input coupled to the second terminal of the first transistor (e.g., Vo of the Error Amplifier coupled to Vout of Mp through R1/Cf), the output coupled to the control terminal of the second transistor (e.g., see Fig. 3).
Claim 2, Liu teaches the limitations of claim 1 as discussed above. It further teaches that further comprising: a third transistor (e.g., M2) having first (e.g., D of M2) and second terminals (e.g., S of M2), the first terminal of the third transistor coupled to the second terminal of the second transistor (e.g., See Fig. 3); a fourth transistor (M3/M4) having first (e.g., D of M3) and second terminals (e.g., S of M3 OR D of M4) and a control terminal (e.g., G of M3), the control terminal of the fourth transistor coupled to the second terminal of the third transistor, the first terminal of the fourth transistor coupled to the first terminal of the first transistor and the second terminal of the third transistor, the second terminal of the fourth transistor (e.g., S of M3) coupled to the control terminal of the first transistor (e.g., see Fig. 3); and a resistor (e.g., R1) having a first terminal and a second terminal, the first terminal coupled to the second terminal of the first transistor and to the first terminal of the second transistor (e.g., see Fig. 3), wherein the first terminal of the first transistor is a source terminal or a emitter terminal, the first terminal of the fourth transistor is a drain terminal or a collector terminal, the second terminal of the first transistor is a drain terminal or a collector terminal, and the first terminal of the second transistor is a source terminal or an emitter terminal (e.g., see Fig. 3).
Claim 3, Liu teaches the limitations of claim 2 as discussed above. It further teaches that wherein the second terminal of the second transistor is a drain terminal or a collector terminal, the first terminal of the third transistor is a source terminal or an emitter terminal (e.g., see Fig. 3), and the apparatus further comprises a current source (e.g., the circuits comprising IB3, Rb4, M4) coupled to the second terminal of the second transistor and the first terminal of the third transistor (e.g., see Fig. 3).
Claim 4, Liu teaches the limitations of claim 2 as discussed above. It further teaches that wherein the first terminal of the fourth transistor (M3/M4) is a drain terminal (e.g., D of M4) or a collector terminal, the second terminal of the fourth transistor is a source terminal (e.g., S of M3) or an emitter terminal, the first terminal of the first transistor is a source terminal (e.g., S of Mp) or an emitter terminal, and the apparatus further comprises a current source coupled to the second terminal of the fourth transistor (e.g., see Fig. 3).
Claim 5, Liu teaches the limitations of claim 2 as discussed above. It further teaches that further comprising: a fifth transistor (e.g., the PMOS transistor(s) having its gate connected directly with Vb2) having first and second terminals, the first terminal of the fifth transistor coupled to the power input, the second terminal of the fifth transistor coupled to the first terminal of the first transistor (e.g., both terminals D and S of the PMOS transistor(s) having its gate connected directly with Vb2 coupled to Vin and the first terminal of Mp, see Fig. 3).
Claim 6, Liu teaches the limitations of claim 2 as discussed above. It further teaches that further comprising a resistor capacitor network (e.g., R1/Cf) coupled between the control terminal of the fourth transistor and the first terminal of the third transistor (e.g., coupled through Mp and M1, see Fig. 3).
Claim 8, Liu teaches an apparatus (e.g., the LDO, see Fig. 3), comprising: first transistor (e.g., Mp) coupled between a power input (e.g., Vin) and a power output (e.g., Vout), the first transistor having a control terminal (e.g., the gate of Mp, see Fig. 3); a second transistor (e.g., M1) coupled between the power output and a terminal (e.g., drain of M1), the terminal coupled to the control terminal of the first transistor (e.g., coupled through M2, M3/M4); and an amplifier (e.g., Error Amplifier) having a first input (e.g., Vfb), a reference input (e.g., Vref), and an output (e.g., Vo), the first input of the amplifier coupled to the terminal (e.g., through through R1/Cf), and the output of the amplifier coupled to the control terminal of the second transistor (e.g., see Fig. 3).
Claim 9, Liu teaches the limitations of claim 8 as discussed above. It further teaches that further comprising: a third transistor (e.g., M2) coupled between the power input and the control terminal of the first transistor (e.g., see Fig. 3); a fourth transistor (M3/M4) coupled between a control terminal of the third transistor and the terminal (e.g., see Fig. 3); and a resistor (e.g., R1) coupled between respective terminals of the first and second transistors and the power output (e.g., see Fig. 3).
Claim 10, Liu teaches the limitations of claim 9 as discussed above. It further teaches that further comprising a fifth transistor (e.g., the PMOS transistor(s) having its gate connected directly with Vb2) coupled between the power input and the power output, a control terminal of the fifth transistor coupled to the control terminal of the first transistor, and the resistor is coupled between respective terminals of the fifth transistor and the first transistor (e.g., see Fig. 3).
Claim 11, Liu teaches the limitations of claim 9 as discussed above. It further teaches that further comprising a first current source (e.g., Ib3) coupled to the terminal and a second current source (e.g., Ib1, see Fig. 3) coupled to a current terminal of the third transistor.
Claim 12, Liu teaches the limitations of claim 8 as discussed above. It further teaches that further comprising: a third transistor (e.g., M2) coupled between the power input and the first transistor (e.g., see Fig. 3).
Claim 13, Liu teaches the limitations of claim 9 as discussed above. It further teaches that, further comprising a resistor capacitor network (e.g., R1/Cf) coupled between the control terminal of the third transistor and the power input (e.g., coupled through Mp and M1, see Fig. 3).
Claim 14, Liu teaches the limitations of claim 9 as discussed above. It further teaches that wherein resistor is a first resistor, and the apparatus further comprises a resistor (e.g., RB2) coupled between the control terminal of the third transistor M2 and the power input (e.g., coupled between Vin and the gate of M2 through the Drain of M2, see Fig. 3).
Claim 15, Liu teaches the limitations of claim 8 as discussed above. It further teaches that wherein the amplifier is a transconductance amplifier (e.g., the output of the Error Amplifier being function of gmEA, see Fig. 3, 4).
Claim 16, Liu teaches an apparatus (e.g., see Fig. 3, 4), comprising: a voltage regulator including: a first amplifier (e.g., the Error Amplifier) having a first input (e.g., the input of the Error Amplifier connected to Vref), a second input (e.g., the input of the Error Amplifier or gmEA directly connected to Vfb), and an output (e.g., Vo), the first input of the first amplifier coupled to a reference terminal (e.g., Vref), and the second input coupled to an output of the voltage regulator (e.g., coupled to Vout through through R1/Cf); a second amplifier having a first input Mc (e.g., the gate of M1), a second input (e.g., the Source of M1), and an output 242/106 (e.g., the Drain of Mp), the first input of the second amplifier coupled to the output of the first amplifier, the second input and the output of the second amplifier coupled to the output of the voltage regulator (e.g., see Fig. 3, 4).
Claim 17, Liu teaches the limitations of claim 16 as discussed above. It further teaches that wherein the second amplifier includes a first transistor 202 (e.g., Mp) coupled between a power input and the output of the voltage regulator, and a second transistor 204 (e.g., M1) coupled between the output of the voltage regulator and a terminal (e.g., the node V1), a control terminal (e.g., gate of Mp) of the first transistor coupled to the second input of the second amplifier and to the terminal (e.g., see Fig. 3), and a control terminal of the second transistor (e.g., gate of M1) coupled to the output of the first amplifier via the first input of the second amplifier (e.g., see Fig. 3).
Claim 18, Liu teaches the limitations of claim 17 as discussed above. It further teaches that wherein the second amplifier further comprises: a third transistor (e.g., M2) coupled between the power input and the control terminal of the first transistor (e.g., see Fig. 3); a fourth transistor (M3/M4) coupled between the control terminal of the first transistor and the terminal; a first current source (e.g., Ib3) coupled to the terminal (e.g., see Fig. 3); and a second current source (e.g., Ib1, see Fig. 3) coupled to a current terminal of the third M2 transistor.
Claim 19, Liu teaches the limitations of claim 16 as discussed above. It further teaches that further comprising a resistor (e.g., R1/R2) coupled between the output of the second amplifier and the output of the voltage regulator (e.g., see Fig. 3).
Claim 21, Liu teaches the limitations of claim 18 as discussed above. It further teaches that wherein the second amplifier further comprises: a fifth transistor (e.g., the PMOS transistor(s) having its gate connected directly with Vb2) coupled between the power input and the output of the voltage regulator, a control terminal of the fifth transistor coupled to the control terminal of the first transistor (e.g., both terminals D and S of the PMOS transistor(s) having its gate connected directly with Vb2 coupled to Vin and the first terminal of Mp, see Fig. 3); and a resistor (e.g., Rb2) coupled between respective terminals of the first and fifth transistor (e.g., see Fig. 3).
Response to Argument
Applicant's arguments filed on 10/22/2025 have been fully considered but are moot in view of the new ground of rejections necessitated by Applicant's current amendment.
Examiner's Note:
Examiner has cited particular columns and line numbers in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner.
In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JUE ZHANG whose telephone number is (571)270-1263. The examiner can normally be reached on M-F: 8:30AM-5:00PM
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Monica Lewis can be reached on 571-272-2838. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/JUE ZHANG/
Primary Examiner, Art Unit 2838