DETAILED ACTION
This office action is in response to the amendment filed on 05/06/2026. Claims 1-6, 8-19, and21 are pending, of which claims 1-2, 4-6, 8-14, and 21 are amended, claim 17 is cancelled, and claims 22-23 are newly added by the current amendment.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-6, 8-16, 18-19, 21-23 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Liu et al. (IEEE_A Transient-Enhanced Fully-Integrated LDO Regulator for SoC Application, hereinafter Liu).
Claim 1, Liu teaches an apparatus (e.g., the LDO, see Fig. 3), comprising: a first transistor (e.g., Mp) having first (e.g., S of Mp) and second (e.g., D of Mp) terminals and a control terminal (e.g., G of Mp), the first terminal (e.g., S of Mp) of the first transistor coupled to a power input (e.g., Vin, see Fig. 3); a second transistor (e.g., M1) having first (e.g., source and M1) and second (e.g., D of M1) terminals (e.g., source and gate of M1 respectively) and a control terminal (e.g., G of M1), the first terminal of the second transistor (e.g., source of M1) coupled to the second terminal (e.g., D of Mp) of the first transistor (e.g., at Vout); an amplifier (e.g., Error Amplifier) having a first input (e.g., Vfb), a reference input (e.g., Vref), and an output (e.g., Vo), the first input coupled to the second terminal of the first transistor (e.g., Input Vfb of the Error Amplifier coupled to Vout of Mp through R1/Cf), the output coupled to the control terminal of the second transistor (e.g., see Fig. 3); a third transistor (e.g., M2) having first and second terminals, the first terminal (e.g., source of M2) of the third transistor coupled to the second terminal (e.g., drain of M1) of the second transistor; and a fourth transistor (e.g., M3/M4) coupled between the first terminal and the control terminal of the first transistor and having first and second terminals and a control terminal, the control terminal (e.g., Gate of M3) of the fourth transistor coupled to the second terminal (e.g., D of M2) of the third transistor, the first terminal (e.g., S of M3) of the fourth transistor coupled to the first terminal (e.g., Source of Mp) of the first transistor (e.g., the gate and drain of M3 coupled to Vin through Rb2 and Ib3 respectively, and through drain of M4 coupled to Vin through Ib3 and gate of M4 coupled to Vin through M3 and Rb2 or Ib3 respectively, see Fig. 3), and the second terminal (e.g., Drain of M4) of the fourth transistor coupled to the control terminal of the first transistor (e.g., the gate and drain of M3 coupled to Vin through Rb2 and Ib3 respectively, and through drain of M4 coupled to Vin through Ib3 and gate of M4 coupled to Vin through M3 and Rb2 or Ib3 respectively, see Fig. 3).
Claim 2, Liu teaches the limitations of claim 1 as discussed above. It further teaches that further comprising: a resistor (e.g., R1) having a first terminal and a second terminal, the first terminal coupled to the second terminal of the first transistor and to the first terminal of the second transistor (e.g., see Fig. 3), wherein the first terminal of the first transistor is a source terminal or a emitter terminal, the first terminal of the fourth transistor is a drain terminal or a collector terminal, the second terminal of the first transistor is a drain terminal or a collector terminal, and the first terminal of the second transistor is a source terminal or an emitter terminal (e.g., see Fig. 3).
Claim 3, Liu teaches the limitations of claim 2 as discussed above. It further teaches that wherein the second terminal of the second transistor is a drain terminal or a collector terminal, the first terminal of the third transistor is a source terminal or an emitter terminal (e.g., see Fig. 3), and the apparatus further comprises a current source (e.g., the circuits comprising IB3, Rb4, M4) coupled to the second terminal of the second transistor and the first terminal of the third transistor (e.g., see Fig. 3).
Claim 4, Liu teaches the limitations of claim 2 as discussed above. It further teaches that wherein the second terminal of the fourth transistor is a source terminal (e.g., S of M3) or an emitter terminal, and the apparatus further comprises a current source coupled to the second terminal of the fourth transistor (e.g., see Fig. 3).
Claim 5, Liu teaches the limitations of claim 2 as discussed above. It further teaches that further comprising: a fifth transistor (e.g., the PMOS transistor(s) having its gate connected directly with Vb2) having first and second terminals, the first terminal of the fifth transistor coupled to the power input, and the second terminal of the fifth transistor coupled to the first terminal of the first transistor (e.g., both terminals D and S of the PMOS transistor(s) having its gate connected directly with Vb2 coupled to Vin and the first terminal of Mp, see Fig. 3).
Claim 6, Liu teaches the limitations of claim 2 as discussed above. It further teaches that further comprising a resistor capacitor network (e.g., R1/Cf) coupled between the control terminal of the fourth transistor and the first terminal of the fourth transistor (e.g., coupled through Mp and M1, see Fig. 3).
Claim 8, Liu teaches an apparatus (e.g., the LDO, see Fig. 3), comprising:
first transistor (e.g., Mp) coupled between a power input (e.g., Vin) and a power output (e.g., Vout), the first transistor having a control terminal (e.g., the gate of Mp, see Fig. 3); a second transistor (e.g., M1) coupled between the power output and a terminal (e.g., V1 between Vout and the drain of M1); an amplifier (e.g., Error Amplifier) having a first input (e.g., Vfb), a reference input (e.g., Vref), and an output (e.g., Vo), the first input of the amplifier coupled to the power output (e.g., coupled to Vfb through R1/Cf), and the output of the amplifier coupled to the control terminal of the second transistor (e.g., see Fig. 3); a third transistor (e.g., M3/M4) coupled between the power input and the control terminal of the first transistor (Gate and Source of M3 coupled to Vin through Rb2 and Ib3 respectively, and Source of M3 and Drain of M4 coupled to Gate of Mp, see Fig. 3); and a fourth transistor (e.g., M2) coupled between a control terminal of the third transistor and the terminal (e.g., M2 coupled between gate of M3 and node V1, see Fig. 3).
Claim 9, Liu teaches the limitations of claim 8 as discussed above. It further teaches that further comprising: a resistor (e.g., R1) coupled between respective terminals of the first and second transistors and the power output (e.g., see Fig. 3).
Claim 10, Liu teaches the limitations of claim 9 as discussed above. It further teaches that further comprising a fifth transistor (e.g., the PMOS transistor(s) having its gate connected directly with Vb2) coupled between the power input and the power output, a control terminal of the fifth transistor coupled to the control terminal of the first transistor; and a resistor (e.g., Rb2) coupled between respective terminals of the fifth transistor and the first transistor (e.g., see Fig. 3).
Claim 11, Liu teaches the limitations of claim 8 as discussed above. It further teaches that further comprising a first current source (e.g., Ib3) coupled to the terminal and a second current source (e.g., Ib1, see Fig. 3) coupled to a current terminal of the third transistor.
Claim 12, Liu teaches the limitations of claim 8 as discussed above. It further teaches that further comprising: a fifth transistor (e.g., the PMOS transistor(s) having its gate connected directly with Vb2) coupled between the power input and the first transistor (e.g., see Fig. 3).
Claim 13, Liu teaches the limitations of claim 8 as discussed above. It further teaches that, further comprising a resistor capacitor network (e.g., R1/Cf) coupled between the control terminal of the third transistor and the power input (e.g., coupled through Mp and M1, see Fig. 3).
Claim 14, Liu teaches the limitations of claim 9 as discussed above. It further teaches that wherein the resistor is a first resistor, and the apparatus further comprises a second resistor (e.g., RB2) coupled between the control terminal of the third transistor M2 and the power input (e.g., coupled between Vin and the gate of M2 through the Drain of M2, see Fig. 3).
Claim 15, Liu teaches the limitations of claim 8 as discussed above. It further teaches that wherein the amplifier is a transconductance amplifier (e.g., the output of the Error Amplifier being function of gmEA, see Fig. 3, 4).
Claim 16, Liu teaches an apparatus (e.g., see Fig. 3, 4), comprising:
a voltage regulator including: a first amplifier (e.g., the Error Amplifier) having a first input (e.g., the input of the Error Amplifier connected to Vref), a second input (e.g., the input of the Error Amplifier or gmEA directly connected to Vfb), and an output (e.g., Vo), the first input of the first amplifier coupled to a reference terminal (e.g., Vref), and the second input coupled to an output of the voltage regulator (e.g., coupled to Vout through R1/Cf); a second amplifier having a first input Mc (e.g., the gate of M1), a second input (e.g., the Source of M1), and an output 242/106 (e.g., the Drain of Mp), the first input of the second amplifier coupled to the output of the first amplifier, the second input of the second amplifier coupled to a power input (e.g., coupled to Vin through the PMOS transistor(s) having its gate connected directly with Vb2), and the output of the second amplifier coupled to the output of the voltage regulator (e.g., see Fig. 3, 4), the second amplifier including: a first transistor (e.g., Mp) coupled between the power input and the output of the voltage regulator; a second transistor (e.g., M1) coupled between the output of the voltage regulator and a terminal (e.g., the node V1), a control terminal of the second transistor coupled to the first input of the second amplifier (e.g., Vfb through R1/Cf and M1, see Fig. 3); a third transistor (e.g., M3/M4) coupled between the power input and a control terminal of the first transistor (e.g., Gate and Source of M3 coupled to Vin through Rb2 and Ib3 respectively, and Source of M3 and Drain of M4 coupled to Gate of Mp, see Fig. 3); and a fourth transistor (e.g., M2) coupled between a control terminal of the third transistor and the terminal (e.g., M2 coupled between gate of M3 and node V1, see Fig. 3).
Claim 18, Liu teaches the limitations of claim 16 as discussed above. It further teaches that wherein the second amplifier further comprises: a first current source (e.g., Ib3) coupled to the terminal (e.g., see Fig. 3); and a second current source (e.g., Ib1, see Fig. 3) coupled to a current terminal of the third transistor (e.g., see Fig. 3).
Claim 19, Liu teaches the limitations of claim 16 as discussed above. It further teaches that further comprising a resistor (e.g., R1/R2) coupled between the output of the second amplifier and the output of the voltage regulator (e.g., see Fig. 3).
Claim 21, Liu teaches the limitations of claim 16 as discussed above. It further teaches that wherein the second amplifier further comprises: a fifth transistor (e.g., the PMOS transistor(s) having its gate connected directly with Vb2) coupled between the power input and the output of the voltage regulator, a control terminal of the fifth transistor coupled to the control terminal of the first transistor (e.g., both terminals D and S of the PMOS transistor(s) having its gate connected directly with Vb2 coupled to Vin and the first terminal of Mp, see Fig. 3); and a resistor (e.g., R1) coupled between a terminal of the fifth transistor and the output of the voltage regulator (e.g., R1 coupled between the terminals D of the PMOS transistor(s) having its gate connected directly with Vb2 through Vfb and Vout, see Fig. 3).
Claim 22, Liu teaches the limitations of claim 21 as discussed above. It further teaches that wherein the resistor is a first resistor, and the second amplifier further comprises a second resistor (e.g., Rb2) coupled between the fifth transistor and the power input (e.g., see Fig. 3).
Claim 23, Liu teaches the limitations of claim 16 as discussed above. It further teaches that wherein the second amplifier further comprises a resistor capacitor network (e.g., R1/Cf, see Fig. 3) coupled between the control terminal of the third transistor and the power input.
Response to Arguments
Applicants’ arguments in the remarks filed on 02/26/2018 have been considered have been fully considered and please see the examiner's responses for the reasons as discussed below.
Applicants stated on page 7 of the REMARKS:
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572
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570
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Examiner's Response:
Applicant's above arguments have been fully considered but they are not persuasive. Examiner would like to respectfully remind Applicant that M3/M4 do coupled to the Vin, for example, the gate and drain of M3 coupled to Vin through Rb2 and Ib3 respectively, and through drain of M4 coupled to Vin through Ib3 and gate of M4 coupled to Vin through M3 and Rb2 or Ib3 respectively. Therefore, it is Examiner’s position that the prior art Liu anticipates the argued the limitations as recited in the claim.
Applicants stated on page 8 of the REMARKS:
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566
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Applicant's above arguments have been fully considered but they are not persuasive. Examiner would like to respectfully remind Applicant that the prior art Liu teaches the claimed limitations including “a third transistor (e.g., the hybrid transistor M3/M4) coupled between the power input and the control terminal of the first transistor (e.g., Gate and Source of M3 coupled to Vin through Rb2 and Ib3 respectively, and Source of M3 and Drain of M4 coupled to Gate of Mp, see Fig. 3) " in claim 8, and "a third transistor (e.g., the hybrid transistor M3/M4) coupled between the power input and a control terminal of the first transistor (e.g., Gate and Source of M3 coupled to Vin through Rb2 and Ib3 respectively, and Source of M3 and Drain of M4 coupled to Gate of Mp, see Fig. 3)" In claim 16.
Therefore, Liu anticipates the argued limitations as recited in the amended claims 8 and 16.
For at least the reasons as discussed above, the grounds of the claim rejections based on prior art Liu are maintained in the current office action, and the current office action is made FINAL.
Examiner's Note:
Examiner has cited particular columns and line numbers in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner.
In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JUE ZHANG whose telephone number is (571)270-1263. The examiner can normally be reached on M-F: 8:30AM-5:00PM
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Monica Lewis can be reached on 571-272-2838. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JUE ZHANG/
Primary Examiner, Art Unit 2838
Prosecution Insights