DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event a determination of the status of the application as subject to AIA 35 U.S.C. 102, 103, and 112 (or as subject to pre-AIA 35 U.S.C. 102, 103, and 112) is incorrect, any correction of the statutory basis for a rejection will not be considered a new ground of rejection if the prior art relied upon and/or the rationale supporting the rejection, would be the same under either status.
Notice of Claim Interpretation
Claims in this application are not interpreted under 35 U.S.C. 112(f) unless otherwise noted in an office action.
Claim Interpretation
The Examiner is interpreting claims 1 and 16 in light of the limitations of claim 19. Claim 19 depends on claim 1 and therefore must further limit claim 1 as required by 35 U.S.C. 112(d). Thus, the limitation of claim 19 provides at least one possible embodiment of the limitations in claims 1 and 16 that the limitation in claim 19 further limits.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 5-8, 16, 18, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Surico et al. (US 2006/0161727) in view of Moyer et al. (US 6,378,022) and Johns et al. (US 2018/0107385).
In regards to claims 1 and 16, Surico teaches an apparatus comprising:
processing circuitry configured to execute instructions (“The ROM 14 stores instructions which are retrieved by the microcontroller 12 and executed to operate the flash memory system.”, paragraph 0022);
a memory system configured to store data and provide access to the data in response to memory access operations from the processing circuitry, (id.; abstract) wherein the memory system is responsive to a first type of memory access operation to change contents of data stored in the memory system (“The method begins at 102, and in step 104, a modify operation is initiated and is in process. As described above, the modify operation can be a program operation to change or add a new value to the flash memory array 16, an erase operation to erase a value from the array 16, or other operation that modifies the contents of the array.”, paragraph 0040), and to return a response to the processing circuitry from the memory system with respect to the memory access operation (“For example, VERIFY is a microcontroller output that activates and indicates a verify operation for verifying a completed operation”, paragraph 0035); and
memory access operation handling circuitry responsive to receiving, when a memory access operation of the first type of memory access operation is being handled by the memory system, an indication of an interrupt to be taken (“Flip-flop 20 is able to receive a suspend request 22 from a user, which is a request to interrupt and halt the execution of a current modify operation so that the flash memory may be accessed for other operations for the user, such as a read operation. The execution of the suspended modify operation is resumed once the user's operations are complete.”, paragraph 0025), to determine, based on a state of the memory system, whether the memory access operation has reached a stage for which the memory access operation should not be suspended (“In step 108, the method checks whether the conditions are appropriate to suspend the modify operation of step 104. In the present invention, the conditions are appropriate for suspension when the logic 26 generates a ‘true condition’ based on state variables and microcontroller outputs, which are themselves based on whether the currently-executed instruction within the current modify operation is suspendable or interruptible.”, paragraph 0042);
wherein the memory access operation handling circuitry is responsive:
to the memory access operation not reaching a stage for which the memory access operation should not be suspended, to stall the interrupt until the memory access operation has completed (“If conditions are not appropriate to suspend in step 108, then in step 110 the next instruction in the modify operation is executed, and the process returns to step 108 to again determine whether the conditions are appropriate for suspension.”, paragraph 0044); and
to the memory access operation reaching a stage for which the memory access operation can be suspended, to abort the memory access operation and allow the interrupt to be taken (“In step 116, the suspend sequence is executed until it is completed and the modify operation is suspended.”, paragraph 0046).
Surico fails to teach that a stage for which the memory access operation should not be suspended occurs when a remaining time to complete the memory access operation will be bounded;
wherein the memory access operation handling circuitry is responsive:
to the remaining time to complete the memory access operation being determined based on the state of the memory system to be bounded, to stall the interrupt until the memory access operation has completed; and
to the remaining time to complete the memory access operation being determined based on the state of the memory system to be that the memory access operation is not guaranteed to complete within any particular amount of time, to abort the memory access operation and allow the interrupt to be taken.
Moyer teaches that a stage for which the memory access operation can be suspended occurs when a remaining time to complete the memory access operation will be bounded (“If the remaining number of clocks is less than a predetermined or programmable, post-threshold value or interval, the instruction is almost complete, and interrupt recognition for the particular operation is postponed until the next instruction boundary.”, Col. 2, lines 55-60);
wherein the memory access operation handling circuitry is responsive:
to the remaining time to complete the memory access operation being determined based on the state of the memory system to be bounded, to stall the interrupt until the memory access operation has completed (“If the remaining number of clocks is less than a predetermined or programmable, post-threshold value or interval, the instruction is almost complete, and interrupt recognition for the particular operation is postponed until the next instruction boundary. Because the instruction is allowed to complete prior to processing the interrupt, data is not lost due to the interrupt, and the instruction need not be re-executed after the interrupt is processed.”, Col. 2, lines 55-63); and
to the remaining time to complete the memory access operation being determined based on the state of the memory system to be that the memory access operation is not guaranteed to complete within a particular amount of time, to abort the memory access operation and allow the interrupt to be taken (“If the remaining number of clocks is greater than the post-threshold interval, the instruction is not almost complete, and interrupts are recognized during execution of the instruction. Because the instruction is interruptible prior to the post-threshold interval, interrupt latency may be limited to the length of the post-threshold interval instead of the length of the long instruction.”, Col. 2, line 63 - Col. 3, line 2)
such that “interrupt latency and processor re-execution overhead are both optimized” (Col. 3, lines 3-4).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Surico with Moyer such that a stage for which the memory access operation should not be suspended occurs when a remaining time to complete the memory access operation will be bounded;
wherein the memory access operation handling circuitry is responsive:
to the remaining time to complete the memory access operation being determined based on the state of the memory system to be bounded, to stall the interrupt until the memory access operation has completed; and
to the remaining time to complete the memory access operation being determined based on the state of the memory system to be that the memory access operation is not guaranteed to complete within a particular amount of time, to abort the memory access operation and allow the interrupt to be taken
such that “interrupt latency and processor re-execution overhead are both optimized” (id.).
Surico in view of Moyer fails to teach that the memory access operation is not guaranteed to complete within any particular amount of time. Johns teaches that the memory access operation is not guaranteed to complete within any particular amount of time (“Some memory/storage subsystems can be so large and/or complex, that the latency to access the data may be unbounded, or beyond the reasonable expectations of the CPU.”, paragraph 0003) in order to support large and/or complex memory/storage subsystems (id.). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Surico with Moyer and Johns such that the memory access operation is not guaranteed to complete within any particular amount of time in order to support large and/or complex memory/storage subsystems (id.).
In regards to claim 5, Surico further teaches that for a given memory access operation, the stage for which the memory access operation should not be suspended coincides with a stage for which handling of the memory access operation is irreversible (“For example, the current instruction of the modify operation may not be able to be interrupted without causing functionality errors or problems (all referred to simply as "errors" herein); e.g., some types of instructions of the modify operation, when interrupted, may not allow the modify operation to correctly resume.”, paragraph 0042).
In regards to claim 6, Moyer further teaches that the memory access operation handling circuitry is responsive to receiving the indication of the interrupt when the remaining time to complete the memory access operation is such that the memory access operation is not guaranteed to complete within the particular amount of time, to cause the memory system to prioritise handling of the memory access operation (“If the interrupt is masked, for example because the received interrupt has a priority level below a threshold priority determined by the interrupt mask control bits, then execution of the first instruction completes without interruption in the manner described above with reference to operations 528 and 635.”, Col. 5, lines 49-55).
In regards to claim 7, Moyer further teaches that prioritising the handling of the memory access operation by the memory system causes the memory access operation to be handled in bounded time (“In one embodiment, a data processing unit calculates (e.g., counts, reads or otherwise determines) the remaining number of execution clocks for a particular operation.”, Col. 2, lines 53-55).
In regards to claim 8, Moyer further teaches that the memory system comprises main memory and at least one level of cache (“volatile storage media including registers, buffers or caches, main memory, RAM, etc.”, Col. 10, lines 60-62).
In regards to claim 18, Johns further teaches that at least one level of cache in the memory system comprises a level one cache (“Caches can be arranged at several ‘levels’, each getting smaller and faster as they cache the level below.”, paragraph 0002).
In regards to claim 19, Johns further teaches that the memory access operation handling circuitry is configured to determine that the memory access operation is not guaranteed to complete within any particular amount of time when a time required to complete the memory access operation cannot be determined (“Some memory/storage subsystems can be so large and/or complex, that the latency to access the data may be unbounded, or beyond the reasonable expectations of the CPU.”, paragraph 0003).
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Surico et al. (US 2006/0161727) in view of Moyer et al. (US 6,378,022), Johns et al. (US 2018/0107385), and Wittenbrink et al. (“Cache Write Generate For High-Performance Processing”).
In regards to claim 3, Surico in view of Moyer and Johns teaches claim 1. Surico and Johns in view of Moyer fails to teach that: the first type of memory access operation is a write-exclusive operation for which a change to the contents of a particular data item indicated by the write-exclusive operation is contingent on the particular data item being tagged in the memory system as being for exclusive access by the processing circuitry. Wittenbrink teaches that: the first type of memory access operation is a write-exclusive operation for which a change to the contents of a particular data item indicated by the write-exclusive operation (“Cache write generate (CWG) is defined as cache write validation on a write miss. The cache line is updated with the write and the cache line tag is modified to the address of the write.”, section 2, paragraph 1) is contingent on the particular data item being tagged in the memory system as being for exclusive access by the processing circuitry (“However, in a multiprocessor system, for cache coherency purposes it is important to inform the main memory system and other processors that a line is being used in write exclusive mode by the processor writing that line.”, section 2.2, paragraph 1) which “achieves higher performance because it reduces the usage of write buffers, it increases the number of hits on writes, and the write misses do not cause unnecessary reads” (section 2, paragraph 2). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Surico with Moyer, Johns, and Wittenbrink such that: the first type of memory access operation is a write-exclusive operation for which a change to the contents of a particular data item indicated by the write-exclusive operation is contingent on the particular data item being tagged in the memory system as being for exclusive access by the processing circuitry which “achieves higher performance because it reduces the usage of write buffers, it increases the number of hits on writes, and the write misses do not cause unnecessary reads” (id.).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Surico et al. (US 2006/0161727) in view of Moyer et al. (US 6,378,022), Johns et al. (US 2018/0107385), and Tong et al. (US 11,556,485).
In regards to claim 4, Surico in view of Moyer and Johns teaches claim 1. Surico in view of Moyer and Johns fails to teach that the first type of memory access operation is an atomic operation comprising a plurality of sub-operations to be executed atomically. Tong teaches that the first type of memory access operation is an atomic operation comprising a plurality of sub-operations to be executed atomically (“Some instructions may be atomic instructions having a requirement that, once execution has started, it cannot be interrupted until its execution is complete.”, Col. 10, lines 21-24; “For an instruction having a number of microcode operations that include one or more store operations, the store operations may be grouped and placed at the end of the microcode operations. This may reduce the non-interruptible window to a portion of the instruction in which the one or more store operations are carried out. Additionally, where multiple store operations are part of an instruction, the disclosure contemplates bounding the time to complete the various ones of the store operations to minimize the non-interruptible window.”, Col. 3, line 63 - Col. 4, line 5). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Surico with Moyer, Johns, and Tong such that the first type of memory access operation is an atomic operation comprising a plurality of sub-operations to be executed atomically in order to prevent race conditions between threads.
Claims 9-14 are rejected under 35 U.S.C. 103 as being unpatentable over Surico et al. (US 2006/0161727) in view of Moyer et al. (US 6,378,022), Johns et al. (US 2018/0107385), and Garibay et al. (US 5,584,009).
In regards to claim 9, Surico further teaches that the memory access operation handling circuitry is configured to abort the memory access operation by preventing a change to the contents of data in the memory system (“In step 116, the suspend sequence is executed until it is completed and the modify operation is suspended.”, paragraph 0046).
Moyer further teaches that the memory system comprises a cache (“volatile storage media including registers, buffers or caches, main memory, RAM, etc.”, Col. 10, lines 60-62).
Surico in view of Moyer and Johns fails to teach that the cache operates according to a write-back arrangement. Garibay teaches that the cache operates according to a write-back arrangement (“The unified cache 70 is 4-way set associative (with a 4 k set size), using a pseudo-LRU replacement algorithm, with write-through and write-back modes.”, Col. 5, lines 6-8). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Surico with Moyer, Johns, and Garibay such that the cache operates according to a write-back arrangement in order to provide flexibility to the workload.
In regards to claim 10, Surico further teaches that the memory access operation handling circuitry is configured to abort the memory access operation by preventing a change to the contents of data in the memory system (“In step 116, the suspend sequence is executed until it is completed and the modify operation is suspended.”, paragraph 0046).
Moyer further teaches that the memory system comprises a cache and one or more higher levels of the memory system, located logically further from the processing circuitry than the cache (“volatile storage media including registers, buffers or caches, main memory, RAM, etc.”, Col. 10, lines 60-62).
Surico in view of Moyer and Johns fails to teach that the cache that operates according to a write-through arrangement. Garibay teaches that the cache that operates according to a write-through arrangement (“The unified cache 70 is 4-way set associative (with a 4 k set size), using a pseudo-LRU replacement algorithm, with write-through and write-back modes.”, Col. 5, lines 6-8). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Surico with Moyer, Johns, and Garibay such that the cache that operates according to a write-through arrangement in order to provide flexibility to the workload.
In regards to claim 11, Surico in view of Moyer and Johns teaches claim 1. Surico in view of Moyer and Johns fails to teach that the memory system comprises a cache that is operable according to write-back arrangement and a write-through arrangement. Garibay teaches that the memory system comprises a cache that is operable according to write-back arrangement and a write-through arrangement (“The unified cache 70 is 4-way set associative (with a 4 k set size), using a pseudo-LRU replacement algorithm, with write-through and write-back modes.”, Col. 5, lines 6-8). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Surico with Moyer, Johns, and Garibay such that the memory system comprises a cache that is operable according to write-back arrangement and a write-through arrangement in order to provide flexibility to the workload.
In regards to claim 12, Garibay further teaches that to handle the memory access operation, the memory system is configured to issue a request from the cache to the one or more higher levels of the memory system and, once a confirmation has been received from the one or more higher levels of the memory system, provide data to be written to the one or more higher levels of cache (“The memory/bus controller 82 provides the interface between the microprocessor and the external memory subsystem--level two cache 84 and main memory 86--controlling data movement over the 64 bit processor data bus PD (the data path is external to the controller which reduces its pin count and cost).”, Col. 8, lines 13-19).
Moyer further teaches that to abort the operation, the system is configured to provide, with the data, an abort indication (“Floating point unit 340 interrupts an instruction execution flow at the next interrupt recognition point after floating point unit 340 receives ABORT_B signal 324 from integer CPU 300.”, Col. 4, lines 43-46); and
the system is configured to prevent, in response to the abort indication, the change to the contents of data associated with the operation in the system (“Floating point unit 340 interrupts an instruction execution flow at the next interrupt recognition point after floating point unit 340 receives ABORT_B signal 324 from integer CPU 300.”, Col. 4, lines 43-46).
In regards to claim 13, Moyer further teaches that the system is configured to stall, when handling the operation of the first type of operation, further operations until the operation has completed or is aborted (“Instruction execution flow 200 includes sequentially executing instructions A, B, C and D. Instructions A and B are single cycle instructions. Instruction C is a multi-cycle instruction of two cycles.”, Col. 3, lines 24-27; “When an interrupt is received and recognized, execution of instructions in instruction flow 200 is halted at the next interrupt recognition point, and an interrupt handling routine is selected and executed. Execution of instructions is then restarted beginning after the last fully executed instruction.”, Col. 3, lines 42-47).
In regards to claim 14, Moyer further teaches that the system is configured to provide a completion indication once the change to the contents of data associated with the operation in the system has been prevented to indicate that handling of the further operations will not conflict with aborting the operation (“In one embodiment, the partial results of the first instruction are discarded and the data processing system 10 is returned to the same state the data processing system 10 had before the execution of the first instruction began upon completion of processing of the interrupt during operation 632.”, Col. 6, lines 29-35);
the system is responsive to the completion indication to allow the further operations to proceed (“After processing of the interrupt request has completed, the data processing system 10 will re-decode and re-execute the first instruction during operation 526 because execution of the first instruction has not completed.”, Col. 6, lines 36-41).
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Surico et al. (US 2006/0161727) in view of Moyer et al. (US 6,378,022), Johns et al. (US 2018/0107385), Garibay et al. (US 5,584,009), and Juan et al. (“Data Caches for Superscalar Processors”).
In regards to claim 15, Surico in view of Moyer, Johns, and Garibay teaches claim 14.
Surico in view of Moyer, Johns, and Garibay fails to teach that:
the memory system provides a plurality of ports for receiving memory access operations;
the one or more higher levels of the memory system are configured to provide an early completion response in advance of the completion response to indicate that further memory access operations received on ports other than a port associated with the memory access operation will not conflict with aborting the memory access operation; and
the memory system is responsive to the early completion indication to allow memory access operations of the further memory access operations associated with the ports other than the port associated with the memory access operation to proceed.
Juan teaches that:
the memory system provides a plurality of ports for receiving memory access operations (“A multi-banked cache consists of several banks connected to processor-to-cache ports via a crossbar.”, section 5, paragraph 1);
the one or more higher levels of the memory system are configured to provide an early completion response in advance of the completion response to indicate that further memory access operations received on ports other than a port associated with the memory access operation will not conflict with aborting the memory access operation (“The cache is divided in several banks, each bank can be accessed independently of the others. … Bank conflicts occur when two or more requests need to access the same bank simultaneously.”, section 1, paragraph 5); and
the memory system is responsive to the early completion indication to allow memory access operations of the further memory access operations associated with the ports other than the port associated with the memory access operation to proceed (“The cache is divided in several banks, each bank can be accessed independently of the others. … Bank conflicts occur when two or more requests need to access the same bank simultaneously.”, section 1, paragraph 5)
in order to “cope with increasing degree of instruction parallelism” (section 1, paragraph 1).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Surico with Moyer, Johns, Garibay, and Juan such that:
the memory system provides a plurality of ports for receiving memory access operations;
the one or more higher levels of the memory system are configured to provide an early completion response in advance of the completion response to indicate that further memory access operations received on ports other than a port associated with the memory access operation will not conflict with aborting the memory access operation; and
the memory system is responsive to the early completion indication to allow memory access operations of the further memory access operations associated with the ports other than the port associated with the memory access operation to proceed
in order to “cope with increasing degree of instruction parallelism” (id.).
Response to Arguments
Applicant’s arguments, see page 7, filed 5 February 2026, with respect to the claim objection have been fully considered and are persuasive. The claim objection has been withdrawn.
Applicant’s arguments, see pages 7-10, filed 5 February 2026, with respect to the obviousness rejections have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/Nathan Sadler/Primary Examiner, Art Unit 2139 10 March 2026