Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 9-17 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected claim, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 6/14/26.
Applicant’s election without traverse of 1-8 in the reply filed on 6/14/26 is acknowledged.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 3, 5, and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Komada (US 2015/0325741 A1; hereinafter Komada) in view of Sugano (US 2011/0204412 A1; hereinafter Sugano).
Regarding Claim 1. Komada (Fig.1-12) discloses a method for manufacturing a light-emitting element comprising:
forming a first n-layer (3; [0031]) above a first substrate (1; Fig.1-12) being made of a nitride semiconductor layer ([0039]-[0043]);
forming a second n-layer (5/9; [0031]) above the first n-layer (3), the second n-layer being made of a nitride semiconductor layer ([0052]);
forming an active layer (11; [0031]) configured to emit ultraviolet light ([0007]) above the second n-layer (5/9), the active layer (11) being made of a nitride semiconductor layer ([0056]);
forming a p-layer (13; [0031]) above the active layer (11), the p-layer (13) being made of a nitride semiconductor layer ([0031]);
forming a p-electrode (19; [0032]) on the p-layer (13);
exposing the second n-layer (5/9) by removing the first substrate (1) and the first n-layer (3; see Fig.12-13); and
forming an n-electrode (17) on the second n-layer (5/9) exposed in the step of exposing the second n-layer.
Komada does not particularly discloses how the n layers are formed.
Sugano (Fig.1) in a related art discloses a method for manufacturing a light-emitting element comprising:
forming a first n-layer ( [0053]-[0055]) by using a first source gas comprising an Al source gas, a Ga source gas, and a Ge source gas, the first n-layer being made of a nitride semiconductor layer ([0076]-[0077]);
forming a second n-layer ( [0054]) by using a second source gas comprising an Al source gas, a Ga source gas, and a Si source gas, the second n-layer being made of a nitride semiconductor layer ([0076]-[0077]);
forming an active layer of a nitride semiconductor layer ([0056]).
Therefore, it would have been obvious in the art before the effective filing date of the application to use Al, Ga, Ge, and Silicon gas sources to make the n-layers since these methods results in an improved crystal quality, balances lattice stress, setting wide direct bandgap, and a low contact resistance for lower operating voltage.
Regarding Claim 3. The method for manufacturing a light-emitting element according to claim 1, Sugano (Fig.1; [0054]-[0055]) discloses wherein in the step of forming the second n-layer (14a), the second n-layer (14b) is formed with a thickness greater than a thickness of the first n-layer (14b).
Regarding Claim 5. The method for manufacturing a light-emitting element according to claim 1, Sugano (Fig.1; [0055]) discloses wherein in the step of forming the first n-layer (14b), the first n-layer (14b) is formed with a thickness in a range from 0.2 μm to 1.2 μm.
Regarding Claim 7. The method for manufacturing a light-emitting element according to claim 1, Sugano (Fig.1; [0054]) discloses wherein in the step of forming the second n-layer, the second n-layer (14a) is formed with a thickness in a range from 1 μm to 3 μm.
Claim(s) 2, 4, 6, and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Komada in view of Sugano in view of Chadda et al. (US 2021/0257510 A1; hereinafter Chadda).
Regarding Claim 2. The method for manufacturing a light-emitting element according to claim Komada in view of Sugano were not particularly disclose the step of forming the p-electrode, joining the p-electrode and a second substrate by disposing the second substrate at a position proximate to the p-layer, wherein after the step of joining the p-electrode and the second substrate, the step of exposing the second n-layer is performed.
Chadda (Fig.11B) discloses first substrate (22B), LED layers (10B), and a second substrate (400) on top of the electrodes.
Therefore, it would have been obvious in the art before the effective filing date of the application to use a second substrate at a position proximate to the p-layer of the LED to transfer the LED structure more efficiently with minimum damage.
Regarding Claim 4. The method for manufacturing a light-emitting element according to claim 2, Sugano (Fig.1; [0054]-[0055]) discloses wherein in the step of forming the second n-layer (14b), the second n-layer (14b) is formed with a thickness greater than a thickness of the first n-layer (14a).
Regarding Claim 6. The method for manufacturing a light-emitting element according to claim 2, Sugano (Fig.1; [0055]) discloses wherein in the step of forming the first n-layer (14b), the first n-layer (14b) is formed with a thickness in a range from 0.2 μm to 1.2 μm.
Regarding Claim 8. The method for manufacturing a light-emitting element according to claim 2, Sugano (Fig.1; [0054]) discloses wherein in the step of forming the second n-layer (14a), the second n-layer is formed with a thickness in a range from 1 μm to 3 μm.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HAJAR KOLAHDOUZAN whose telephone number is (571)270-5842.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Leonard Chang can be reached on (571)270-3691. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/HAJAR KOLAHDOUZAN/ Examiner, Art Unit 2898
/Leonard Chang/ Supervisory Patent Examiner, Art Unit 2898