CTNF 18/174,694 CTNF 101768 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. This office action is in response to submission of application on 02/27/2023. Claims 1-20 are presented for examination. Claim Rejections - 35 USC § 101 07-04-01 AIA 07-04 35 U.S.C. 101 reads as follows: Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title. Claims 1-20 are rejected under 35 U.S.C 101 because the claimed invention is directed to an abstract idea without significantly more. Step 1: Is the claim to a process, machine, manufacture or composition of matter? Claims 1-7 are directed to a method; claims 8-14 are directed to a computer program product; and claims 15-20 are directed to a computer system. Therefore, the claims are directed to one of the four statutory categories. Step 2A Prong One: Does the claim recite an abstract idea, law of nature, or natural phenomenon? Claim 1 recites limitations of: selecting an architecture search space and a hardware components space, wherein the architecture search space comprises architectures and the hardware components space comprising components for executing a deep neural network; - mental process (observation, evaluation, judgement) as a human mind is able to choose an architecture search space and a hardware components space selecting an initial deep neural network from the architecture search space, the initial deep neural network having a machine learning task performance metric for an evaluation of the initial deep neural network; - mental process (observation, evaluation, judgement) as a human mind is able to choose an initial deep neural network determining an initial chip design for executing the initial deep neural network, wherein the initial chip design has a hardware performance metric for implementing the initial deep neural network; - mental process (observation, evaluation, judgement) as a human mind is able to establish an initial chip design for executing the initial deep neural network executing an optimization method, the optimization method comprising: improving, by a first optimizer, the hardware performance metric of the initial chip design by modifying the initial chip design one or more times using the components from the hardware components space, the improving the hardware performance metric resulting in a revised chip design for a next phase of chip design improvement; - mental process (observation, evaluation, judgement) as a human mind is able to observe a chip design, select a component from a list, substitute it in, and decide whether the hardware metric and improving, by a second optimizer, the machine learning task performance metric of the initial deep neural network by selecting a second deep neural network from the architecture search space, the improving the machine learning task performance metric resulting in a revised deep neural network for a next phase of deep neural network improvement; - mental process (observation, evaluation, judgement) as a human mind is able to observe a neural network architecture, select a different one from a list, and decide whether the ML performance metric improved Step 2A Prong Two: Does the claim recite additional elements that integrate the judicial exceptions into a practical application? Claim 1 recites limitations of: repeating execution of the optimization method by entering the next phase of chip design improvement using the revised chip design as the initial chip design and by entering the next phase of deep neural network improvement using the revised deep neural network as the initial deep neural network; - repeating execution of the optimization method merely amounts to recalculating and readjusting. See MPEP § 2106.05(g), item (3), which identifies recalculating and readjusting as an example of extra-solution activity and responsive to a combination of the hardware performance metric for a specific chip design and the machine learning task performance metric for a specific deep neural network meeting a convergence criterion, providing the specific chip design and the specific deep neural network for performing the machine learning task. – when the convergence criterion is met the specific chip design and specific deep neural network are provided merely amounts to the idea of a solution or outcome. See MPEP § 2106.05(f). Step 2B: Does the claim recite additional elements that amounts to significantly more than the judicial exception? The additional elements are: repeating execution of the optimization method by entering the next phase of chip design improvement using the revised chip design as the initial chip design and by entering the next phase of deep neural network improvement using the revised deep neural network as the initial deep neural network; - repeating execution of the optimization method merely amounts to recalculating and readjusting. See MPEP § 2106.05(g). Recalculating is well-understood, routine, and conventional. See MPEP 2106.05(d)(II)(ii). and responsive to a combination of the hardware performance metric for a specific chip design and the machine learning task performance metric for a specific deep neural network meeting a convergence criterion, providing the specific chip design and the specific deep neural network for performing the machine learning task. – when the convergence criterion is met the specific chip design and specific deep neural network are provided merely amounts to the idea of a solution or outcome. See MPEP § 2106.05(f). The additional elements do not amount to significantly more than the abstract idea. Therefore, the claim is not patent eligible. Independent claim 8 and 15 recites the same relevant limitations and a similar analysis applies. Claim 8 recites the additional elements of, “ A computer program product comprising: one or more computer-readable storage media and program instructions stored on the one or more computer-readable storage media, the program instructions comprising: ” – components recited at a high level are construed as generic computer components used to implement the abstract idea. See MPEP 2106.05(f)(2). Claim 15 recites additional elements of, “ A computer system comprising: one or more computer processors; one or more computer readable storage media; and program instructions stored on the computer readable storage media for execution by at least one of the one or more processors, the program instructions comprising: ” – components recited at a high level are construed as generic computer components used to implement the abstract idea. See MPEP 2106.05(f)(2). They do not integrate the abstract idea into a practical application. Nor do they amount to significantly more. Therefore, the independent claims are not patent eligible. The above analysis similarly applies to the dependent claims. Dependent claims 2, 9 and 16 recites, satisfying the hardware performance metric for the revised chip design obtained after every n th repetition of the optimization method, where n is an integer within a predefined set of numbers. – satisfying the hardware performance metric after every nth repetition merely amounts to the idea of a solution or outcome. See MPEP § 2106.05(f). Dependent claims 3, 10 and 17 recites, the first optimizer provides to the second optimizer a revised hardware performance metric when a hardware performance metric value differs by a minimum value from a immediately previous hardware performance metric value; - the first optimizer providing the revised hardware performance metric to the second optimizer is merely transmitting data. See MPEP § 2106.05(g). Transmitting is well-understood, routine, and conventional. See MPEP 2106.05(d)(II)(i). and improving, by a second optimizer, the machine learning task performance metric of the initial deep neural network is performed while satisfying the revised hardware performance metric. - the second optimizer improving the machine learning task performance metric while satisfying the revised hardware performance metric merely recites the idea of a solution or outcome. See MPEP § 2106.05(f). Dependent claims 4, 11, and 18 recites, wherein the convergence criterion requires the hardware performance metric to have a predefined optimal value and/or the machine learning task performance metric to have a predefined optimal value. – the convergence criterion requiring the metrics to reach predefined optimal values merely recites the idea of a solution or outcome. See MPEP § 2106.05(f). Dependent claims 5, 12, and 19 recites, the convergence criterion requires, before providing the specific chip design: a specified number of repeated executions of the optimization method; - a number of repeated executions merely recites the idea of a solution or outcome. See MPEP § 2106.05(f). and either (a) the hardware performance metric value meets a predefined target value; or (b) the machine learning task performance metric value meets a predefined target value. – meeting a predefined target value merely recites the idea of a solution or outcome. See MPEP § 2106.05(f). Dependent claim 6, 13, and 20 recites, wherein the repeating execution of the optimization method is performed in parallel for multiple initial deep neural networks and corresponding initial chip designs. – repeating execution in parallel merely recites the idea of a solution or outcome. See MPEP § 2106.05(f). Dependent claim 7 and 14 recites, selecting the second deep neural network from the architecture search space is performed such that the second deep neural network and the initial deep neural network have a maximum dissimilarity level; - selecting the second deep neural network merely amounts to data gathering which is insignificant extra-solution activity. See MPEP § 2106.05(g). Data gathering is well-understood, routine, and conventional. See MPEP 2106.05(d)(II)(iv). replacing the initial deep neural network by the second deep neural network if the machine learning task performance metric value obtained with the second deep neural network is closer to a target value than the machine learning task performance metric value obtained with the initial deep neural network; - replacing the initial deep neural network merely amounts to recalculating and readjusting. See MPEP § 2106.05(g). Readjusting is well-understood, routine, and conventional. See MPEP 2106.05(d)(II)(ii). and improving the machine learning task performance metric is performed repeatedly by the second optimizer until a stopping criterion is reached. – the second optimizer repeating until a stopping criterion is reached merely recites the idea of a solution or outcome. See MPEP § 2106.05(f). The dependent claims do not integrate the abstract idea into a practical application, nor do they amount to significantly more than the abstract idea. Claim Rejections - 35 USC § 103 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim (s) 1, 2, 4, 5, 8, 9, 11, 12, 15, 16, 18, 19 are rejected under 35 U.S.C. 103 as being unpatentable over Zhang et al. (DNA: Differentiable Network-Accelerator Co-Search, herein Zhang) in view of Zhou et al. (Towards the Co-Design of Neural Networks and Accelerators, herein Zhou) Regarding claim 1, Zhang teaches, selecting an architecture search space and a hardware components space, wherein the architecture search space comprises architectures and the hardware components space comprising components for executing a deep neural network; (Zhang, abstract, “(1) a generic design space for DNN accelerators […] (2) a joint DNN network and accelerator co-search algorithm that enables the simultaneous search for optimal DNN structures and their accelerators’ micro-architectures and mapping methods to maximize both the task accuracy and acceleration efficiency”, page 3, section 3.1, " DNA consists of two search engines: (1) the DAS engine integrated with a generic accelerator design space, which enables differentiable search to handle the accelerators’ large and discrete design space, and (2) the DNS engine, built upon SOTA differentiable NAS works" and page 2, Figure 1, “ PNG media_image1.png 242 687 media_image1.png Greyscale ”, note : selecting an architecture search space maps to DNA's DNS engine that operates on a network architecture search space. And a hardware components space maps to the DNA's DAS engine integrated with a generic accelerator design space. Wherein the architecture search space comprises architectures maps to the DNA's DNS engine that searches over candidate network architectures defined by kernel size, channel expansion ratio, and group number per building block (section 3.3). And the hardware components space comprising components maps to DNA's generic accelerator design space that comprises components listed in Tab 1: loop-order, loop-size, NoC design, max number of PEs, and pipeline/multi-cycle. for executing a deep neural network maps to the DNA's accelerator are designed for accelerating DNNs (section 3.4)) selecting an initial deep neural network from the architecture search space, the initial deep neural network having a machine learning task performance metric for an evaluation of the initial deep neural network; (Zhang, page 4, section 3.2, " DNA samples M networks from the current network distribution NET(α)... the hardware-cost loss of each operator is then obtained using its average hardware cost on the M optimal accelerators' and page 3, section 3.1, equation 1, " PNG media_image2.png 34 324 media_image2.png Greyscale ", note : selecting an initial deep neural network maps to the DNA samples M networks from NET(a), the first sampled network is the initial network. From the architecture search space maps to the networks are sampled from the current network distribution NET(a) which is parameterized over the network search space. the initial deep neural network having a machine learning task performance metric maps to each sampled NET(a) has an associated Lval which is the task loss of... validation (section 3.1). For an evaluation of the initial deep neural network maps to DNA evaluates each sampled network by computing Lval in equation 1.) determining an initial chip design for executing the initial deep neural network, wherein the initial chip design has a hardware performance metric for implementing the initial deep neural network; (Zhang, page 3, section 3.1, "DNA accepts user defined datasets, target performance (e.g., task accuracy and hardware efficiency), and resource constraints as inputs to automatically generate matched pairs of DNNs and their accelerators to maximize both the accuracy and efficiency" and page 5, section 3.4, " PNG media_image3.png 25 324 media_image3.png Greyscale ” and page 7, section 4.1.2, "We adopt Frame-Per-Second (FPS), latency, or Energy-Delay-Product (EDP)as the hardware-cost loss(i.e.,Lhw in Eq.1))", note : determining the initial chip design maps to the DNA's DAS engine determines an accelerator HW(y) by solving equation 7, the accelerator is the chip design. For executing the initial deep neural network maps to the accelerator is generated as one of the matched pairs of DNNs and their accelerations, meaning it is designed for executing the specific DNN. Wherein the initial chip design has a hardware performance metric maps to the DNA measures hardware efficiency with Lhw defined as Frame-Per-Second (FPS), latency or Energy-Delay-Product (EDP) (section 4.1.2). For implementing the initial deep neural network maps to the metric Lhw is computed in equation 7, which means that the hardware metric is measured for how well the accelerator implements the given NET(a)) executing an optimization method, the optimization method comprising: improving, by a first optimizer, the hardware performance metric of the initial chip design by modifying the initial chip design one or more times using the components from the hardware components space, the improving the hardware performance metric resulting in a revised chip design for a next phase of chip design improvement; (Zhang, page 4, algorithm 1, " PNG media_image4.png 51 659 media_image4.png Greyscale ]", page 5, section 3.4, "Our DAS engine aims to... realizes a generic differentiable accelerator search engine", and page 6, section 4.1.2, "for updating the hardware accelerator parameters, we conduct updates at each epoch using an SGD optimizer", note : executing an optimization method maps to DNA executes its algorithm within the loop. Improving, by a first optimizer maps to the DNA's DAS engine is the first optimizer, described as a generic differentiable accelerator search engine. The hardware performance metric of the initial chip design maps to the DAS engine minimizes Lhw of the accelerator HW(y). By modifying the initial chip design one or more times maps to DAS conduct updates at each epoch to the hardware accelerator parameters. Using the components from the hardware components space maps to DAS operates on the generic accelerator design space whose components are listed in Tab 1. The improving the hardware performance metric resulting in a revised chip design maps to each epoch produces optimized accelerators HW*_m which are the revised chip design. For a next phase of chip design improvement maps to the while loop iterates, so the optimized accelerators HW*_m from one epoch become the starting point for the next epoch which is the next phase.) and improving, by a second optimizer, the machine learning task performance metric of the initial deep neural network by selecting a second deep neural network from the architecture search space, the improving the machine learning task performance metric resulting in a revised deep neural network for a next phase of deep neural network improvement; (Zhang, page 4, section 3.3, algorithm 1, " PNG media_image5.png 63 411 media_image5.png Greyscale ", and page 4-5, section 3.3, "The DNS engine can be realized by leveraging SOTA differentiable NAS works. which computes the output of the l-th layer Al as a weighted sum of all candidate operators: PNG media_image6.png 47 145 media_image6.png Greyscale ”, note : the machine learning task performance metric of the initial deep neural network maps to the DNS engine minimizes L_val which is the task loss of validation (section3.1). Selecting a second deep neural network maps to update a reweighting all candidate operators) repeating execution of the optimization method by entering the next phase of chip design improvement using the revised chip design as the initial chip design and by entering the next phase of deep neural network improvement using the revised deep neural network as the initial deep neural network; (Zhang, page 4, algorithm 1, " PNG media_image7.png 130 662 media_image7.png Greyscale ”, note : repeating execution maps to the while epoch < max_epoch. Using the revised chip design as the initial chip design is the next epoch reruns DAS on current y producing new optimized accelerators HW*_m. Using the revised deep neural network as the initial deep neural network maps to the next epoch reruns DNS on current network distribution NET(a).) Zhang does not explicitly teach, and responsive to a combination of the hardware performance metric for a specific chip design and the machine learning task performance metric for a specific deep neural network meeting a convergence criterion, providing the specific chip design and the specific deep neural network for performing the machine learning task. Zhou teaches, and responsive to a combination of the hardware performance metric for a specific chip design and the machine learning task performance metric for a specific deep neural network meeting a convergence criterion, providing the specific chip design and the specific deep neural network for performing the machine learning task. (Zhou, page 5, equation 1, " PNG media_image8.png 114 319 media_image8.png Greyscale ," and page 4-5, section 3.1, "The objective for NaaS is to find a neural architecture configuration in the space of α and hardware accelerator configuration in the space of h such that the validation accuracy can be maximized while meeting a chip area and latency target.", note: This tracks both the ML metric (Lval) and hardware metrics (latency and area) jointly. The loop ends when both constraints are satisfied together which maps to the convergence criterion.) It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Zhang with Zhao because Zhang teaches the full co-search loop, but ends after a fixed number of epochs and does not mention a joint stopping condition. Zhou operates in the same co-design, but also shows that both metrics need to be satisfied together for the best result. Therefore, adding the joint stopping condition will allow it so that the search only finishes and outputs the final chip and network once both targets are confirmed to be met, this allows for that both ends are optimal rather than one or the other. Regarding claim 2, The combination of Zhang and Zhou teaches, The method of claim 1, wherein improving the machine learning task performance metric of the initial deep neural network includes: satisfying the hardware performance metric for the revised chip design obtained after every nth repetition of the optimization method, where n is an integer within a predefined set of numbers. (Zhang, page 6, section 4.1.2, " the search for the optimal DNNs and accelerators adopts 50 epochs with a batch size of 64… for updating the hardware accelerator parameters, we conduct updates at each epoch", note: DNA updates and evaluates the hardware metric once per epoch. Each epoch is one repetition of the optimization method, therefore n=1 is the integer within a predefined set. The hardware constraint is satisfied and checked at every repetition. Zhang explicitly discloses max_epoch as the boundary of the predetermined set of numbers or use.) Regarding claim 4, The combination of Zhang and Zhou teaches, The method of claim 1, wherein the convergence criterion requires the hardware performance metric to have a predefined optimal value and/or the machine learning task performance metric to have a predefined optimal value. (Zhou, page 6, section 3.4, " PNG media_image9.png 197 519 media_image9.png Greyscale ”, note: hardware performance metric to have a predefined optimal value maps to the T_latency and T_area are predefined target values. The reward function penalizes solutions where Latency (a,h) exceeds T_latency.) Regarding claim 5, The combination of Zhang and Zhou teaches, The method of claim 1, wherein: the convergence criterion requires, before providing the specific chip design: a specified number of repeated executions of the optimization method; (Zhang, page 6, section 4.1.2, " the search for the optimal DNNs and accelerators adopts 50 epochs… the search for both the optimal network and accelerator adopts 90 epochs", note : a specified number of repeated executions maps to the DNA's 50 epochs or 90 epochs. Before providing the specific chip design maps to how the DNA does not return {optimal_net, optimal_accelerator} until after the loop completes. and either (a) the hardware performance metric value meets a predefined target value; or (b) the machine learning task performance metric value meets a predefined target value. (Zhou, page 6, section 3.4, " PNG media_image9.png 197 519 media_image9.png Greyscale , note : hardware performance metric value meets a predefined target value maps to the Latency(a,h) <= T_latency.) It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Zhang and Zhou because Zhang teaches how many times to repeat but does not teach what target value signals success and Zhou fills that gap by providing explicit predefined target values (Latency and Area) that the metrics must hit. Therefore, combining the two would ensure that the search runs efficiently. Claims 8, 9, 11, and 12 corresponds to method claims 1, 2, 4, and 5. They are not patentably distinguishable as they only differ between a computer program product and a method , A computer program product comprising: one or more computer-readable storage media and program instructions stored on the one or more computer-readable storage media, the program instructions comprising . (Zhang, abstract, “DNA integrates two enablers: (1) a generic design space for DNNaccelerators that is applicable to both FPGA- and ASIC-based DNN accelerators and compatible with DNN frameworks such as PyTorch to enable algorithmic exploration”, note : The storage media is necessarily required to execute the recited PyTorch framework on the FPGA/ASIC processor.) Therefore, claims 8, 9, 11, and 12 are rejected for the same reasons as 1, 2, 4, and 5, respectively. Claims 15, 16, 18, and 19 corresponds to method claims 1, 2, 4, and 5. They are not patentably distinguishable as they only differ between a computer system and a method, A computer system comprising: one or more computer processors; one or more computer readable storage media; and program instructions stored on the computer readable storage media for execution by at least one of the one or more processors, the program instructions comprising , (Zhang, abstract, “DNA integrates two enablers: (1) a generic design space for DNNaccelerators that is applicable to both FPGA- and ASIC-based DNN accelerators and compatible with DNN frameworks such as PyTorch to enable algorithmic exploration”, note : The storage media is necessarily required to execute the recited PyTorch framework on the FPGA/ASIC processor.) Therefore, claims 15, 16, 18, and 19 are rejected for the same reasons as 1, 2, 4, and 5, respectively . 07-21-aia AIA Claim (s) 3, 10, and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Zhang et al. (DNA: Differentiable Network-Accelerator Co-Search, herein Zhang) in view of Zhou et al. (Towards the Co-Design of Neural Networks and Accelerators, herein Zhou) and in further view of Tien-Ju Yang et al. (NetAdapt: Platform-Aware Neural Network Adaptation for Mobile Applications, herein Tien-Ju Yang) Regarding claim 3, The combination of Zhang and Zhou teaches, The method of claim 1, wherein : However, Zhang and Zhou do not teach, the first optimizer provides to the second optimizer a revised hardware performance metric when a hardware performance metric value differs by a minimum value from a immediately previous hardware performance metric value; and improving, by a second optimizer, the machine learning task performance metric of the initial deep neural network is performed while satisfying the revised hardware performance metric. Tien-Ju Yang teaches, the first optimizer provides to the second optimizer a revised hardware performance metric when a hardware performance metric value differs by a minimum value from a immediately previous hardware performance metric value; (Tien-Ju Yang, page 5, section 3.1, "Resj(Neti−1)−∆Ri,j) … .∆Ri,j, which is larger than zero, indicate show much the constraint tightens for the jth resource in the ith iteration and can vary from iteration to iteration.", note: ∆Ri,j > 0 is the needed minimum amount. This means the hardware target only gets updated and sent over when it has changed by at least that minimum amount from the last round. This maps to the minimum value) and improving, by a second optimizer, the machine learning task performance metric of the initial deep neural network is performed while satisfying the revised hardware performance metric. (Tien-Ju Yang, page 4, section 3.1, " PNG media_image10.png 84 586 media_image10.png Greyscale ” note : once the accuracy side receives the new hardware target, it tries to improve the network's accuracy as much as possible while staying within the target.) It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Zhang and Zhou with Tien-Ju Yang because Tien-Ju demonstrates that the hardware target should only be sent over when it has changed by at least a minimum amount, which saves computation. This allows for there to be a smart communication rule that makes the loop more efficient. Claim 10 corresponds to method claim 3. They are not patentably distinguishable as they only differ between a computer program product and a method. Therefore, claim 10 is rejected for the same reasons as 3, respectively. Claim 17 corresponds to method claims 3. They are not patentably distinguishable as they only differ between a computer system and a method. Therefore, claim 17 is rejected for the same reasons as 3, respectively . 07-21-aia AIA Claim (s) 6, 13, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Zhang et al. (DNA: Differentiable Network-Accelerator Co-Search, herein Zhang) in view of Zhou et al. (Towards the Co-Design of Neural Networks and Accelerators, herein Zhou) and in further view of Lei Yang et al. (Co-Exploration of Neural Architectures and Heterogeneous ASIC Accelerator Designs Targeting Multiple Tasks, herein Lei Yang) Regarding claim 6, The combination of Zhang and Zhou teaches, The method of claim 1, However, Zhang and Zhou do not teach, wherein the repeating execution of the optimization method is performed in parallel for multiple initial deep neural networks and corresponding initial chip designs. Lei Yang teaches, wherein the repeating execution of the optimization method is performed in parallel for multiple initial deep neural networks and corresponding initial chip designs. (Lei Yang, abstract, " with the consideration that multiple DNNs will run in parallel for different workloads with diverse layer operations and sizes, integrating heterogeneous ASIC sub accelerators for distinct DNNs in one design... NASAIC, which can simultaneously identify multiple DNN architectures and the associated heterogeneous ASIC accelerator design," note : in parallel for multiple initial deep neural networks maps to simultaneously identify multiple DNN architectures. Corresponding initial chip design maps to the associated heterogeneous ASIC sub-accelerators for the distinct DNNs.) It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Zhang and Zhou with Lei Yang because Lei Yang shows that multiple DNN architectures and their corresponding chip designs can be searched at the same time, which saves time by finding the best pairs faster than doing them one by one. Zhang and Zhou only teach optimizing one network and chip at a time. Therefore, Lei Yang teaches the straightforward improvement of running the same loop in parallel for multiple networks and chips at once. Claim 13 corresponds to method claim 6. They are not patentably distinguishable as they only differ between a computer program product and a method. Therefore, claim 13 is rejected for the same reasons as 6, respectively. Claim 20 corresponds to method claims 6. They are not patentably distinguishable as they only differ between a computer system and a method. Therefore, claim 20 is rejected for the same reasons as 6, respectively . 07-21-aia AIA Claim (s) 7 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Zhang et al. (DNA: Differentiable Network-Accelerator Co-Search, herein Zhang) in view of Zhou et al. (Towards the Co-Design of Neural Networks and Accelerators, herein Zhou) and in further view of Sinha (Novelty Driven Evolutionary Neural Architecture Search, herein Sinha) and in further view of Real (Regularized Evolution for Image Classifier Architecture Search, herein Real) Regarding claim 7, The combination of Zhang and Zhou teaches, The method of claim 1 wherein : However, Zhang and Zhou do not teach, selecting the second deep neural network from the architecture search space is performed such that the second deep neural network and the initial deep neural network have a maximum dissimilarity level; replacing the initial deep neural network by the second deep neural network if the machine learning task performance metric value obtained with the second deep neural network is closer to a target value than the machine learning task performance metric value obtained with the initial deep neural network; and improving the machine learning task performance metric is performed repeatedly by the second optimizer until a stopping criterion is reached. Sinha teaches, selecting the second deep neural network from the architecture search space is performed such that the second deep neural network and the initial deep neural network have a maximum dissimilarity level; (Sinha, page 9, section 6, "the NAS problem as a multi-objective problem with two objectives of maximizing the architecture novelty (i.e. novelty search) and maximizing the architecture fitness.”, note : The claim requires the selected candidate to be maximally different from the current network. This maps to maximize architecture novelty, meaning it favors candidates that are most dissimilar from previously explored architectures.) It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Zhang and Zhou with Sinha because Sinha explains picking the most dissimilar architecture helps the search avoid getting stuck and find better results. Therefore, Sinha adds that by picking the most different candidate it keeps things moving in new directions. Sinha does not teach, replacing the initial deep neural network by the second deep neural network if the machine learning task performance metric value obtained with the second deep neural network is closer to a target value than the machine learning task performance metric value obtained with the initial deep neural network; and improving the machine learning task performance metric is performed repeatedly by the second optimizer until a stopping criterion is reached. Real teaches, replacing the initial deep neural network by the second deep neural network if the machine learning task performance metric value obtained with the second deep neural network is closer to a target value than the machine learning task performance metric value obtained with the initial deep neural network; (Real, page 1, section 1, "Whereas in tournament selection, the best genotypes (architectures) are kept" and page 7, discussion, "What makes evolution different from random search is that only the good models are selected to be mutated." note : the claim requires a compare and replace where they evaluate the new candidate, compare it to the current network, and replace only if the new one is better. The tournament selection does this by candidates are evaluated by accuracy, only good models are selected.) and improving the machine learning task performance metric is performed repeatedly by the second optimizer until a stopping criterion is reached. (Real, page 1, section 1, "Whereas in tournament selection, the best genotypes (architectures) are kept", note : improving the machine learning task performance metric maps to the evolutionary process where the best genotypes are kept. Accuracy improves over generations as inferior candidates are replaces. Is performed repeatedly maps to Algorithm 1 (aging evolution) running the tournament loop across many cycles. until a stopping criterion is reached maps to the process terminating after a fixed number of cycles) It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Zhang, Zhou, and Sinha with Real because Real explains that when the new network is better, then you swap and stop after a set number of rounds. This would help ensure that the search never goes backwards and only improves or stays the same, so by the time it stops, it is guaranteed to have the best network found. Claim 14 corresponds to method claim 7. They are not patentably distinguishable as they only differ between a computer program product and a method. Therefore, claim 14 is rejected for the same reasons as 7, respectively. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to UYEN-NHU PHAM TRAN whose telephone number is (571)272-1559. The examiner can normally be reached Monday - Friday 7:30-5. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Miranda Huang can be reached at (571) 270-7092. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. 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If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /U.P.T./ Examiner, Art Unit 2124 /MIRANDA M HUANG/ Supervisory Patent Examiner, Art Unit 2124 Application/Control Number: 18/174,694 Page 2 Art Unit: 2124 Application/Control Number: 18/174,694 Page 3 Art Unit: 2124 Application/Control Number: 18/174,694 Page 4 Art Unit: 2124 Application/Control Number: 18/174,694 Page 5 Art Unit: 2124 Application/Control Number: 18/174,694 Page 6 Art Unit: 2124 Application/Control Number: 18/174,694 Page 7 Art Unit: 2124 Application/Control Number: 18/174,694 Page 8 Art Unit: 2124 Application/Control Number: 18/174,694 Page 9 Art Unit: 2124 Application/Control Number: 18/174,694 Page 10 Art Unit: 2124 Application/Control Number: 18/174,694 Page 11 Art Unit: 2124 Application/Control Number: 18/174,694 Page 12 Art Unit: 2124 Application/Control Number: 18/174,694 Page 13 Art Unit: 2124 Application/Control Number: 18/174,694 Page 14 Art Unit: 2124 Application/Control Number: 18/174,694 Page 15 Art Unit: 2124 Application/Control Number: 18/174,694 Page 16 Art Unit: 2124 Application/Control Number: 18/174,694 Page 17 Art Unit: 2124 Application/Control Number: 18/174,694 Page 18 Art Unit: 2124 Application/Control Number: 18/174,694 Page 19 Art Unit: 2124 Application/Control Number: 18/174,694 Page 20 Art Unit: 2124
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