Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “the host apparatus is configured to: receive partial information being a base of a value of a first part being part of the coefficient matrix and the coefficient vector” of claim 13 must be shown or the feature(s) canceled from the claim(s). Claim 1 recites, “the Ising machine includes: a coefficient memory configured to store a coefficient matrix and a coefficient vector defining the Ising model”. Figure 16 seems to show the host apparatus receiving partial information (reference number 122). Claim 1 gives the antecedent basis for the coefficient matrix and the coefficient vector, and claim 1 states that the coefficient matrix and coefficient vector is stored in coefficient memory (reference number 52, which is part of the Ising machine reference number 12). The figures, including Fig. 16, do not show the host apparatus receiving partial information of the coefficient matrix and the coefficient vector because the coefficient matrix and coefficient vector are stored in the coefficient memory, nor do the figures show providing the host apparatus the partial information AND the host apparatus sending the Ising machine the coefficient vector & matrix to be stored by the coefficient memory.
No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claims 1 and 13 objected to because of the following informalities:
Claim 1 appears to contain a grammatical error and should be changed to, “corresponding to each of the Ising spins”. The Examiner respectfully notes that Ising spins have implied antecedent basis due to Ising spins being elements of an Ising model, the correction to this grammatical objection would not result in a lack of antecedent basis based on the grammar.
Claim 13 appears to contain a grammatical error and should be changed to, “generate difference information indicating an address and a value indicating a position of a different point between:
the coefficient matrix and the coefficient vector defining the preceding Ising model to be searched and being stored in the coefficient memory, and
the new coefficient matrix and the new coefficient vector”.
Appropriate correction is required.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are: “host apparatus” in claims 1-3, and 7-13. In review of the applicant’s specification, the structure of the “host apparatus” is interpreted as: host apparatus 14 includes a model generator 72, a coefficient sender 74, an execution commander 76, and an outputter 78 as disclosed in paragraph [0068] and Fig. 6, and Fig. 12, and host apparatus 14 includes a partial information receiver 122, a model updater 126, a partial coefficient sender 128, the execution commander 76, and the outputter 78 as disclosed in paragraph [0143], and Fig. 16.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend nbto have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 6, 11, and 13-14 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 6, claim 6 recites the limitations of: “the set of the main variables”. There is insufficient antecedent basis for this limitation in the claim.
Furthermore, claim 6 recites the limitations of: “the set of the auxiliary variables”. There is insufficient antecedent basis for this limitation in the claim.
Regarding claim 11, claim 11 recites the limitations of: “the output circuit is configured to collectively transmit, to the host apparatus, the search results”. Claim 1, which claim 11 is dependent upon, recites the limitations of: “an output circuit configured to transmit a value based on the main variable to the host apparatus as a search result”, “host apparatus is configured to: receive the search result”, and “the received search result”. Claim 1 describes a singular search result transmitted to the host apparatus, and the host apparatus receiving a singular search result. Claim 11 describes the output circuit collectively transmitting a plurality of search results. It is unclear how the limitations of claim 11 coincide with the limitations of claim 1. It is unclear if the limitations of claim 11 are meant to replace the limitations of claim 1, or if the limitations of claim 11 are meant to be in addition to the limitations of claim 1.
Regarding claim 13, claim 13 recites the limitations of: “a preceding Ising model to be searched”. The limitation “to be searched”, is a limitation describing a future event potentially taking place, therefore it is unclear whether or not the Ising model being searched is positively claimed or not.
Furthermore, claim 13 recites the limitations of: “receive partial information being a base of a value of a first part being part of the coefficient matrix and the coefficient vector”. It is unclear if the limitation is meant to be understood as the host apparatus is configured to receive a base of a value of a first part of the coefficient matrix and receive a base of a value of the coefficient vector, or if the base value is meant to be a value of a first part of the coefficient matrix and a first part of the coefficient vector.
Furthermore, claim 13 recites the limitations of: “generate a new coefficient matrix and a new coefficient vector by replacing, with a value based on the partial information, a value of the first part in the coefficient matrix and the coefficient vector defining a preceding Ising model to be searched”. It is unclear if the limitation is meant to be understood as a value of the first part in the coefficient matrix is replaced and a value of the first part of the coefficient matrix is replaced, or if it is meant to be understood as a value of the first part in the coefficient matrix is replaced and the entirety of the coefficient vector defining a preceding Ising model to be searched is replaced.
Furthermore, claim 13 recites the limitation of: “generate difference information indicating an address and a value indicating a position of a different point between the coefficient matrix and the coefficient vector”. The phrase in the limitation, “a different point between the coefficient matrix and the coefficient vector”, implies a first point between the coefficient matrix and the coefficient vector, but the claim does not recite a first point between the coefficient matrix and the coefficient vector.
Furthermore, claim 13 recites the limitations of: “the coefficient matrix and the coefficient vector defining a preceding Ising model to be searched”. Claim 1 recites, “a coefficient memory configured to store a coefficient matrix and a coefficient vector defining the Ising model”, the Ising model of claim 1 is different than “a preceding Ising model”. Therefore, there is a lack of antecedent basis for this limitation, “the coefficient matrix and the coefficient vector defining a preceding Ising model to be searched”. Similarly, there is a lack of antecedent basis for the claim 13 limitation, “the coefficient matrix and the coefficient vector defining the preceding Ising model to be searched and being stored in the coefficient memory”.
Furthermore, claim 13 recites the limitation of: “the setting circuit is configured to rewrite a value of the address”. It is unclear if the limitation is meant to be understood as the setting circuit is configured to rewrite a value at the address, or if it is meant to be understood as the setting circuit is configured to rewrite the address value.
Furthermore, claim 13 recites the limitation of: “the setting circuit is configured to rewrite a value of the address indicated by the difference information in the coefficient matrix and the coefficient vector stored in the coefficient memory”. It is unclear if the limitation is meant to be understood as the setting circuit is configured to rewrite a value of the address with the address being in the coefficient matrix and the coefficient vector stored in the coefficient memory, or if the reference to the coefficient matrix and the coefficient vector stored in the coefficient memory is a reference to where the difference information is determined from, the address indicated by the difference information of the coefficient matrix and the coefficient vector.
Claim 14 inherits the same deficiencies as claim 13 based on dependence.
Regarding claim 14, Claim 14 recites the limitation of: “an address and a value of an element of the different point”. It is unclear if the different point is meant to be understood as a single value, a vector, or a matrix of values.
Furthermore, claim 14 recites the limitation of: “the coefficient matrix and the coefficient vector”. It is unclear if the limitation is referring to the coefficient matrix and the coefficient vector of the Ising model of claim 1, or if it is referring to the coefficient matrix and the coefficient vector of the preceding Ising model to be searched.
Furthermore, claim 14 recites the limitation of: “a plurality of values included in the coefficient vector”. It is unclear if the limitation is referring to the coefficient vector of the Ising model of claim 1, or if it is referring to the coefficient vector of the preceding Ising model to be searched.
Furthermore, claim 14 recites the limitations of: “the difference information contains at least one of an address of a row and a plurality of values included in the row, the row including the different point in the coefficient matrix and the coefficient vector, an address of a column and a plurality of values included in the column, the column including the different point in the coefficient matrix and the coefficient vector, an address of a submatrix and a plurality of values included in the submatrix, the submatrix including the different point in the coefficient matrix and the coefficient vector, an address and a value of an element of the different point in the coefficient matrix and the coefficient vector, and a plurality of values included in the coefficient vector.” Claim 13, which claim 14 is dependent upon, recites the limitation of, “generate difference information indicating an address and a value indicating a position of a different point between the coefficient matrix and the coefficient vector”. The limitation of claim 13 describes the difference information indicating a singular address and a singular value, “an address and a value”, indicating a position of a different point. The limitation of claim 14 describes the difference information instead containing one or more addresses, and a plurality of values along with each of the one or more addresses, and one of the listed potential contents of the difference information being “a plurality of values included in the coefficient vector”. It is unclear how the limitations of claim 14 coincide with the limitation of claim 13. It is unclear if the limitations of claim 14 are meant to replace the limitation of claim 13, or if the limitations of claim 14 are meant to be in addition to the limitation of claim 13 in some manner.
Allowable Subject Matter
Claims 1-5, 7-10, and 12 are allowed.
Claims 6, 11, and 13-14 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
With regards to claim 1, the applicant claims An information processing system solving a combinatorial optimization problem, the information processing system comprising:
an Ising machine being hardware configured to execute a search process searching for a ground state of an Ising model representing the combinatorial optimization problem; and
a host apparatus being hardware connected to the Ising machine via an interface, the host apparatus being configured to control the Ising machine, wherein
the Ising machine includes:
a coefficient memory configured to store a coefficient matrix and a coefficient vector defining the Ising model;
a variable memory configured to store a main variable and an auxiliary variable corresponding to each of Ising spins contained in the Ising model;
an arithmetic circuit configured to alternately repeat, in the search process, execution of an auxiliary variable update process and a main variable update process for each of the Ising spins, the auxiliary variable update process updating the auxiliary variable with the main variable, the main variable update process updating the main variable with the auxiliary variable;
an output circuit configured to transmit a value based on the main variable to the host apparatus as a search result, the main variable corresponding to each of the Ising spins after execution of the search process; and
a setting circuit configured to
write the coefficient matrix and the coefficient vector on the coefficient memory, and
cause the arithmetic circuit to start the search process in response to reception of an execution start command of the search process from the host apparatus,
the host apparatus is configured to:
receive the search result from the Ising machine after the search process; and
output a solution of the combinatorial optimization problem on the basis of the received search result, and
the coefficient memory is configured to continue storing a preceding coefficient matrix and a preceding coefficient vector until a new coefficient matrix and a new coefficient vector are written by the setting circuit.
The primary reason for indication of allowable subject matter is the above italicized claim limitations in combination with the remaining claim limitations including intervening claims.
Tatsumura et al. (K. Tatsumura, A. R. Dixon and H. Goto, "FPGA-Based Simulated Bifurcation Machine," 2019 29th International Conference on Field Programmable Logic and Applications (FPL), Barcelona, Spain, 2019, pp. 59-66, doi: 10.1109/FPL.2019.00019), hereinafter “Tatsumura” discloses an information processing system for solving a combinatorial optimization problem (pg. 59 column 2 paragraph 2 regarding the simulated bifurcation algorithm is for solving combinatorial optimization problems; pg. 59 column 2 paragraph 3 regarding an FPGA-based accelerator for simulated bifurcation). Tatsumura further discloses, hardware configured to search for a ground state of an Ising model (pg. 64 column 2 paragraph 3 regarding the system finding the local minima, ground state). Tatsumura further discloses, coefficient memory configured to store a coefficient matrix and a coefficient vector (pg. 60 column 1 paragraph 6 regarding Jij as the coefficient matrix, and hi as the coefficient vector; Fig. 1 regarding JB1 as coefficient memory). Tatsumura further discloses, variable memory to store a main variable an auxiliary variable corresponding to Ising spins (pg. 60 column 2 paragraph 6 regarding xi (position), and pi (momentum), as a main variable and auxiliary variable respectively, corresponding to spins; Fig. 1 regarding XB1 as variable memory). Tatsumura further discloses, alternately repeating an auxiliary variable update, updating an auxiliary variable with a main variable, and a main variable update updating the main variable with the auxiliary variable (pg. 61 column 2 paragraph 3 regarding a self-evolution which alternately and repeatedly updates the momentum and position with the position updated depending on the momentum, and the momentum updated using the updated position). Tatsumura further discloses, an output circuit configured to transmit a value based on the main variable to a host apparatus (Fig. 1 regarding output of MMTE1 to X’mem). Tatsumura further discloses, outputting the discovered solution (pg. 60 column 1 paragraph 5 regarding outputting the discovered solution, s). However, Tatsumura fails to teach or suggest the italicized claim limitations in combination with the remaining claim limitations as referenced above. Tatsumura does not teach or suggest a setting circuit which writes the coefficient matrix and coefficient vector to the coefficient memory and causes the arithmetic circuit to start the search process in response to a command from the host apparatus. Tatsumura further does not teach or suggest coefficient memory storing a preceding coefficient matrix and a preceding coefficient vector until a new coefficient matrix and a new coefficient vector are written by the setting circuit. Instead, Tatsumura discloses coefficient memory, JBk which stores J data, with JBK being large, (pg. 62 column 2 paragraph 3), with JBK storing all coefficient data required, without updating with a new coefficient matrix and a new coefficient vector written to it.
Nasa MATSUMOTO et al., ("Distance-based clustering using QUBO formulations," SCIENTIFIC REPORTS, Vol. 12, Art. 2669, 10 pages, DOI: 10.1038/s41598-022-06559-z (2022)) hereinafter, “Matsumoto”, discloses an Information processing system for solving a combinatorial optimization problem (Pg. 1 paragraph 2 regarding clustering formulated as a combinatorial optimization problem; Pg. 1 paragraph 3 regarding a clustering method using an Ising machine). Matsumoto further discloses, an Ising machine searching for a ground state (Fig. 7 regarding the FPGA as an Ising machine and the Hamiltonian in Equation 3 is minimized). Matsumoto further discloses, a host apparatus (Fig. 7 CPU). Matsumoto further discloses alternately repeating an auxiliary variable update, updating an auxiliary variable with a main variable, and a main variable update updating the main variable with the auxiliary variable (pg. 8 regarding the ballistic SB, and using the symplectic Euler method to update yi, xi; Equations 8, 9). However, Matsumoto fails to teach or suggest the italicized claim limitations in combination with the remaining claim limitations as referenced above.
Ide (U.S. Patent Application Publication 2024/0127122 A1), hereinafter “Ide” discloses an information processing system for solving a combinatorial optimization problem (Fig. 1; [0089] regarding the optimization machine used to solve a combinatorial optimization problem). Ide further discloses, an Ising machine searching for a ground state ([0134] regarding searching for a ground state). However, Ide fails to teach or suggest the italicized claim limitations in combination with the remaining claim limitations as referenced above.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JEROME ANTHONY KLOSTERMAN II whose telephone number is (571)272-0541. The examiner can normally be reached Monday - Friday 8:30am-3:30pm ET.
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/J.A.K./ Examiner, Art Unit 2182 /EMILY E LAROCQUE/ Primary Examiner, Art Unit 2182
