Prosecution Insights
Last updated: August 17, 2026
Application No. 18/175,208

BURIED ZENER DIODE VOLTAGE REFERENCE WITH DIGITAL CORRECTION

Non-Final OA §103§112
Filed
Feb 27, 2023
Examiner
PELTON, NATHANIEL R
Art Unit
2859
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Texas Instruments Incorporated
OA Round
1 (Non-Final)
75%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
93%
With Interview

Examiner Intelligence

Grants 75% — above average
75%
Career Allowance Rate
561 granted / 748 resolved
+7.0% vs TC avg
Strong +18% interview lift
Without
With
+18.4%
Interview Lift
resolved cases with interview
Typical timeline
2y 9m
Avg Prosecution
36 currently pending
Career history
771
Total Applications
across all art units

Statute-Specific Performance

§101
1.7%
-38.3% vs TC avg
§103
56.9%
+16.9% vs TC avg
§102
20.3%
-19.7% vs TC avg
§112
12.6%
-27.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 748 resolved cases

Office Action

§103 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Continued Examination Under 37 CFR 1.114 A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after allowance or after an Office action under Ex Parte Quayle, 25 USPQ 74, 453 O.G. 213 (Comm'r Pat. 1935). Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, prosecution in this application has been reopened pursuant to 37 CFR 1.114. Applicant's submission filed on 06/15/2026 has been entered. Response to Amendment Acknowledgment is made of the amendment filed on 06/15/2026 in which claims 10-20 were amended and claims 21-30 added. Therefore, claims 10-30 are pending for examination below. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 10-15 and 21-30 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. With respect to claims 10 and 27, the claims were amended to include the ADC “having a sense input, a reference input, and an output, the reference input coupled to the reference input”. The claim lacks clarity as it stated it is connected to itself. Further, thereafter, there is introduced “a sense input” again which lacks antecedent basis. The claim as written is not able to be search until the clarity is fixed as the Examiner cannot guess the specific connections and how many sense inputs are present. Claims 11-15, 21-26, and 28-30 depend from the claims above and are rejected for the same reasons. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 16-17 and 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wilson et al. [US 2023/0179217] in view of Kalt [US 2018/0210027]. With respect to claim 16, Wilson discloses a method, comprising: receiving a battery voltage at an analog front end [via 102]; generating a reference voltage [par. 0047]; generating first signals representing of comparing the battery voltage by comparing the battery voltage to the reference voltage with an analog-to-digital converter (ADC) [via 130];and generating second signals based on the first signals and a sense signal [i.e. interaction of the ADC between receiving and input and supplying an output]. However, the internal component of a reference voltage is omitted. A voltage generator comprising Zener diodes and transistors is known in the art. For example, Kalt relates to testing devices and teaches a reference voltage generator with a Zener diode and bipolar junction transistors (BJTs) [par. 0055]. Therefore, it would have been obvious to a person having ordinary skill in the art before the filing date of the instant invention to modify Wilson to include a voltage reference generator with a diode and transistor for the benefit of the inherent ability to maintain a constant voltage output with the component even with varying load currents. With respect to claim 17, Wilson further discloses wherein the sense signal includes at least one of a temperature sense signal or a stress sense signal, and generating second signals based on the first signals and a sense signal includes performing a digital correction on the first signals responsive to the sense signal [par. 0148]. With respect to claim 19, Wilson further discloses wherein generating a reference voltage with a Zener diode and BJTs includes generating a first voltage having a first temperature coefficient, and generating a second voltage across the Zener diode having a second temperature coefficient different from the first temperature coefficient [par. 0148]. With respect to claim 20, Wilson further discloses wherein generating a reference voltage with a Zener diode and BJTs includes generating the reference voltage based on a difference between the first and second voltages [par. 0007]. Claim(s) 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wilson et al. [US 2023/0179217] and Kalt [US 2018/0210027] as applied above, and further in view of Gupta [US 11,251,803]. With respect to claim 18, Wilson fails to disclose multiple order correct as claimed. However, such a method is known in the art. For example, Gupta relates to correction devices and teaches wherein performing the digital correction includes: performing a second order digital correction for a gain error of the ADC; performing a second order digital correction for an offset error of the ADC; and performing a third order digital correction for the reference voltage [claims 1 and 23]. Therefore, it would have been obvious to a person having ordinary skill in the art before the filing date of the instant invention to modify Wilson to include the second and third orders for the benefit of improving accuracy of the measurements as suggested by Gupta. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to NATHANIEL R PELTON whose telephone number is (571)270-1761. The examiner can normally be reached M-F 9am to 5pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julian Huffman can be reached at 571-272-2147. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /NATHANIEL R PELTON/Primary Examiner, Art Unit 2859
Read full office action

Prosecution Timeline

Feb 27, 2023
Application Filed
Jun 15, 2026
Request for Continued Examination
Jun 18, 2026
Response after Non-Final Action
Jul 24, 2026
Non-Final Rejection mailed — §103, §112 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
75%
Grant Probability
93%
With Interview (+18.4%)
2y 9m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 748 resolved cases by this examiner. Grant probability derived from career allowance rate.

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