DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species i, claims 1-17, in the reply filed on 3/27/26 is acknowledged.
Claims 18, 19 and 28 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn nonelected Species ii and iii, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 3/27/26.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-6 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Jeong et al (US 2020/0194419 A1).
Regarding claim 1, Jeong et al discloses an integrated circuit (Figure 17) comprising: a first active pattern group extending in a first direction in a first row and including a plurality of first active patterns overlapping each other in the first direction (Figure 17, references F1-F4), the first row extending in the first direction (paragraph 0055); and a plurality of gate electrodes (Figure 17, references G1-G5) extending in a second direction that is perpendicular to the first direction in the first row (paragraphs 0058-0059), wherein the plurality of first active patterns comprise any two first active patterns that are adjacent to each other in the first direction (Figure 17, references F1-1 and F1-2), the two first active patterns have first and second widths in the second direction, respectively, and the first and second widths are identical or are different by a first offset or a second offset (Figure 17, references F1 and F2; paragraph 0172).
Regarding claim 2, Jeong et al discloses wherein the plurality of gate electrodes (Figure 17, references G1’-G5) extend in the second direction with a first pitch, the first and second widths are different (paragraph 0169), and the two first active patterns (Figure 17, references F1 and F2) are spaced apart from each other by at least the first pitch in the first direction (paragraphs 0169-0175).
Regarding claim 3, Jeong et al discloses wherein no active pattern (Figure 17, references F1-1 and F1-2) is between the two first active pattern (Figure 17, reference F1).
Regarding claim 4, Jeong et al discloses wherein each of the plurality of first active patterns has the first width or the second width that is wider than the first width by the first offset (Figure 17, references F1-F4; paragraphs 0170- 0175).
Regarding claim 5, Jeong et al discloses wherein the integrated circuit further comprises a second active pattern group extending in the first direction in a second row that is adjacent to the first row (Figure 17, references F5-F8), the second active pattern group including a plurality of second active patterns (Figure 17, reference F5-1 and F5-2) overlapping each other in the first direction (paragraph 0055), wherein the first row and the second row have different widths in the second direction (Figure 17, paragraphs 0170-0175).
Regarding claim 6, Jeong et al discloses wherein the plurality of second active patterns (Figure 17, references F5-F8) comprise any two second active patterns (Figure 17, references F5-1 and F5-2) that are adjacent to each other in the first direction and have an identical width in the second direction or have widths in the second direction that are different by a third offset or a fourth offset, and the third offset is different from the first offset and the second offset (Figure 17, references F1, F2, F5 and F6; paragraph 0172).
Allowable Subject Matter
Claims 7-17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The prior art does not disclose nor fairly suggest an integrated circuit comprising: wherein a widest width of the plurality of first active patterns in the second direction is different from a widest width of the plurality of second active patterns in the second direction (claim 7), wherein a narrowest width of the plurality of first active patterns in the second direction is different from a narrowest width of the plurality of second active patterns in the second direction (claim 8), further comprising a third active pattern group extending in the first direction in the first row and including a plurality of third active patterns overlapping each other in the first direction, wherein the plurality of third active patterns comprises any two third active patterns that are adjacent to each other in the first direction and have an identical width in the second direction or have widths in the second direction that are different by the first offset or the second offset (claim 9) and wherein each of the plurality of first active patterns comprises at least one nanosheet overlapping at least one of the plurality of gate electrodes in the second direction and a third direction, the third direction being perpendicular to the first direction and the second direction (claim 17), incorporated into the claims from which they depend from, further incorporated into independent claim 1 and in the context of its recited apparatus, along with its depending claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MONICA D HARRISON whose telephone number is (571)272-1959. The examiner can normally be reached M-F 7-4:30pm.
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/MONICA D HARRISON/Primary Examiner, Art Unit 2815
mdh
May 27, 2026
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