Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Response to Arguments
Applicant’s arguments with respect to claim 1 have been considered but are moot because the arguments do not apply to any of the references being used in the current rejection.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 5, 11 rejected under 35 U.S.C. 103 as being unpatentable over Lim et al. (US 2019/0137333) in view of Yamazaki et al. (US 2015/0144920); further in view of Yang et al. (US 2012/0026449).
Regarding claim 1, Lim et al. (figure 15) discloses an electronic device having an active area and a peripheral area, comprising:
a first substrate (58);
a second substrate (60) disposed opposite to the first substrate;
a sealant frame (65-2) disposed in the peripheral area and surrounding the active area;
a conductive member (68) disposed in the peripheral area; and
a wall structure (65-1, 86) disposed between the first substrate and the second substrate, wherein, when viewed in a top view direction, the wall structure is disposed between the sealant frame and the conductive member, wherein the wall structure, the sealant frame and the conductive member are disposed on the first substrate;
wherein the electronic device further comprises a conductive sealant (92) disposed on the first substrate, wherein the conductive member contacts the conductive sealant (92, 74, 68; see at least paragraph 0070);
wherein the electronic device further comprises an electrode layer (portion of 68) disposed on the first substrate.
Lim et al. discloses the limitations as shown in the rejection of claim 1 above. However, Lim et al. is silent regarding wherein the wall structure, the sealant frame and the conductive member are disposed on a first surface of an insulating layer and wherein the electronic device further comprises an electrode layer disposed on a second surface of the insulating layer, and the second surface is opposed to the first surface and wherein in a direction, a shortest distance between the sealant frame and the first substrate is arranged between 50µm and 200µm, wherein the direction is substantially perpendicular to the top view direction.
Yamazaki et al. (figures 1-4) teaches all the layers are disposed on a first surface of an insulating layer (171) and wherein the electronic device further comprises an electrode layer (144) disposed on a second surface of the insulating layer (171), and the second surface is opposed to the first surface. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the insulating layer as taught by Yamazaki et al. in order to prevent diffusion of impurities from the outside and enhance a bonding ability of the color filter substrate and the TFT substrate reduce the thickness of the display device.
In addition, Yang et al. (figures 1-2) wherein in a direction, a shortest distance between the sealant frame and the first substrate is arranged between 50µm and 200µm, wherein the direction is substantially perpendicular to the top view direction (the distance P between the sidewall at the outer edge 208b of the photo-curable sealant 208 and the sidewall of the first substrate 202 may be substantially smaller than or equal to 150 .mu.m; see at least paragraph 0051). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the sealant as taught by Yang et al. in order to achieve a design with ultra slim border in the LCD panel.
Therefore, Lim et al. as modified by Yamazaki et al. and Yang et al. teaches wherein the wall structure, the sealant frame and the conductive member are disposed on a first surface of an insulating layer and wherein the electronic device further comprises an electrode layer disposed on a second surface of the insulating layer, and the second surface is opposed to the first surface.
Regarding claim 2, Lim et al. (figure 15) discloses a circuit board (figure 2), wherein the circuit board includes a dummy pad connected to the conductive member through a conductive wire (92, 74, 68; see at least paragraph 0070).
Regarding claim 3, Lim et al. discloses the limitations as shown in the rejection of claim 1 above. However, Lim et al. is silent regarding wherein the conductive member includes at least one opening, and the conductive sealant is filled into the at least one opening. Yamazaki et al. (figures 1-4) teaches wherein the conductive member includes at least one opening, and the conductive sealant is filled into the at least one opening (165-166). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the conductive sealant as taught by Yamazaki et al. in order to enhance a bonding ability of the color filter substrate and the TFT substrate reduce the thickness of the display device.
Regarding claim 5, Lim et al. (figure 15) discloses wherein the conductive sealant is in contact with the wall structure (92 and 94).
Regarding claim 11, Lim et al. (figure 15) discloses wherein the conductive member is disposed on the first substrate, and at least part of the conductive member is disposed between the first substrate and the second substrate (68).
Claims 11-12 are rejected under 35 U.S.C. 103 as being unpatentable over Lim et al. in view of Yamazaki et al. and Yang et al.; further in view of Chan et al. (US 2019/0369431).
Regarding claim 11, Lim et al. discloses the limitations as shown in the rejection of claim 1 above. However, Lim et al. is silent regarding wherein the wall structure comprises a first wall and a second wall, the first blocking wall is disposed on the first substrate, the second wall is disposed on the second substrate, and a height of the first wall or a height of the second wall is smaller than a height of the sealant frame. Chan et al. (figures 2-4) teaches wherein the wall structure comprises a first wall and a second wall (1111 and 1112), the first blocking wall is disposed on the first substrate, the second wall is disposed on the second substrate, and a height of the first wall or a height of the second wall is smaller than a height of the sealant frame (figure 2). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the wall structure as taught by Chan et al. in order to enhance a bonding ability of the color filter substrate and the TFT substrate and achieve liquid crystal display panels with narrow borders.
Regarding claim 12, Chan et al. (figures 2-4) teaches wherein the first wall and the second wall are connected together.
Claims 13, 15-18 are rejected under 35 U.S.C. 103 as being unpatentable over Lim et al. in view of Yamazaki et al. and Yang et al.; further in view of Yoshikazu (JP 2007-34117).
Regarding claim 13, Lim et al. discloses the limitations as shown in the rejection of claim 1 above. However, Lim et al. is silent regarding wherein a contour shape of the first wall or the second wall projected in a first direction is a column shape or a trapezoid shape, and a contour edge of the first wall or the second wall projected in the first direction is step shape or a gently slope shape, wherein the first direction is different from the top view direction. Yoshikazu (figures 11-12b) teaches wherein a contour shape of the first wall or the second wall projected in a first direction is a column shape or a trapezoid shape, and a contour edge of the first wall or the second wall projected in the first direction is step shape or a gently slope shape, wherein the first direction is different from the top view direction (44). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the wall structure as taught by Yoshikazu in order to enhance a bonding ability of the color filter substrate and the TFT substrate and achieve liquid crystal display panels with narrow borders.
Regarding claim 15, Yoshikazu (figures 11-12b) teaches wherein the wall structure is formed by connecting a plurality of walls, and has a shape of periodic signal waveform.
Regarding claim 16, Yoshikazu (figures 11-12b) teaches wherein the wall structure includes a plurality of first extension portions, a plurality of second extension portions, a plurality of third extension portions and a plurality of fourth extension portions, in which a first extension portion is connected to a second extension portion, the second extension portion is connected to a third extension portion, the third extension portion is connected to a fourth extension portion, and the fourth extension portion is connected to another first extension portion.
Regarding claim 17, Yoshikazu (figures 11-12b) teaches wherein the first extension portion and the third extension portion extend in a second direction and are opposite to each other, and the second extension portion and the fourth extension portion extend in the first direction and are opposite to each other, where the second direction is different from the first direction and the top view direction.
Regarding claim 18, Yoshikazu (figures 11-12b) teaches wherein the first extension portion, the second extension portion and the third extension portion form a first accommodating space, the third extension portion, the fourth extension portion and the another first extension portion form a second accommodating space, in which the first accommodating space has an opening facing the first substrate, and the second accommodating space has an opening facing the sealant frame.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LAUREN NGUYEN whose telephone number is (571)270-1428. The examiner can normally be reached on Monday - Thursday, 8:00 AM -6:00 PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jennifer Carruth, can be reached at 571-272-9791. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/LAUREN NGUYEN/Primary Examiner, Art Unit 2871