Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This Office Action is in response to the application filed 02/28/2023 for 18/176,315.
Claims 1-27 are currently pending. Claims 28-46 have been canceled. Claims 1, 14, 20, and 26 are independent claims. Claims 1-27 have been examined. This Action is made non-FINAL.
Claim Interpretation - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as "configured to" or "so that"; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word "means," but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are: “streaming engines [] generat[ing data],” recited in claim 1; and “interface [] perform[ing] stream cipher operation … including generating a mask …, and XORing the generated mask,” recited in claims 1 and 14.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-27 are rejected under 35 USC 101 as being directed to an abstract idea without being integrated into a practical application or being significantly more.
Regarding claims 1, 14, 20, and 26 the claims are directed to an abstract idea as reciting the limitations “”generating a mash based on an encryption ID …” and “XORing the generated mask with the data word… Broadly interpreted, the aforementioned steps are directed to mathematical operations as said steps could be performed in the human mind or using pen and paper. Therefore, the claims recite an abstract idea.
Said abstract idea and/or judicial exception is not integrated into a practical application as the claim does not recite any other active steps that could be considered that the abstract idea is being integrated into a practical application. It’s noted that the claim recites the steps of “generating a mask.” However, said steps are not sufficient to consider that the abstract idea is being interpreted into a practical application. Said steps are recited at a high level of generality in gathering/processing/storing information, which are a form of insignificant extra-solution activity.
It’s also noted that the claims recite additional limitation/elements (i.e., streaming data streams, streaming engines, a hardware accelerator, host device, interface). However, said additional elements are recited at a high-level of generality (i.e., as a generic computing device performing a generic computer functions) such that it amounts no more than mere instructions to apply the exception or abstract idea using generic computer components. Accordingly, these additional elements do not integrate the abstract idea into a practical application because they do not impose any meaningful limits on practicing the abstract idea.
The claims do not include additional elements/limitations/embodiments that are sufficient to amount to significantly more than the judicial exception because the additional elements when considered both individually and as an ordered combination do not amount to significantly more than the abstract idea. As mentioned above, although the claims recite additional elements, said elements taken individually or as a combination, do not result in the claim amounting to significantly more than the abstract idea because as the additional elements perform generic computer content distributing functions routinely used in information technology field. As discussed above, the additional elements recited at a high-level of generality such that they amount no more than mere instructions to apply the exception using a generic computer component. Therefore, the claim is directed to non- statutory subject matter.
Regarding claims 2-15, 17-19, 21-25, and 27, claims 2-15, 17-19, 21-25, and 27 are also rejected under 35 U.S.C. 101 as being directed to non-statutory subject matter for the same reasons addressed above as the claims recite an abstract idea and the claims do not positively recite any other operations that could be considered as the abstract idea is being integrated into a practical application or significantly more. It’s noted that claim 23 recites the limitations: “incrementing….” Claim 24 recites the limitations: “streaming….” Claim 25 recites “streaming….” Said limitations/operations are either directed to mental processes and/or in a form of insignificant extra-solution activities and do not make the claims statutory. Therefore, claims 2-15, 17-19, 21-25, and 27 are also rejected under 35 U.S.C. 101 as being directed to non-statutory subject matter.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1, 2, 9-11, 14, 20, and 24-27 are rejected under 35 U.S.C. 103 as being unpatentable over Pope (US20220292042), filed March 11, 2021, in view of Urzi (US20150358300), filed March 12, 2015, and Reynolds (US4903219), filed January 27, 1998.
Regarding claim 1, Pope discloses a hardware accelerator, comprising: (Pope, paragraph 0059, engine, host computing device, paragraph 0097, hardware accelerator, virtual switch);
a plurality of functional circuits; a plurality of streaming engines coupled to the plurality of functional circuits, wherein the plurality of streaming engines, in operation, generate data streaming requests to stream data to and from functional circuits of the plurality of functional circuits (Pope, paragraph 0086, interface 112, controller 117 , memory fabric 140, DDR memory 142, paragraph 0167, streaming engines, controller, interface; paragraph 0220, host, engine, paragraph 0020, engines, streaming engine, host computing device; paragraph 0360, vSwitch, encrypted data; paragraph 0197, streaming engines; paragraph 0217, encryption/ decryption, encryption);
an interface coupled to the plurality of streaming engines, wherein the interface, in operation, performs stream cipher operations on data words associated with the data streaming requests, the performing a stream cipher operation on a data word including (Pope, paragraph 0059, engine, host computing device, paragraph 0097, hardware accelerator, virtual switch, paragraph 0097, hardware accelerator, virtual switch; paragraph 0333, virtual switch may be provided by the streaming subsystem; vSwitch, paragraph 0086, interface 112, controller 117 , memory fabric 140, DDR memory 142, paragraph 0167, streaming engines, controller, interface; paragraph 0220, host, engine, paragraph 0020, engines, streaming engine, host computing device; paragraph 0360, vSwitch, encrypted data; paragraph 0197, streaming engines; paragraph 0217, encryption/ decryption, encryption).
Pope does not explicitly disclose generating a mask based on an encryption ID associated with a streaming engine of the plurality of streaming engines, an address associated with the data word, and a stored key associated with the streaming engine.
However, in an analogous art, Urzi discloses generating a mask based on an encryption ID associated with a streaming engine of the plurality of streaming engines, an address associated with the data word, and a stored key associated with the streaming engine (Urzi, paragraph 0095, mask generated as a function of primary key, identification, and address).
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention to combine the teachings of Reynolds with the hardware accelerator/ system/ method/ non-transitory computer-readable medium of Pope and Urzi to include generating a mask based on an encryption ID associated with a streaming engine of the plurality of streaming engines, an address associated with the data word, and a stored key associated with the streaming engine. One would have been motivated to provide users with the benefits of handling multiple memory interfaces (Urzi: paragraph 0009).
Pope and Urzi do not explicitly disclose XORing the generated mask with the data word;
However, in an analogous art, Reynolds discloses XORing the generated mask with the data word (Reynolds, col. 6, lines 40-44, XOR the data word, mask; col. 6, lines 45-54, data word, mask, XOR; col. 6, lines 55-64, masks).
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention to combine the teachings of Reynolds with the hardware accelerator/ system/ method/ non-transitory computer-readable medium of Pope and Urzi to include generating a mask based on an encryption ID associated with a streaming engine of the plurality of streaming engines, an address associated with the data word, and a stored key associated with the streaming engine. One would have been motivated to provide users with the benefits of a recovery system for a diagnostic (Reynolds: col. 2, lines 25-30).
Regarding claim 2, Pope, Urzi, and Reynolds disclose the hardware accelerator of claim 1. Pope, Urzi, and Reynolds disclose comprising: a stream switch coupled between the plurality of streaming engines and the plurality of functional circuits (Pope, paragraph 0352, vSwitch, stream).
Regarding claim 9, Pope, Urzi, and Reynolds disclose the hardware accelerator of claim 1. Pope, Urzi, and Reynolds disclose wherein the interface, in operation, couples streaming engines of the plurality of streaming engines to a host device (Pope, paragraph 0005, interface, engines; paragraph 0007, interface coupled to host).
Regarding claim 10, Pope, Urzi, and Reynolds disclose the hardware accelerator of claim 9. Pope, Urzi, and Reynolds disclose wherein the data word is associated with a data streaming request to stream data from the hardware accelerator to the host device and the performing the cipher operation on the data word comprises encrypting the data word (Pope, paragraph 0214, encrypted, data; paragraph 0334, decrypted data).
Regarding claim 11, Pope, Urzi, and Reynolds disclose the hardware accelerator of claim 9. Pope, Urzi, and Reynolds disclose wherein the data word is associated with a data streaming request to stream data to the hardware accelerator from the host device and the performing the cipher operation on the data word comprises decrypting the data word (Pope, paragraph 0214, encrypted, data; paragraph 0334, decrypted data).
Regarding claim 14, Pope discloses a system, comprising:
a host device (Pope, paragraph 0059, engine, host computing device);
a hardware accelerator, the hardware accelerator including (Pope, paragraph 0097, hardware accelerator, virtual switch):
a stream switch (Pope, paragraph 0097, hardware accelerator, virtual switch; paragraph 0333, virtual switch may be provided by the streaming subsystem; vSwitch);
a plurality of functional circuits (Pope, paragraph 0086, interface 112, controller 117 , memory fabric 140, DDR memory 142);
a plurality of streaming engines, wherein the stream switch, in operation, selectively couples streaming engines of the plurality of streaming engines to functional circuits of the plurality of functional circuits (Pope, paragraph 0167, streaming engines, controller, interface; paragraph 0220, host, engine); and
an interface, which, in operation, selectively couples streaming engines of the plurality of streaming engines to the host device, wherein the interface, in operation, performs stream cipher operations on data words associated with data streamed between the host device and a streaming engine of the plurality of streaming engines, wherein the performing a stream cipher operation on a data word includes (Pope, paragraph 0020, engines, streaming engine, host computing device; paragraph 0360, vSwitch, encrypted data; paragraph 0197, streaming engines; paragraph 0217, encryption/ decryption, encryption).
Pope does not explicitly disclose generating a mask based on an encryption ID associated with a streaming engine of the plurality of streaming engines, an address associated with the data word and a stored key associated with the streaming engine.
However, in an analogous art, Urzi discloses generating a mask based on an encryption ID associated with a streaming engine of the plurality of streaming engines, an address associated with the data word and a stored key associated with the streaming engine (Urzi, paragraph 0095, mask generated as a function of primary key, identification, and address).
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention to combine the teachings of Reynolds with the hardware accelerator/ system/ method/ non-transitory computer-readable medium of Pope and Urzi to include generating a mask based on an encryption ID associated with a streaming engine of the plurality of streaming engines, an address associated with the data word and a stored key associated with the streaming engine. One would have been motivated to provide users with the benefits of handling multiple memory interfaces (Urzi: paragraph 0009).
Pope and Urzi do not explicitly disclose XORing the generated mask with the data word;
However, in an analogous art, Reynolds discloses XORing the generated mask with the data word (Reynolds, col. 6, lines 40-44, XOR the data word, mask; col. 6, lines 45-54, data word, mask, XOR; col. 6, lines 55-64, masks).
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention to combine the teachings of Reynolds with the hardware accelerator/ system/ method/ non-transitory computer-readable medium of Pope and Urzi to include XORing the generated mask with the data word. One would have been motivated to provide users with the benefits of a recovery system for a diagnostic (Reynolds: col. 2, lines 25-30).
Regarding claim 20, Pope discloses a method, comprising:
streaming data streams between streaming engines of a plurality of streaming engines of a hardware accelerator and functional circuits of a plurality of functional circuits of the hardware accelerator (Pope, paragraph 0167, streaming engines, controller, interface; paragraph 0220, host, engine, paragraph 0097, hardware accelerator, virtual switch; paragraph 0333, virtual switch may be provided by the streaming subsystem;); and
streaming data streams between a host device and streaming engines of the plurality of streaming engines of the hardware accelerator via an interface of the hardware accelerator, wherein the streaming of a data stream between the host device and a streaming engine of the plurality of streaming engines includes performing stream cipher operations on data words of the data stream, and the performing a stream cipher operation on a data word includes: (Pope, paragraph 0086, interface 112, controller 117 , memory fabric 140, DDR memory 142) (Pope, paragraph 0020, engines, streaming engine, host computing device; paragraph 0360, vSwitch, encrypted data; paragraph 0197, streaming engines; paragraph 0217, encryption/ decryption, encryption).
Pope does not explicitly disclose generating a mask based on an encryption ID associated with the streaming engine of the plurality of streaming engines, an address associated with the data word, and a stored key associated with the streaming engine of the plurality of streaming engines.
However, in an analogous art, Urzi discloses generating a mask based on an encryption ID associated with the streaming engine of the plurality of streaming engines, an address associated with the data word, and a stored key associated with the streaming engine of the plurality of streaming engines (Urzi, paragraph 0095, mask generated as a function of primary key, identification, and address).
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention to combine the teachings of Reynolds with the hardware accelerator/ system/ method/ non-transitory computer-readable medium of Pope and Urzi to include generating a mask based on an encryption ID associated with the streaming engine of the plurality of streaming engines, an address associated with the data word, and a stored key associated with the streaming engine of the plurality of streaming engines. One would have been motivated to provide users with the benefits of handling multiple memory interfaces (Urzi: paragraph 0009).
Pope and Urzi do not explicitly disclose XORing the generated mask with the data word.
However, in an analogous art, Reynolds discloses XORing the generated mask with the data word (Reynolds, col. 6, lines 40-44, XOR the data word, mask; col. 6, lines 45-54, data word, mask, XOR; col. 6, lines 55-64, masks).
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention to combine the teachings of Reynolds with the hardware accelerator/ system/ method/ non-transitory computer-readable medium of Pope and Urzi to include XORing the generated mask with the data word. One would have been motivated to provide users with the benefits of a recovery system for a diagnostic (Reynolds: col. 2, lines 25-30).
Regarding claim 24, Pope, Urzi, and Reynolds disclose the method of claim 20. Pope, Urzi, and Reynolds disclose comprising streaming the data stream from the hardware accelerator to the host device, wherein the performing the stream cipher operation on the data word comprises encrypting the data word (Pope, paragraph 0214, encrypted, data; paragraph 0334, decrypted data).
Regarding claim 25, Pope, Urzi, and Reynolds disclose the method of claim 20. Pope, Urzi, and Reynolds disclose comprising streaming the data stream from the host device to the hardware accelerator, wherein the performing the stream cipher operation on the data word comprises decrypting the data word (Pope, paragraph 0214, encrypted, data; paragraph 0334, decrypted data).
Regarding claim 26, Pope discloses a non-transitory computer-readable medium (Pope, paragraph 0457, memory) having contents which configure an interface of a hardware accelerator to stream data streams between streaming engines of a plurality of streaming engines of the hardware accelerator and a host system, the streaming of a data stream between a streaming engine of the plurality of streaming engines and the host device comprising (Pope, paragraph 0059, engine, host computing device, paragraph 0097, hardware accelerator, virtual switch; paragraph 0333, virtual switch may be provided by the streaming subsystem; vSwitch, paragraph 0086, interface 112, controller 117 , memory fabric 140, DDR memory 142, paragraph 0167, streaming engines, controller, interface; paragraph 0220, host, engine, paragraph 0020, engines, streaming engine, host computing device; paragraph 0360, vSwitch, encrypted data; paragraph 0197, streaming engines; paragraph 0217, encryption/ decryption, encryption).
Pope does not explicitly disclose generating a mask based on an encryption ID associated with the streaming engine of the plurality of streaming engines, an address associated with a data word of the data stream, and a stored key associated with the streaming engine.
However, in an analogous art, Urzi discloses generating a mask based on an encryption ID associated with the streaming engine of the plurality of streaming engines, an address associated with a data word of the data stream, and a stored key associated with the streaming engine (Urzi, paragraph 0095, mask generated as a function of primary key, identification, and address).
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention to combine the teachings of Reynolds with the hardware accelerator/ system/ method/ non-transitory computer-readable medium of Pope and Urzi to include generating a mask based on an encryption ID associated with the streaming engine of the plurality of streaming engines, an address associated with a data word of the data stream, and a stored key associated with the streaming engine. One would have been motivated to provide users with the benefits of handling multiple memory interfaces (Urzi: paragraph 0009).
Pope and Urzi do not explicitly disclose XORing the generated mask with the data word.
However, in an analogous art, Reynolds discloses XORing the generated mask with the data word (Reynolds, col. 6, lines 40-44, XOR the data word, mask; col. 6, lines 45-54, data word, mask, XOR; col. 6, lines 55-64, masks).
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention to combine the teachings of Reynolds with the hardware accelerator/ system/ method/ non-transitory computer-readable medium of Pope and Urzi to include XORing the generated mask with the data word. One would have been motivated to provide users with the benefits of a recovery system for a diagnostic (Reynolds: col. 2, lines 25-30).
Regarding claim 27, Pope, Urzi, and Reynolds disclose the non-transitory computer-readable medium of claim 26. Pope, Urzi, and Reynolds disclose wherein :the contents comprise instructions executed by the interface of the hardware accelerator (Pope, paragraph 0080, interfaces, deliver data, accelerator).
Claims 3, 4, 15, and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Pope (US20220292042), filed March 11, 2021, in view of Urzi (US20150358300), filed March 12, 2015, and Reynolds (US4903219), filed January 27, 1998, and further in view of Bidault (US20210150688), filed November 18, 2019.
Regarding claim 3, Pope, Urzi, and Reynolds disclose the hardware accelerator of claim 2.
Pope, Urzi, and Reynolds do not explicitly disclose wherein the plurality of functional circuits includes multiple convolutional accelerators.
However, in an analogous art, Bidault discloses wherein the plurality of functional circuits includes multiple convolutional accelerators (Bidault, paragraph 0089, convolutional accelerators).
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention to combine the teachings of Bidault with the hardware accelerator/ system/ method/ non-transitory computer-readable medium of Pope, Urzi, and Reynolds to include wherein the plurality of functional circuits includes multiple convolutional accelerators. One would have been motivated to provide users with the benefits of training embedded systems (Bidault: paragraph 0001).
Regarding claim 4, Pope, Urzi, and Reynolds disclose the hardware accelerator of claim 1.
Pope, Urzi, and Reynolds do not explicitly disclose wherein the interface includes a pool of stream cipher engines and control circuitry, and the control circuitry, in operation, schedules performance, by stream cipher engines of the pool of stream cipher engines, of the stream cipher operations on the data words associated with the data streaming requests.
However, in an analogous art, Bidault discloses wherein the interface includes a pool of stream cipher engines and control circuitry, and the control circuitry, in operation, schedules performance, by stream cipher engines of the pool of stream cipher engines, of the stream cipher operations on the data words associated with the data streaming requests (Bidault, paragraph 0012, activation function, circuitry, pooling layer; paragraph 0027, convolutional accelerators)(Pope, paragraph 0320, streaming data, scheduler).
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention to combine the teachings of Bidault with the hardware accelerator/ system/ method/ non-transitory computer-readable medium of Pope, Urzi, and Reynolds to include wherein the plurality of functional circuits includes multiple convolutional accelerators. One would have been motivated to provide users with the benefits of training embedded systems (Bidault: paragraph 0001).
Regarding claim 15, Pope, Urzi, and Reynolds disclose the system of claim 14.
Pope, Urzi, and Reynolds do not explicitly disclose wherein the plurality of functional circuits includes multiple convolutional accelerators.
However, in an analogous art, Bidault discloses wherein the plurality of functional circuits includes one or more convolutional accelerators, one or more pooling circuits, and one or more activation circuits (Bidault, paragraph 0012, activation function, circuitry, pooling layer; paragraph 0027, convolutional accelerators).
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention to combine the teachings of Bidault with the hardware accelerator/ system/ method/ non-transitory computer-readable medium of Pope, Urzi, and Reynolds to include wherein the plurality of functional circuits includes one or more convolutional accelerators, one or more pooling circuits, and one or more activation circuits. One would have been motivated to provide users with the benefits of training embedded systems (Bidault: paragraph 0001).
Regarding claim 16, Pope, Urzi, Reynolds, and Bidault disclose the system of claim 15. Pope, Urzi, Reynolds, and Bidault disclose wherein the interface includes a pool of stream cipher engines and control circuitry, and the control circuitry, in operation, schedules performance, by stream cipher engines of the pool of stream cipher engines, of the stream cipher operations on the data words associated with data streamed between the host device and a streaming engine of the plurality of streaming engines (Bidault, paragraph 0012, activation function, circuitry, pooling layer; paragraph 0027, convolutional accelerators)(Pope, paragraph 0320, streaming data, scheduler).
Claims 5 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Pope (US20220292042), filed March 11, 2021, in view of Urzi (US20150358300), filed March 12, 2015, Reynolds (US4903219), filed January 27, 1998, and Bidault (US20210150688), filed November 18, 2019, and further in view of Harrison (US20210217001), filed January 10, 2020.
Regarding claim 5, Pope, Urzi, Reynolds, and Bidault disclose the hardware accelerator of claim 4.
Pope, Urzi, Reynolds, and Bidault do not explicitly disclose wherein the pool of stream cipher engines comprises a plurality of keccak stream cipher engines.
However, in an analogous art, Harrison discloses wherein the pool of stream cipher engines comprises a plurality of keccak stream cipher engines (Harrison, paragraph 0051, crypto processors, cryptographic engines, encryption, Keccak).
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention to combine the teachings of Harrison with the hardware accelerator/ system/ method/ non-transitory computer-readable medium of Pope, Urzi, Reynolds, and Bidault to include wherein the pool of stream cipher engines comprises a plurality of keccak stream cipher engines. One would have been motivated to provide users with the benefits of a secure hash algorithm (Harrison: paragraph 0051)
Regarding claim 17, Pope, Urzi, Reynolds, and Bidault disclose the system of claim 16.
Pope, Urzi, Reynolds, and Bidault do not explicitly disclose wherein the pool of stream cipher engines comprises a plurality of keccak stream cipher engines.
However, in an analogous art, Harrison discloses wherein the pool of stream cipher engines comprises a plurality of keccak stream cipher engines (Harrison, paragraph 0051, crypto processors, cryptographic engines, encryption, Keccak).
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention to combine the teachings of Harrison with the hardware accelerator/ system/ method/ non-transitory computer-readable medium of Pope, Urzi, Reynolds, and Bidault to include wherein the pool of stream cipher engines comprises a plurality of keccak stream cipher engines. One would have been motivated to provide users with the benefits of a secure hash algorithm (Harrison: paragraph 0051)
Claims 21 is rejected under 35 U.S.C. 103 as being unpatentable over Pope (US20220292042), filed March 11, 2021, in view of Urzi (US20150358300), filed March 12, 2015, and Reynolds (US4903219), filed January 27, 1998, and further in view of Harrison (US20210217001), filed January 10, 2020.
Regarding claim 21, Pope, Urzi, and Reynolds disclose the method of claim 20.
Pope, Urzi, and Reynolds do not explicitly disclose wherein the interface includes a pool of keccak stream cipher engines, and the method includes scheduling performance, by a stream cipher engine of the pool of keccak stream cipher engines, of the stream cipher operation on the data word.
However, in an analogous art, Harrison discloses wherein the interface includes a pool of keccak stream cipher engines, and the method includes scheduling performance, by a stream cipher engine of the pool of keccak stream cipher engines, of the stream cipher operation on the data word (Harrison, paragraph 0051, crypto processors, cryptographic engines, encryption, Keccak).
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention to combine the teachings of Harrison with the hardware accelerator/ system/ method/ non-transitory computer-readable medium of Pope, Urzi, and Reynolds to include wherein the interface includes a pool of keccak stream cipher engines, and the method includes scheduling performance, by a stream cipher engine of the pool of keccak stream cipher engines, of the stream cipher operation on the data word. One would have been motivated to provide users with the benefits of a secure hash algorithm (Harrison: paragraph 0051).
Claims 6, 7, 18, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Pope (US20220292042), filed March 11, 2021, in view of Urzi (US20150358300), filed March 12, 2015, and Reynolds (US4903219), filed January 27, 1998, and further in view of Lorie (US5146590), filed February 5, 1992.
Regarding claim 6, Pope, Urzi, and Reynolds disclose the hardware accelerator of claim 1.
Pope, Urzi, and Reynolds do not explicitly disclose wherein the interface includes wherein, in operation, an encryption ID associated with a streaming engine of the plurality of streaming engines is set at a start of a processing epoch.
However, in an analogous art, Lorie discloses wherein, in operation, an encryption ID associated with a streaming engine of the plurality of streaming engines is set at a start of a processing epoch (Lorie, col. 7, line 52, through col. 8, line 3, stream, target processor, subrange, key value, key value).
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention to combine the teachings of Lorie with the hardware accelerator/ system/ method/ non-transitory computer-readable medium of Pope, Urzi, and Reynolds to include wherein, in operation, an encryption ID associated with a streaming engine of the plurality of streaming engines is set at a start of a processing epoch. One would have been motivated to provide users with the benefits of sorting data distributed across multiple processors (Lorie: col. 1, lines 11-14).
Regarding claim 7, Pope, Urzi, Reynolds, and Lorie disclose the hardware accelerator of claim 6. Pope, Urzi, Reynolds, and Lorie disclose wherein, in operation, respective encryption IDs associated with each of the streaming engines of the plurality of streaming engines are set at the start of the processing epoch (Lorie, col. 7, line 52, through col. 8, line 3, stream, target processor, subrange, key value, key value).
Regarding claim 18, Pope, Urzi, and Reynolds disclose the system of claim 14.
Pope, Urzi, and Reynolds do not explicitly disclose wherein, in operation, respective encryption IDs associated with streaming engines of the plurality of streaming engines are initialized at a start of a processing epoch.
However, in an analogous art, Lorie discloses wherein, in operation, respective encryption IDs associated with streaming engines of the plurality of streaming engines are initialized at a start of a processing epoch (Lorie, col. 7, line 52, through col. 8, line 3, stream, target processor, subrange, key value, key value).
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention to combine the teachings of Lorie with the hardware accelerator/ system/ method/ non-transitory computer-readable medium of Pope, Urzi, and Reynolds to include wherein, in operation, respective encryption IDs associated with streaming engines of the plurality of streaming engines are initialized at a start of a processing epoch. One would have been motivated to provide users with the benefits of sorting data distributed across multiple processors (Lorie: col. 1, lines 11-14).
Regarding claim 22, Pope, Urzi, and Reynolds disclose the method of claim 20.
Pope, Urzi, and Reynolds do not explicitly disclose comprising setting a respective encryption ID associated with each streaming engine of the plurality of streaming engines at a start of a processing epoch by the hardware accelerator.
However, in an analogous art, Lorie discloses comprising setting a respective encryption ID associated with each streaming engine of the plurality of streaming engines at a start of a processing epoch by the hardware accelerator (Lorie, col. 7, line 52, through col. 8, line 3, stream, target processor, subrange, key value, key value).
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention to combine the teachings of Lorie with the hardware accelerator/ system/ method/ non-transitory computer-readable medium of Pope, Urzi, and Reynolds to include comprising setting a respective encryption ID associated with each streaming engine of the plurality of streaming engines at a start of a processing epoch by the hardware accelerator. One would have been motivated to provide users with the benefits of sorting data distributed across multiple processors (Lorie: col. 1, lines 11-14).
Claims 8, 19, and 23 are rejected under 35 U.S.C. 103 as being unpatentable over Pope (US20220292042), filed March 11, 2021, in view of Urzi (US20150358300), filed March 12, 2015, Reynolds (US4903219), filed January 27, 1998, and Lorie (US5146590), filed February 5, 1992, and further in view of Ibi (US20030118189), filed March 20, 2002.
Regarding claim 8, Pope, Urzi, Reynolds, and Lorie disclose the hardware accelerator of claim 6.
Pope, Urzi, Reynolds, and Lorie do not explicitly disclose wherein, in operation, an encryption ID associated with the streaming engine of the plurality of streaming engines is incremented between iterative processing rounds of the processing epoch.
However, in an analogous art, Ibi discloses wherein, in operation, an encryption ID associated with the streaming engine of the plurality of streaming engines is incremented between iterative processing rounds of the processing epoch (Ibi, paragraph 0091, incrementing a key ID counter; encryption processing unit).
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention to combine the teachings of Lorie with the hardware accelerator/ system/ method/ non-transitory computer-readable medium of Pope, Urzi, Reynolds, and Lorie to include wherein, in operation, an encryption ID associated with the streaming engine of the plurality of streaming engines is incremented between iterative processing rounds of the processing epoch. One would have been motivated to provide users with the benefits of dispersing encryption processing load (Ibi: paragraph 0001).
Regarding claim 19, Pope, Urzi, Reynolds, and Lorie disclose the system of claim 18.
Pope, Urzi, Reynolds, and Lorie do not explicitly disclose wherein, in operation, an encryption ID associated with a streaming engine of the plurality of streaming engines is incremented between rounds of iterative processing of the processing epoch.
However, in an analogous art, Ibi discloses wherein, in operation, an encryption ID associated with a streaming engine of the plurality of streaming engines is incremented between rounds of iterative processing of the processing epoch (Ibi, paragraph 0091, incrementing a key ID counter; encryption processing unit).
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention to combine the teachings of Lorie with the hardware accelerator/ system/ method/ non-transitory computer-readable medium of Pope, Urzi, Reynolds, and Lorie to include wherein, in operation, an encryption ID associated with a streaming engine of the plurality of streaming engines is incremented between rounds of iterative processing of the processing epoch. One would have been motivated to provide users with the benefits of dispersing encryption processing load (Ibi: paragraph 0001).
Regarding claim 23, Pope, Urzi, Reynolds, and Lorie disclose the method of claim 22.
Pope, Urzi, Reynolds, and Lorie do not explicitly disclose comprising incrementing an encryption ID associated with a streaming engine of the plurality of streaming engines between iterative rounds of processing of the processing epoch.
However, in an analogous art, Ibi discloses comprising incrementing an encryption ID associated with a streaming engine of the plurality of streaming engines between iterative rounds of processing of the processing epoch (Ibi, paragraph 0091, incrementing a key ID counter; encryption processing unit).
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention to combine the teachings of Lorie with the hardware accelerator/ system/ method/ non-transitory computer-readable medium of Pope, Urzi, Reynolds, and Lorie to include comprising incrementing an encryption ID associated with a streaming engine of the plurality of streaming engines between iterative rounds of processing of the processing epoch. One would have been motivated to provide users with the benefits of dispersing encryption processing load (Ibi: paragraph 0001).
Claims 12 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Pope (US20220292042), filed March 11, 2021, in view of Urzi (US20150358300), filed March 12, 2015, and Reynolds (US4903219), filed January 27, 1998, and further in view of Harriman (US20200151362), filed January 10, 2020.
Regarding claim 12, Pope, Urzi, and Reynolds disclose the hardware accelerator of claim 1.
Pope, Urzi, and Reynolds disclose functional circuits associated with a second security state are restricted to performing functional operations associated with the second security state (Pope, paragraph 0086, interface 112, controller 117 , memory fabric 140, DDR memory 142);
streaming engines associated with the second security state are restricted to performing streaming operations associated with the second security state (Pope, paragraph 0167, streaming engines, controller, interface; paragraph 0220, host, engine).
Pope, Urzi, and Reynolds do not explicitly disclose configuration registers, which, in operation, store configuration information indicating a respective security state associated with each functional circuit of the plurality of functional circuits and a respective security state associated with each streaming engine of the plurality of streaming engines, wherein, in a secure mode of operation: functional circuits associated with a first security state are restricted to performing functional operations associated with the first security state; streaming engines associated with the first security state are restricted to performing streaming operations associated with the first security state.
However, in an analogous art, Harriman discloses configuration registers, which, in operation, store configuration information indicating a respective security state associated with each functional circuit of the plurality of functional circuits and a respective security state associated with each streaming engine of the plurality of streaming engines, wherein, in a secure mode of operation: functional circuits associated with a first security state are restricted to performing functional operations associated with the first security state (Harriman, paragraph 0208, configuration registers; paragraph 0211, security state);
streaming engines associated with the first security state are restricted to performing streaming operations associated with the first security state (Harriman, paragraph 0236, secure stream protocol operating in a restricted ordering mode).
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention to combine the teachings of Lorie with the hardware accelerator/ system/ method/ non-transitory computer-readable medium of Pope, Urzi, and Reynolds to include configuration registers, which, in operation, store configuration information indicating a respective security state associated with each functional circuit of the plurality of functional circuits and a respective security state associated with each streaming engine of the plurality of streaming engines, wherein, in a secure mode of operation: functional circuits associated with a first security state are restricted to performing functional operations associated with the first security state; streaming engines associated with the first security state are restricted to performing streaming operations associated with the first security state. One would have been motivated to provide users with the benefits of internet security (Harriman: paragraph 0031).
Regarding claim 13, Pope, Urzi, Reynolds, and Harriman disclose the hardware accelerator of claim 12. Pope, Urzi, Reynolds, and Harriman disclose wherein: the first security state is a secure security state; the second security state is a non-secure security state; operations associated with the first security state are operations of a secure network; and operations associated with the second security state are operations of a non-secure network (Harriman, paragraph 0236, secure stream protocol operating in a restricted ordering mode; paragraph 0247, non-secure).
Conclusion
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/W.J.M/
Examiner, Art Unit 2439
/LUU T PHAM/Supervisory Patent Examiner, Art Unit 2439