DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
The Examiner acknowledges the applicant's submission of the amendment dated 12/31/25, which has been entered.
1. REJECTIONS BASED ON PRIOR ART
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC ' 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wang (US 10552153) in view of Sistla (US 20080126707) and Strahl (US 20060230085).
With respect to claim 1, the Wang reference teaches a method for flushing cache lines, comprising:
sending, by a processor core in a processor, a flush packet in a broadcast manner via an internal bus of the processor to a set of caches of the processor, (column 5, line 60 to column 6, line 24, where the ARFLUSH instruction invalidates all cache lines in the processor cache that contain a memory address included in the contiguous region. The processor cache referred to here may be IL1, DL1, L2, or a combination thereof. In some embodiments, the invalidation is broadcasted throughout the cache coherence domain and may include cache(s) on other core(s). In one embodiment, any invalidated cache lines in the processor cache that are dirty (e.g., modified) are written back to the system memory) wherein the flush packet carries information identifying a range of physical addresses of multiple cache lines that are to be flushed) wherein the flush request carries information identifying a range of physical addresses of multiple cache lines that are to be flushed; (column 5, line 60 to column 6, line 25, where there is range-based flushing of a processor cache, instruction ARFLUSH; and the range could include physical addresses) and
receiving, by a first cache in the set of caches, the flush packet sent by the processor core; (see fig. 7; and column 9, line 19-59, where a determination is made at block 712 on whether the cache line is to be flushed or invalidated. According to an embodiment, this is based on whether the request is to flush/invalidate the cache line or simply to writeback to memory. As described above, an ARFLUSH instruction flushes/invalidates a cache line in the processor cache irrespective of whether the cache line is dirty or not)
flushing, by the first cache, cache lines that are in the first cache and are within the range of physical addresses identified by the flush packet; (see fig. 7; and column 9, line 19-59, where a determination is made at block 712 on whether the cache line is to be flushed or invalidated. According to an embodiment, this is based on whether the request is to flush/invalidate the cache line or simply to writeback to memory. As described above, an ARFLUSH instruction flushes/invalidates a cache line in the processor cache irrespective of whether the cache line is dirty or not; and column 5, line 60 to column 6, line 25, where there is range-based flushing of a processor cache, instruction ARFLUSH; and the range could include physical addresses)
sending, by the first cache, a flush completion packet to the processor core; (column 8, lines 57-65, where a status bit is set upon the completion of the whole flow, which will then be checked by an ordering instruction (e.g., MFENCE) for serialization purpose)
receiving, by processor core, flush completion packets from responding caches in the set of caches, wherein the responding caches comprise the multiple cache lines to be flushed, and the flush completion packets include the flush completion packet from the first cache. (column 5 line 60 to column 6, line 24, where any invalidated cache lines in the processor cache that are dirty (e.g., modified) are written back to the system memory; and column 8, lines 57-65, where a status bit is set upon the completion of the whole flow, which will then be checked by an ordering instruction (e.g., MFENCE) for serialization purpose)
However, the Wang reference does not explicitly teach wherein the first cache is a distributed cache device not included in the processor core; and wherein the flush packet comprises a page type of each page.
The Sistla reference teaches it is conventional to have wherein the first cache is a distributed cache device not included in the processor core. (see fig. 3; and paragraph 33, where referring to FIG. 3, an exemplary block diagram of multi-core processor 20 having a distributed shared cache configuration is shown. As shown, shared caches 210.sub.1-210.sub.N are distributed among the multiple cores 220.sub.1-220.sub.N. External to and associated with cores 220.sub.1-220.sub.N and coupled to an on-die interconnect 240, each controller 230.sub.1-230.sub.N is responsible for maintaining coherency of shared caches 210.sub.1-210.sub.N, respectively)
It would have been obvious to a person of ordinary skill in the art before the claimed invention was effectively filed to modify the Wang reference to have
wherein the first cache is a distributed cache device not included in the processor core, as taught by the Sistla reference.
The suggestion/motivation for doing so would have been to a system that is high-speed and scalable to ensure that the distributed shared caches accesses have a low latency since on-die interconnect that lies in a critical path. (paragraph 33)
However, the combination of the Wang and Sistla reference does not explicitly teach wherein the flush packet comprises a page type of each page.
The Strahl reference teaches it is conventional to have wherein the flush packet comprises a page type of each page. (paragraph 29, where process 200 may be triggered or started each time data cache 112 is flushed (or each time modified pages held in data cache 112 are to be committed to data volumes 116). For example, in some database systems, the data cache may be flushed every few minutes or any time the number or size of the pages in the cache exceeds a predetermined threshold [i.e. a page type’])
It would have been obvious to a person of ordinary skill in the art before the claimed invention was effectively filed to modify the Wang reference to have
wherein the flush packet comprises a page type of each page, as taught by the Strahl reference.
The suggestion/motivation for doing so would have been to allow this writing to be performed efficiently and in a manner that enables the data to be read back efficiently as well
Therefore it would have been obvious to combine the Wang, Sistla, and Strahl references for the benefits shown above to obtain the invention as specified in the claim.
With respect to claim 2, the combination of the Wang, Sistla, and Strahl references teaches the method according to claim 1, wherein the multiple cache lines to be flushed include consecutive cache lines. (Wang, column 6, line 50-57, where the ARFLUSHS instruction behaves exactly the same as the ARFLUSH instruction, but flushes out cache lines in the contiguous region to a shared cache instead of all the way to system memory)
With respect to claim 3, the combination of the Wang, Sistla, and Strahl references teaches the method according to claim 2, wherein the flush packet comprises information indicating a physical address in a segment of continuous physical address space, and multiple cache lines comprise a cache line in which a start physical address in the segment of continuous physical address space is located to a cache line in which an end physical address in the segment of continuous physical address space is located. (Wang, column 5, line 60 to column 6, line 25, where the ARFLUSH instruction is in the following format: ARFLUSH{S} mem_addr, range and where the mem_addr operand is a memory address, the range operand is a range indicator, and S is an optional opcode. Together, the mem_addr operand and the range operand define a contiguous region in the system memory)
With respect to claim 4, the combination of the Wang, Sistla, and Strahl references teaches the method according to claim 3, wherein the continuous physical address space is a physical address space mapped to a main memory, a physical address in a to-be-flushed continuous physical address space is aligned with a physical address of a cache line, and the to-be-flushed continuous physical address space is a space measured by a cache line size. (Wang, column 5, line 60 to column 6, line 25, where the ARFLUSH instruction is in the following format: ARFLUSH{S} mem_addr, range and where the mem_addr operand is a memory address, the range operand is a range indicator, and S is an optional opcode. Together, the mem_addr operand and the range operand define a contiguous region in the system memory)
With respect to claim 5, the combination of the Wang, Sistla, and Strahl references teaches the method according to claim 3, wherein the information about the physical address in the segment of continuous physical address space comprises a start physical address of a page, and wherein the flush packet further comprises a page type describes a size of the page. (Wang, column 5, line 60 to column 6, line 25, where the ARFLUSH instruction is in the following format: ARFLUSH{S} mem_addr, range and where the mem_addr operand is a memory address, the range operand is a range indicator, and S is an optional opcode. Together, the mem_addr operand and the range operand define a contiguous region in the system memory; and column 5, line 12-35, where the instructions and data stored within the various processor caches are managed at the granularity of cache lines which may be a fixed size (e.g., 64, 128, 512 Bytes in length) [equivalent to a ‘page’ and ‘page size’])
With respect to claim 6, the combination of the Wang, Sistla, and Strahl references teaches the method according to claim 3, wherein the information about the physical address in the segment of continuous physical address space comprises a start physical address of a page and an end physical address of the page. (Wang, column 5, line 60 to column 6, line 25, where the ARFLUSH instruction is in the following format: ARFLUSH{S} mem_addr, range and where the mem_addr operand is a memory address, the range operand is a range indicator, and S is an optional opcode. Together, the mem_addr operand and the range operand define a contiguous region in the system memory; and column 5, line 12-35, where the instructions and data stored within the various processor caches are managed at the granularity of cache lines which may be a fixed size (e.g., 64, 128, 512 Bytes in length) [equivalent to a ‘page’ and ‘page size’])
With respect to claim 7, the combination of the Wang, Sistla, and Strahl references teaches the method according to claim 3, wherein the information about the physical address in the segment of continuous physical address space comprises a physical address of a cache line in at least one page, and wherein the flush packet further comprises a page type of each page, and the page type describes a size of the page. (Wang, column 5, line 60 to column 6, line 25, where the ARFLUSH instruction is in the following format: ARFLUSH{S} mem_addr, range and where the mem_addr operand is a memory address, the range operand is a range indicator, and S is an optional opcode. Together, the mem_addr operand and the range operand define a contiguous region in the system memory; and column 5, line 12-35, where the instructions and data stored within the various processor caches are managed at the granularity of cache lines which may be a fixed size (e.g., 64, 128, 512 Bytes in length) [equivalent to a ‘page’ and ‘page size’])
With respect to claim 8, the combination of the Wang, Sistla, and Strahl references teaches the method according to claim 3, wherein the information about the physical address in the segment of continuous physical address space comprises a physical address of one cache line and a quantity of cache lines. (Wang, column 5, line 60 to column 6, line 25, where the ARFLUSH instruction is in the following format: ARFLUSH{S} mem_addr, range and where the mem_addr operand is a memory address, the range operand is a range indicator, and S is an optional opcode. Together, the mem_addr operand and the range operand define a contiguous region in the system memory; and column 5, line 12-35, where the instructions and data stored within the various processor caches are managed at the granularity of cache lines which may be a fixed size (e.g., 64, 128, 512 Bytes in length))
With respect to claim 9, the combination of the Wang, Sistla, and Strahl references teaches the method according to claim 3, wherein the information about the physical address in the segment of continuous physical address space comprises one physical address and an immediate, and the immediate indicates a quantity of low-order bits in the physical address. (Wang, column 1, line 52 to 56, where an instruction set includes one or more instruction formats. A given instruction format defines various fields (number of bits, location of bits) to specify, among other things, the operation to be performed and the operand(s) on which that operation is to be performed)
With respect to claim 10, the combination of the Wang, Sistla, and Strahl references teaches the method according to claim 1, wherein the multiple cache lines to be flushed include non-consecutive cache lines. (Wang, column 5 line 60 to column 6, line 24, where any invalidated cache lines [which could be ‘non-consecutive’] in the processor cache that are dirty (e.g., modified) are written back to the system memory)
Claims 11-14 are another cache flushing method similar to claims 1-10 noted above. The Examiner notes that these claims are from the cache’s point of view of receiving the commands and performing the commands and sending a completion notification, and are rejected under the same rationale as claims 1-10.
Claims 15-19 are the processor implementation of claims 1-10, and rejected under the same rationale. The Examiner notes the limitations of “a processor core; an internal bus; and a set of caches” are shown by figs. 1-3 and corresponding text.
Claim 20 is a computing device implementation of claims 11-14, and rejected under the same rationale as above. The Examiner notes the limitations of “a processor comprising a processor core, an internal bus, and a set of caches; and a main memory;” are shown by figs. 1-3 and corresponding text.
2. ARGUMENTS CONCERNING NON-PRIOR ART REJECTIONS/OBJECTIONS
Rejections - USC 112
Applicant's arguments and amendments with respect to claims 1-10 have been considered and have overcome the Examiner’s prior rejections and thus are withdrawn.
3. ARGUMENTS CONCERNING PRIOR ART REJECTIONS
Rejections - USC 102/103
Applicant's amendments and arguments (see pages 8-11 of the remarks) with respect to claims 1-20 have been considered, and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Strahl as shown in the rejections above to teach the newly added limitations.
4. CLOSING COMMENTS
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PRASITH THAMMAVONG whose telephone number is (571) 270-1040. The examiner can normally be reached Monday - Friday 12-8 PM EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Arpan Savla can be reached on (571) 272-1077. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/PRASITH THAMMAVONG/
Primary Examiner, Art Unit 2137
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