Prosecution Insights
Last updated: April 19, 2026
Application No. 18/177,168

STORAGE MEDIUM, EQUIVALENT CIRCUIT ANALYSIS APPARATUS, AND EQUIVALENT CIRCUIT ANALYSIS METHOD

Non-Final OA §102
Filed
Mar 02, 2023
Examiner
NGO, BRIAN
Art Unit
2851
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Fujitsu Limited
OA Round
1 (Non-Final)
88%
Grant Probability
Favorable
1-2
OA Rounds
2y 4m
To Grant
99%
With Interview

Examiner Intelligence

Grants 88% — above average
88%
Career Allow Rate
851 granted / 967 resolved
+20.0% vs TC avg
Moderate +12% lift
Without
With
+12.2%
Interview Lift
resolved cases with interview
Typical timeline
2y 4m
Avg Prosecution
24 currently pending
Career history
991
Total Applications
across all art units

Statute-Specific Performance

§101
14.2%
-25.8% vs TC avg
§103
36.9%
-3.1% vs TC avg
§102
38.3%
-1.7% vs TC avg
§112
7.0%
-33.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 967 resolved cases

Office Action

§102
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. DETAILED ACTION This Non-Final office is a response to the papers filed on 03/02/2023 . Claims 1-15 are pending. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale , or otherwise available to the public before the effective filing date of the claimed invention. Claims 1 -15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lin et al. (Pub. No. 2005/0055654 A1) . Regarding claim s 1 , 6, and 11 , Lin discloses: A non-transitory computer-readable storage medium storing an equivalent circuit analysis program that causes at least one computer to execute a process (see par [0008], when the IC layout is done according to the currently used IC CAD (computer aided design) software, there are no known objective and effective rules and methods to judge ….. ) , the process comprising: specifying a surface pattern included in first circuit information (see Fig. 6 A-6B, see par [0035], FIG. 6A shows the layout of one metal layer. As shown in this drawing, the metal layer Mi includes a contact pad 61 and wires 62, 63 and 64 ….. ) ; generating second circuit information in which the surface pattern is changed to a line pattern based on a wire of a layer adjacent to the surface pattern (see Fig. 6A-6B, see par [0035], Referring to FIG. 6B, the metal layer Mi includes a contact pad 61 and wires 62, 63' and 64 ….. , the wire with narrow line width….. , [wherein the surface pattern 63 has been changed to pattern 63’], see par [0010], The method includes the steps of: selecting a first metal layer and a second metal layer, wherein the first metal layer is adjacent to the second metal layer ….. ) ; and executing an equivalent circuit analysis based on the second circuit information (see par [0035], the equivalent resistance of the wire 63 in FIG. 6A is larger than that of the wire 63' in FIG. 6B ….) . Regarding claim s 2 , 7, and 12 , Lin discloses: wherein the generating includes: specifying an edge in the surface pattern included in the first circuit information; and generating the second circuit information that includes information that indicates that a first line pattern that corresponds to the edge is arranged on a layer of the surface pattern, and a second line pattern is arranged at a position that faces the wire on the layer of the surface pattern (see Fig. 6A-6B, edge 61, first circuit Fig. 6A, second circuit Fig. 6B, see par [0035-0039], the wire line width can be checked according to the present invention, so as to find out the wire with narrow line width ….) . Regarding claim s 3 , 8, and 13 , Lin discloses: wherein the generating includes: determining whether a main line coupled to a power supply is coupled to the first line pattern (see par [0035], If the contact pad 61 is a power connection pad, the electric current flowing through the wire 63 will be relatively large because the wire 63 is quite close to the power connection pad 61 …. , see par [0035-0039] ) ; and when the main line is coupled to the first line pattern, generating the second circuit information that includes information that indicates that the first line pattern is arranged on the layer of the surface pattern (see par [0035], If the contact pad 61 is a power connection pad, the electric current flowing through the wire 63 will be relatively large because the wire 63 is quite close to the power connection pad 61 …. , see par [0035-0039] ) . Regarding claim s 4 , 9, and 14 ., Lin discloses: wherein the generating includes: determining whether a main line coupled to a power supply is coupled to the second line pattern (see par [0035], If the contact pad 61 is a power connection pad, the electric current flowing through the wire 63 will be relatively large because the wire 63 is quite close to the power connection pad 61 …., see par [0035-0039]) ; and when the main line is coupled to the second line pattern, generating the second circuit information that includes information that indicates that the second line pattern is arranged on the layer of the surface pattern (see par [0035], If the contact pad 61 is a power connection pad, the electric current flowing through the wire 63 will be relatively large because the wire 63 is quite close to the power connection pad 61 …., see par [0035-0039]) . Regarding claim s 5 , 10, and 15, Lin discloses: wherein the generating includes: determining whether a third line pattern not arranged on the layer of the surface pattern is included in the second line pattern (see par [0035], If the contact pad 61 is a power connection pad, the electric current flowing through the wire 63 will be relatively large because the wire 63 is quite close to the power connection pad 61 …., see par [0035-0039]) ; and when the third line pattern is included in the second line pattern, generating the second circuit information that does not include information that indicates that the third line pattern is arranged on the layer of the surface pattern (see par [0035], If the contact pad 61 is a power connection pad, the electric current flowing through the wire 63 will be relatively large because the wire 63 is quite close to the power connection pad 61 …., see par [0035-0039]) . Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to FILLIN "Examiner name" \* MERGEFORMAT BRIAN NGO whose telephone number is FILLIN "Phone number" \* MERGEFORMAT (571)270-7011 . The examiner can normally be reached FILLIN "Work Schedule?" \* MERGEFORMAT M-F 7AM-4PM . Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, FILLIN "SPE Name?" \* MERGEFORMAT Jack Chiang can be reached at FILLIN "SPE Phone?" \* MERGEFORMAT 5712727483 . The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /BRIAN NGO/ Primary Examiner, Art Unit 2851
Read full office action

Prosecution Timeline

Mar 02, 2023
Application Filed
Mar 03, 2026
Non-Final Rejection — §102 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
88%
Grant Probability
99%
With Interview (+12.2%)
2y 4m
Median Time to Grant
Low
PTA Risk
Based on 967 resolved cases by this examiner. Grant probability derived from career allow rate.

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