METADATA UPDATING

Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . DETAILED ACTION Continued Examination Under 37 CFR 1.114 A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 07/02/2026 has been entered. Claims 1, 3, 6-7, 10-12, 15-16, 19-21, 24, 27, 29 are pending in this application. This communication is responsive to the Information Disclosure Statement (IDS), filed 07/02/2026. Response to Amendment Prosecution on the merits of this application is reopened on previous allowed claims considered unpatentable for the reasons indicated below: The Notice of Allowance (NOA) is being withdrawn to permit consideration of the references cited in the IDS filed 07/02/2026, which may be pertinent to the patentability of one or more of the allowed claims. Further examination is necessary to determine the effect, if any, of the cited references on patentability. Applicant is advised that the Notice of Allowance mailed 04/15/2026 and Supplemental NOA 05/13/2026 are vacated. If the issue fee has already been paid, applicant may request a refund or request that the fee be credited to a deposit account. However, applicant may wait until the application is either found allowable or held abandoned. If allowed, upon receipt of a new Notice of Allowance, applicant may request that the previously submitted issue fee be applied. If abandoned, applicant may request refund or credit to a specified Deposit Account. The indicated allowability of claims1, 3, 6-7, 10-12, 15-16, 19-21, 24, 27, 29 is withdrawn in view of the newly discovered reference(s) to Minkin et al., and Uhrenholt et al. Rejections based on the newly cited reference(s) follow. Information Disclosure Statement Applicants’ Information Disclosure Statement, filed 07/02/2026, has been received, entered into the record, and considered. See attached form PTO-1449. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. Claims 1, 3, 6-7, 10-12, 15-16, 19-21, 24, 27, 29 are rejected under 35 U.S.C. 103 as being unpatentable over Minkin et al. (US Pub No. 20230289292), in view of Uhrenholt et al. (US Pub No. 20230195631). As per claim 1, Minkin teaches an apparatus comprising: a non-transitory external memory unit configured for storing an original descriptor tag, wherein the original descriptor tag includes information of an object which is rendered and an alternative starting location in the non-transitory external memory unit for one or more surfaces with a plurality of starting location in the non-transitory external memory (i.e. the TMAU also supports tensors that are stored in the global memory in non-interleaved mode or in interleaved mode. In interleaved mode, the TMAU may support multiple slice sizes (e.g. 16-byte slices, 32 bytes sizes, etc.), [0102]; The tensor descriptor is a data structure that is defined in global memory and which can be uniquely identified by its address in global memory … the TMAU has a dedicated descriptor cache (see FIG. 6), [0070]; incrementing the global address by the element size for the tensor, [0089]; When the innermost loop (the loop to iterate through tensor elements in dimension 0) is exited, the base global address for the next outer dimension (i.e. dimension 1) is incremented by the tensor stride defined for dimension 0 (“baseGlobalAddr[1]+=tensorDescriptor.tensorStride[0]”). This effectively advances the global address to the next slice, [0091]), wherein the object is in a graphical product ([0078]); a remap table database coupled to the non-transitory external memory unit, the remap table database to store a plurality of original base values, a plurality of updated based values and a plurality of updated miscellaneous base values (i.e. As illustrated in FIG. 5A, in an embodiment, the tensor descriptor parameters include tensor height, tensor width, tensor stride, and the element size. The tensor stride represents the tensor size (height or width) plus the padding in a particular dimension. The access descriptor parameters include the block height, block width, and the out-of-boundary value, [0078]; the TMAU maintains a descriptor cache 608 to hold recently used tensor descriptors … Each received memory access request may specify the global address of the relevant tensor descriptor, [0082]; The plurality of SM 102 a-102 n can access the global memory 116 through a plurality of TMAUs 112 a-112 n (collectively 112) … the close coupling between an SM 102 and a TMAU 112 is one-to-one, and each SM has its own dedicated TMAU 112 … Each TMAU 112 has read/write access to shared memory 110 and L1 cache 108 of the corresponding closely coupled SM 102 by issuing requests to the memory subsystem, and also to the global memory 116, [0057]); and a description loading block coupled to the non-transitory external memory, the descriptor loading block to fetch the original tag from the non-transitory external memory for storage in an internal cache memory and to compare an original base value of the original descriptor tag stored in the internal cache memory to each of the plurality of original base values in the remap table database, and to replace the original base value of the original descriptor tag with an updated base value of the plurality of updated base values in the remap table database, wherein the original base value is not equal to the updated base value (i.e. For a request for tensor data, it receives the relevant parameters from the setup block and traverses tensor space by iterating multidimensional coordinates, mapping coordinates to addresses, checking out-of-bound conditions, computing shared memory addresses, computing global memory addresses, and generating requests to the memory subsystem, [0084]; the setup block 610 obtains the corresponding descriptor from the descriptor cache 608. The setup block 610 collects and/or calculates the necessary parameters that are used for the request processing. Although many of the parameters necessary for the memory access is available in (is included in) the descriptor some other parameters are received with the memory access request … to populate parameters needed for the address calculation etc. based on the tensor descriptor. It also checks correctness of the request input parameters. As noted above, by providing for parameters that are used by multiple memory access requests to be obtained from the corresponding tensor descriptor and by providing for the memory access request from the SM to only carry parameters that are unique to the particular request, the bandwidth utilization for memory access requests from the SM to the TMAU is optimized, [0083]; A memory input/output controller (MIOC) 604 provides an interface between SM 602 and the request processing pipeline of the TMAU 612, [0080]; three-dimensional image tensors may have the tensor layout format NDHWC in which the innermost dimension C represents the number of channels, [0101]) , wherein the descriptor loading block stores an updated descriptor tag (i.e. The cache may be tagged by the global addresses of the tensor descriptors, [0082]; the setup block 610 obtains the corresponding descriptor from the descriptor cache 608. The setup block 610 collects and/or calculates the necessary parameters that are used for the request processing, [0083]; The request generator 616 is the main TMAU engine. For a request for tensor data, it receives the relevant parameters from the setup block and traverses tensor space by iterating multidimensional coordinates, mapping coordinates to addresses, checking out-of-bound conditions, computing shared memory addresses, computing global memory addresses, and generating requests to the memory subsystem. The request generator generates as many requests to the memory system to load/store the block of tensor data as necessary while adhering to the maximum size of the memory requests handled by the memory subsystem, [0084]; for each tensor, all required parameters are defined in a “tensor descriptor” that combines both tensor and access block properties. Before memory access requests to the TMAU are issued, the required parameters have to be defined in the descriptor, [0069]) including the updated base value and the updated miscellaneous base value in the internal cache memory unit within the descriptor loading block (i.e. The cache may be tagged by the global addresses of the tensor descriptors, [0082]; the setup block 610 obtains the corresponding descriptor from the descriptor cache 608. The setup block 610 collects and/or calculates the necessary parameters that are used for the request processing, [0083]; The request generator 616 is the main TMAU engine. For a request for tensor data, it receives the relevant parameters from the setup block and traverses tensor space by iterating multidimensional coordinates, mapping coordinates to addresses, checking out-of-bound conditions, computing shared memory addresses, computing global memory addresses, and generating requests to the memory subsystem. The request generator generates as many requests to the memory system to load/store the block of tensor data as necessary while adhering to the maximum size of the memory requests handled by the memory subsystem, [0084]). Minkin implicitly teaches the term “updated” (i.e. checking out-of-bound conditions, computing shared memory addresses, computing global memory addresses, and generating requests to the memory subsystem, [0084]; Although many of the parameters necessary for the memory access is available in (is included in) the descriptor some other parameters are received with the memory access request … to populate parameters needed for the address calculation etc. based on the tensor descriptor. It also checks correctness of the request input parameters … and by providing for the memory access request from the SM to only carry parameters that are unique to the particular request, the bandwidth utilization for memory access requests from the SM to the TMAU is optimized, [0083]), however, Minkin does not expressly state this term. Uhrenholt specifically teaches this term (i.e. where the first cache includes an entry (e.g. cache line) that is validly caching data, and the second cache includes a corresponding entry that is associated with same identifier (e.g. tag) and is validly caching the same data, an update (write, e.g. by the processor) to the entry in the first cache should be, and in an embodiment is, accompanied by a corresponding update to the corresponding entry in the second cache. The update to the corresponding entry in the second cache may comprise, for example, updating the data of the corresponding entry in the second cache so that both entries validly cache the same updated data, or invalidating the corresponding entry in the second cache (i.e. updating the state information of the corresponding entry in the second cache to indicate that the data is invalid) so that only the updated entry in the first cache remains valid, [0034]). It would have been obvious to one of ordinary skill of the art having the teaching of Minkin, Uhrenholt before the effective filing date of the claimed invention to modify the system of Minkin to include the limitations as taught by Uhrenholt. One of ordinary skill in the art would be motivated to make this combination in order to cache data stored in memory for a processor, in view of Uhrenholt ([0024]), as doing so would give the added benefit of updating plural related entries in the second cache in response to an update to an entry in the first cache, as taught by Uhrenholt ([0025]). As to claims 12, 21, 27, Minkin teaches: fetching an original descriptor tag from a non-transitory external (i.e. Data from the memory 1004 or other system memory may be fetched by the memory partition unit 1080 and stored in the L2 cache 1160, which is located on-chip and is shared between the various GPCs 1050, [0188]; a global memory location and a shared memory location … the fetched data can be consumed by multiple threads executing on that SM or on multiple SMs, [0042]; a descriptor load request is issued to the GCC in order to prefetch the descriptor from the global memory to cache 608, [0082]; A memory access request to the TMAU to prefetch tensor data to L2 cache may be issued with a tensor prefetch instruction in a form such as: prefetch_tensor.mode.dimensionality descriptor coordinates, [0160]); storing the original descriptor tag in an internal cache memory of a processing engine, and wherein the original descriptor tag includes information of an object which is rendered and an alternative starting location in the non-transitory external memory unit for one or more surfaces with a plurality of starting locations in the non-transitory external memory (i.e. the TMAU also supports tensors that are stored in the global memory in non-interleaved mode or in interleaved mode. In interleaved mode, the TMAU may support multiple slice sizes (e.g. 16-byte slices, 32 bytes sizes, etc.), [0102]; The tensor descriptor is a data structure that is defined in global memory and which can be uniquely identified by its address in global memory … the TMAU has a dedicated descriptor cache (see FIG. 6), [0070]; incrementing the global address by the element size for the tensor, [0089]; When the innermost loop (the loop to iterate through tensor elements in dimension 0) is exited, the base global address for the next outer dimension (i.e. dimension 1) is incremented by the tensor stride defined for dimension 0 (“baseGlobalAddr[1]+=tensorDescriptor.tensorStride[0]”). This effectively advances the global address to the next slice, [0091]), wherein the object is in a graphical product ([0078]); comparing the original descriptor tag to a plurality of descriptor update tags, wherein the original descriptor tag and the plurality of descriptor update tags are stored in the internal cache memory (i.e. As illustrated in FIG. 5A, in an embodiment, the tensor descriptor parameters include tensor height, tensor width, tensor stride, and the element size. The tensor stride represents the tensor size (height or width) plus the padding in a particular dimension. The access descriptor parameters include the block height, block width, and the out-of-boundary value, [0078]; the TMAU maintains a descriptor cache 608 to hold recently used tensor descriptors … Each received memory access request may specify the global address of the relevant tensor descriptor, [0082]; The plurality of SM 102 a-102 n can access the global memory 116 through a plurality of TMAUs 112 a-112 n (collectively 112) … the close coupling between an SM 102 and a TMAU 112 is one-to-one, and each SM has its own dedicated TMAU 112 … Each TMAU 112 has read/write access to shared memory 110 and L1 cache 108 of the corresponding closely coupled SM 102 by issuing requests to the memory subsystem, and also to the global memory 116, [0057]); and replacing an original base value of the original descriptor tag with an updated base value of a plurality of updated base values, wherein the original base value is not equal to the updated base value (i.e. For a request for tensor data, it receives the relevant parameters from the setup block and traverses tensor space by iterating multidimensional coordinates, mapping coordinates to addresses, checking out-of-bound conditions, computing shared memory addresses, computing global memory addresses, and generating requests to the memory subsystem, [0084]; the setup block 610 obtains the corresponding descriptor from the descriptor cache 608. The setup block 610 collects and/or calculates the necessary parameters that are used for the request processing. Although many of the parameters necessary for the memory access is available in (is included in) the descriptor some other parameters are received with the memory access request … to populate parameters needed for the address calculation etc. based on the tensor descriptor. It also checks correctness of the request input parameters. As noted above, by providing for parameters that are used by multiple memory access requests to be obtained from the corresponding tensor descriptor and by providing for the memory access request from the SM to only carry parameters that are unique to the particular request, the bandwidth utilization for memory access requests from the SM to the TMAU is optimized, [0083]; A memory input/output controller (MIOC) 604 provides an interface between SM 602 and the request processing pipeline of the TMAU 612, [0080]; three-dimensional image tensors may have the tensor layout format NDHWC in which the innermost dimension C represents the number of channels, [0101]); generating an updated descriptor tag when the original descriptor tag matches one or more of the plurality of descriptor update tags (i.e. The cache may be tagged by the global addresses of the tensor descriptors, [0082]; the setup block 610 obtains the corresponding descriptor from the descriptor cache 608. The setup block 610 collects and/or calculates the necessary parameters that are used for the request processing, [0083]; The request generator 616 is the main TMAU engine. For a request for tensor data, it receives the relevant parameters from the setup block and traverses tensor space by iterating multidimensional coordinates, mapping coordinates to addresses, checking out-of-bound conditions, computing shared memory addresses, computing global memory addresses, and generating requests to the memory subsystem. The request generator generates as many requests to the memory system to load/store the block of tensor data as necessary while adhering to the maximum size of the memory requests handled by the memory subsystem, [0084]; for each tensor, all required parameters are defined in a “tensor descriptor” that combines both tensor and access block properties. Before memory access requests to the TMAU are issued, the required parameters have to be defined in the descriptor, [0069]). Although Minkin implicitly teaches the term “updated” (i.e. checking out-of-bound conditions, computing shared memory addresses, computing global memory addresses, and generating requests to the memory subsystem, [0084]; Although many of the parameters necessary for the memory access is available in (is included in) the descriptor some other parameters are received with the memory access request … to populate parameters needed for the address calculation etc. based on the tensor descriptor. It also checks correctness of the request input parameters … and by providing for the memory access request from the SM to only carry parameters that are unique to the particular request, the bandwidth utilization for memory access requests from the SM to the TMAU is optimized, [0083]), Minkin does not clearly state this term. Uhrenholt expressly teaches this term (i.e. where the first cache includes an entry (e.g. cache line) that is validly caching data, and the second cache includes a corresponding entry that is associated with same identifier (e.g. tag) and is validly caching the same data, an update (write, e.g. by the processor) to the entry in the first cache should be, and in an embodiment is, accompanied by a corresponding update to the corresponding entry in the second cache. The update to the corresponding entry in the second cache may comprise, for example, updating the data of the corresponding entry in the second cache so that both entries validly cache the same updated data, or invalidating the corresponding entry in the second cache (i.e. updating the state information of the corresponding entry in the second cache to indicate that the data is invalid) so that only the updated entry in the first cache remains valid, [0034]). It would have been obvious to one of ordinary skill of the art having the teaching of Minkin, Uhrenholt before the effective filing date of the claimed invention to modify the system of Minkin to include the limitations as taught by Uhrenholt. One of ordinary skill in the art would be motivated to make this combination in order to cache data stored in memory for a processor, in view of Uhrenholt ([0024]), as doing so would give the added benefit of updating plural related entries in the second cache in response to an update to an entry in the first cache, as taught by Uhrenholt ([0025]). As per claim 3, Minkin teaches the apparatus of claim 1, wherein the descriptor loading block is further to replace an original miscellaneous base value of the original descriptor tag with an updated miscellaneous base value of the original tag with an updated miscellaneous base value of the plurality of updated miscellaneous base values (i.e. The cache may be tagged by the global addresses of the tensor descriptors, [0082]; the setup block 610 obtains the corresponding descriptor from the descriptor cache 608. The setup block 610 collects and/or calculates the necessary parameters that are used for the request processing, [0083]; The request generator 616 is the main TMAU engine. For a request for tensor data, it receives the relevant parameters from the setup block and traverses tensor space by iterating multidimensional coordinates, mapping coordinates to addresses, checking out-of-bound conditions, computing shared memory addresses, computing global memory addresses, and generating requests to the memory subsystem. The request generator generates as many requests to the memory system to load/store the block of tensor data as necessary while adhering to the maximum size of the memory requests handled by the memory subsystem, [0084]). As per claim 6, Minkin teaches the apparatus of claim 5, further comprising a first auxiliary processing engine to utilize the updated descriptor tag (i.e. for each tensor, all required parameters are defined in a “tensor descriptor” that combines both tensor and access block properties. Before memory access requests to the TMAU are issued, the required parameters have to be defined in the descriptor, [0069]). As per claim 7, Minkin teaches the apparatus of claim 6, further comprising a second auxiliary processing engine to utilize the updated descriptor tag (i.e. The request for data is transmitted via the general network interface controller (GNIC) interface 614 to the memory subsystem, and each request is kept track of in the response completion circuit 618. The tracking enables the asynchronous processing with the SM. Responses to the requests are received at a GNIC response processor 620, which communicates with the request tracking circuitry 618 to keep track of the completion status of each request transmitted from the request generator 716, [0085]; FIG. 10 illustrates a parallel processing unit (PPU) 1000, in accordance with an embodiment. In an embodiment, the PPU 1000 is a multi-threaded processor that is implemented on one or more integrated circuit devices. The PPU 1000 is a latency hiding architecture designed to process many threads in parallel. A thread (e.g., a thread of execution) is an instantiation of a set of instructions configured to be executed by the PPU 1000. In an embodiment, the PPU 1000 is a graphics processing unit (GPU) configured to implement a graphics rendering pipeline for processing three-dimensional (3D) graphics data in order to generate two-dimensional (2D) image data for display on a display device such as a liquid crystal display (LCD) device. In other embodiments, the PPU 1000 may be utilized for performing general-purpose computations. In some other embodiments, PPU 100 configured to implement large neural networks in deep learning applications or other high performance computing applications, [0064]). As per claim 10, Minkin teaches the apparatus of claim 1, wherein the remap table database is part of the descriptor loading block (i.e. The plurality of SM 102 a-102 n can access the global memory 116 through a plurality of TMAUs 112 a-112 n (collectively 112). Each SM 102 is closely coupled to a respective TMAU 112 which is configured to access global memory 116 via the global memory interface 114. In some embodiments, the close coupling between an SM 102 and a TMAU 112 is one-to-one, and each SM has its own dedicated TMAU 112, but embodiments are not limited thereto. Each TMAU 112 has read/write access to shared memory 110 and L1 cache 108 of the corresponding closely coupled SM 102 by issuing requests to the memory subsystem, and also to the global memory 116, [0057]). As per claim 11, Minkin teaches the apparatus of claim 10, wherein the internal cache memory is dedicated to the descriptor loading block (i.e. The cache may be tagged by the global addresses of the tensor descriptors, [0082]; the setup block 610 obtains the corresponding descriptor from the descriptor cache 608. The setup block 610 collects and/or calculates the necessary parameters that are used for the request processing, [0083]; The request generator 616 is the main TMAU engine. For a request for tensor data, it receives the relevant parameters from the setup block and traverses tensor space by iterating multidimensional coordinates, mapping coordinates to addresses, checking out-of-bound conditions, computing shared memory addresses, computing global memory addresses, and generating requests to the memory subsystem. The request generator generates as many requests to the memory system to load/store the block of tensor data as necessary while adhering to the maximum size of the memory requests handled by the memory subsystem, [0084]; for each tensor, all required parameters are defined in a “tensor descriptor” that combines both tensor and access block properties. Before memory access requests to the TMAU are issued, the required parameters have to be defined in the descriptor, [0069]). As to claims 15, 24, 29, Minkin teaches replacing an original miscellaneous base value of the original descriptor tag with an updated miscellaneous base value of a plurality of updated miscellaneous base values (i.e. The cache may be tagged by the global addresses of the tensor descriptors, [0082]; the setup block 610 obtains the corresponding descriptor from the descriptor cache 608. The setup block 610 collects and/or calculates the necessary parameters that are used for the request processing, [0083]; The request generator 616 is the main TMAU engine. For a request for tensor data, it receives the relevant parameters from the setup block and traverses tensor space by iterating multidimensional coordinates, mapping coordinates to addresses, checking out-of-bound conditions, computing shared memory addresses, computing global memory addresses, and generating requests to the memory subsystem. The request generator generates as many requests to the memory system to load/store the block of tensor data as necessary while adhering to the maximum size of the memory requests handled by the memory subsystem, [0084]; for each tensor, all required parameters are defined in a “tensor descriptor” that combines both tensor and access block properties. Before memory access requests to the TMAU are issued, the required parameters have to be defined in the descriptor, [0069]). As per claim 16, Minkin teaches the method of claim 15, wherein the plurality of updated base values and the plurality of updated miscellaneous base values are stored in a remap table database within the processing engine (i.e. The plurality of SM 102 a-102 n can access the global memory 116 through a plurality of TMAUs 112 a-112 n (collectively 112). Each SM 102 is closely coupled to a respective TMAU 112 which is configured to access global memory 116 via the global memory interface 114. In some embodiments, the close coupling between an SM 102 and a TMAU 112 is one-to-one, and each SM has its own dedicated TMAU 112, but embodiments are not limited thereto. Each TMAU 112 has read/write access to shared memory 110 and L1 cache 108 of the corresponding closely coupled SM 102 by issuing requests to the memory subsystem, and also to the global memory 116, [0057]). As per claim 19, Minkin teaches the method of claim 12, wherein the plurality of descriptor update tags is stored in a remap table within the processing engine (i.e. The plurality of SM 102 a-102 n can access the global memory 116 through a plurality of TMAUs 112 a-112 n (collectively 112). Each SM 102 is closely coupled to a respective TMAU 112 which is configured to access global memory 116 via the global memory interface 114. In some embodiments, the close coupling between an SM 102 and a TMAU 112 is one-to-one, and each SM has its own dedicated TMAU 112, but embodiments are not limited thereto. Each TMAU 112 has read/write access to shared memory 110 and L1 cache 108 of the corresponding closely coupled SM 102 by issuing requests to the memory subsystem, and also to the global memory 116, [0057]). As per claim 20, Minkin teaches the method of claim 12, wherein the internal cache memory is dedicated to the processing engine (i.e. The cache may be tagged by the global addresses of the tensor descriptors, [0082]; the setup block 610 obtains the corresponding descriptor from the descriptor cache 608. The setup block 610 collects and/or calculates the necessary parameters that are used for the request processing, [0083]; The request generator 616 is the main TMAU engine. For a request for tensor data, it receives the relevant parameters from the setup block and traverses tensor space by iterating multidimensional coordinates, mapping coordinates to addresses, checking out-of-bound conditions, computing shared memory addresses, computing global memory addresses, and generating requests to the memory subsystem. The request generator generates as many requests to the memory system to load/store the block of tensor data as necessary while adhering to the maximum size of the memory requests handled by the memory subsystem, [0084]; for each tensor, all required parameters are defined in a “tensor descriptor” that combines both tensor and access block properties. Before memory access requests to the TMAU are issued, the required parameters have to be defined in the descriptor, [0069]). Response to Arguments Applicant's Information Disclosure Statement filed on 07/02/2026 have been fully considered. References Minkin et al. (US Pub No. 2023/0289292) in view of Uhrenholt et al. (US Pub No. 20230195631) are pertinent to the patentability of claims 1, 3, 6-7, 10-12, 15-16, 19-21, 24, 27, 29; thus, the Notice of Allowance is withdrawn. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Any inquiry concerning this communication or earlier communications from the examiner should be directed to MIRANDA LE whose telephone number is (571)272-4112. The examiner can normally be reached M-F 7AM-5PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kavita Stanley can be reached on 571-272-8352. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /MIRANDA LE/ Primary Examiner, Art Unit 2153