Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This communication is responsive to Amendment, filed 06/25/2025.
Claims 1-7, 10-16, 19-24, 27-29 are pending in this application. Claims 8, 9, 17, 18, 25, 26, 30 were previously cancelled. This action is made Final.
Information Disclosure Statement
Applicants’ Information Disclosure Statement, filed 06/25/2025, has been received, entered into the record, and considered. See attached form PTO-1449.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claims 1-7, 10-16, 19-24, 27-29 are rejected under 35 U.S.C. 103 as being unpatentable over Fielding et al. (US Pub No. 2019/0096027), in view of Guirado et al. (US Pub No. 2022/0075730).
As per claim 1, Fielding teaches an apparatus comprising:
a non-transitory external memory unit configured for storing an original descriptor tag, wherein the original descriptor tag includes information of an object which is rendered a value related to a graphical surface location (i.e. the first cache 22 (the texture data cache) of the texture cache system 21 stores the texture data as a copy of the bits of the texture data as stored in the memory system 20, and each cache line of the first cache 22 is tagged with the memory address of the first byte in the cache line. Thus, each cache line of the first cache 22 will store a cache-line's amount of texture data from contiguous addresses in the main memory of the memory system 20, [0251]; Each cache line 4 in the second cache 23 is provided with an associated “tag”, to identify the data (the texels) that it is storing, [0270]; each cache line in the second cache 23 is tagged the following fields; a surface pointer indicating which surface of the texture the data in the cache line is from ... x, y and z indices for the cache line, [0271-0275]; The texture data can be stored in the first cache (the cache that interfaces with the (main) memory) in any suitable and desired manner and format, [0058]; By arranging and storing the texture data in the second cache in this way, this can facilitate later processing of the texture data for a particular area or sample position of the texture as all of the texture data for an area of the texture is stored together in a cache line, [0093]);
a remap table database coupled to the non-transitory external memory unit, the remap table database configured to store a plurality of original base values, a plurality of updated base values and a plurality of updated miscellaneous base values (i.e. each cache line of texture data in the first cache is identified (is tagged) using the memory address of at least some of the texture data (e.g. of a given byte of the texture data) that is stored in the cache line, [0063]; the texture data that is stored in the second cache is identified (tagged) using an identifier that is indicative of a position in the graphics texture (that the cached texture data comes from) (in contrast to, e.g., using a memory address where the data is stored), [0096]);
a descriptor loading block coupled to the non-transitory external memory, the descriptor loading block to fetch the original descriptor tag from the non-transitory external memory for storage in an internal cache memory and to compare an original base value of the original descriptor stored in the internal cache memory to each of the plurality of original base values in the remap table database, and to replace the original base value of the original descriptor tag with an updated base value of the plurality of updated base values in the remap table database, wherein the original base value is not equal to the updated base value (i.e. One such example would be in the case of YUV texture data, where the YUV texture data is stored in separate planes (in a multi-plane format) in the memory system 20. In this case, the different data channels of the YUV texture data may be loaded separately into the first cache 22, and stored in respective different cache lines in that cache. The data processing unit 24 could then operate to read respective Y, U and V data values for a given texel of the YUV texture from the different cache lines where those values are stored in the first cache 22, and then store those respective Y, U and V data values for the texel in a respective data word for that texel in a given (the same) cache line in the second (texel) cache 23. In this way, the texture data that is stored in separate planes in the memory system 20 will be grouped by the data processing unit 24 into respective texels in the second cache 23 (as discussed above), [0290]; As shown in FIG. 2, as well as including the first (texture data) cache 22 and the second (texel) cache 23, the cache system 21 of the present embodiment further comprises a data processing unit 24 that is intermediate the first and second caches and that is, as shown in FIG. 2, operable to be able to read data from the first (texture data cache) 22, process that data, and then store that data in the second (texel) cache 23 for use by the texture mapper 14, [0282]; FIG. 9 shows the first, texture data cache 22 having an exemplary set of cache lines 90 each tagged with a respective memory address 91 identifying the location in memory where the data in the cache line is stored. FIG. 9 also shows the second, texel cache 23, again as including a number of cache lines 92, and each tagged with a respective x, y, z position 93 to identify the data that is stored in the cache line, [0286]; the plurality of groups of texture data (texels) stored in a cache line in the second cache comprise a set of contiguous texels of the texture (i.e. represent a set of adjacent (or successive) texture data element positions of the texture), [0086]).
Fielding implicitly teaches the term "descriptor" (descriptor tag) (i.e. each cache line of texture data in the first cache is identified (is tagged) using the memory address of at least some of the texture data (e.g. of a given byte of the texture data) that is stored in the cache line, [0063]; the texture data that is stored in the second cache is identified (tagged) using an identifier that is indicative of a position in the graphics texture (that the cached texture data comes from) (in contrast to, e.g., using a memory address where the data is stored), [0096]).
Fielding does not clearly state this term.
Guirado teaches this term (i.e. The identifiers could also comprise a combination (e.g. a concatenation) of more than one parameter (field) if desired. For example, in the case of a texture cache for a graphics processor, the identifiers could comprise a concatenation of a descriptor address and texture coordinates and/or other texture parameters, such as the texture ID, surface ID and texel format together with the texture coordinates, [0057]; Other forms of identifier would, of course, be possible, [0058]; As well as the identifiers and the data itself, each cache line in the cache (each cache line tag) may also have other information stored for it and associated with it as desired, [0059]); Thus, for a portion of data in the group other than the first portion of data whose first part of the identifier matches the first part of the identifier for the first portion of data, but whose second part of the identifier does not match any of the cache lines in the cache, a cache line is allocated for the (other) portion of data, and the cache line identifier (tag) is updated by updating the first part of the identifier for the cache line to match the corresponding first part of the identifier for the first one of the portions of data in the group; and updating the second part of the identifier for the cache line to match the corresponding second part of the identifier for the (other) portion of data that the cache line has been allocated to, [0165]).
It would have been obvious to one of ordinary skill of the art having the teaching of Fielding, Guirado before the effective filing date of the claimed invention to modify the system of Fielding to include the limitations as taught by Guirado. One of ordinary skill in the art would be motivated to make this combination in order to determine whether there is a cache line in the cache for the portion of data in question by comparing the identifier for the portion of data to the identifiers for the cache lines in the cache in view of Guirado ([0072]), as doing so would give the added benefit of updating of the identifiers (tags) for the cache lines in the cache can be simplified, e.g. by reducing the number of multiplex operations that need to be performed, as taught by Guirado ([0166]).
As to claims 12, 21, 27, Fielding teaches a method for updating metadata, the method comprising:
fetching an original descriptor tag from a non-transitory external (i.e. The technology described herein may comprise performing one or more memory requests to fetch required texture data from memory into the first cache (a cache line). The number of memory requests may depend on how the texture data is stored in the memory, and, for example, the number of (different) locations at which it is stored. The number of memory requests may also (or alternatively) depend on the arrangement of groups of texture data to be stored in the first cache or cache line, [0173]; The identifier can be provided in any suitable and desired way. In an embodiment, the identifier is provided as a tag for the cache line in question (in which the texture data is stored), [0061]);
storing the original descriptor tag in an internal cache memory of a processing engine, and wherein the original descriptor tag includes information of an object which is rendered and a value related to a graphical surface location (i.e. the first cache 22 (the texture data cache) of the texture cache system 21 stores the texture data as a copy of the bits of the texture data as stored in the memory system 20, and each cache line of the first cache 22 is tagged with the memory address of the first byte in the cache line. Thus, each cache line of the first cache 22 will store a cache-line's amount of texture data from contiguous addresses in the main memory of the memory system 20, [0251]; Each cache line 4 in the second cache 23 is provided with an associated “tag”, to identify the data (the texels) that it is storing, [0270]; each cache line in the second cache 23 is tagged the following fields; a surface pointer indicating which surface of the texture the data in the cache line is from ... x, y and z indices for the cache line, [0271-0275]; The texture data can be stored in the first cache (the cache that interfaces with the (main) memory) in any suitable and desired manner and format, [0058]; By arranging and storing the texture data in the second cache in this way, this can facilitate later processing of the texture data for a particular area or sample position of the texture as all of the texture data for an area of the texture is stored together in a cache line, [0093]);
comparing the original descriptor tag to a plurality of descriptor update tags, wherein the original descriptor tag and the plurality of descriptor update tags are stored in the internal cache memory (i.e. The data processing unit 24 could then operate to read respective Y, U and V data values for a given texel of the YUV texture from the different cache lines where those values are stored in the first cache 22, [0290]; each cache line of texture data in the first cache is identified (is tagged) using the memory address of at least some of the texture data (e.g. of a given byte of the texture data) that is stored in the cache line, [0063]; the texture data that is stored in the second cache is identified (tagged) using an identifier that is indicative of a position in the graphics texture (that the cached texture data comes from) (in contrast to, e.g., using a memory address where the data is stored), [0096]);
replacing an original base value of the original descriptor tag with an updated base value of a plurality of updated base values, wherein the original base value is not equal to the updated base value (i.e. One such example would be in the case of YUV texture data, where the YUV texture data is stored in separate planes (in a multi-plane format) in the memory system 20. In this case, the different data channels of the YUV texture data may be loaded separately into the first cache 22, and stored in respective different cache lines in that cache. The data processing unit 24 could then operate to read respective Y, U and V data values for a given texel of the YUV texture from the different cache lines where those values are stored in the first cache 22, and then store those respective Y, U and V data values for the texel in a respective data word for that texel in a given (the same) cache line in the second (texel) cache 23. In this way, the texture data that is stored in separate planes in the memory system 20 will be grouped by the data processing unit 24 into respective texels in the second cache 23 (as discussed above), [0290]; As shown in FIG. 2, as well as including the first (texture data) cache 22 and the second (texel) cache 23, the cache system 21 of the present embodiment further comprises a data processing unit 24 that is intermediate the first and second caches and that is, as shown in FIG. 2, operable to be able to read data from the first (texture data cache) 22, process that data, and then store that data in the second (texel) cache 23 for use by the texture mapper 14, [0282]; FIG. 9 shows the first, texture data cache 22 having an exemplary set of cache lines 90 each tagged with a respective memory address 91 identifying the location in memory where the data in the cache line is stored. FIG. 9 also shows the second, texel cache 23, again as including a number of cache lines 92, and each tagged with a respective x, y, z position 93 to identify the data that is stored in the cache line, [0286]; the plurality of groups of texture data (texels) stored in a cache line in the second cache comprise a set of contiguous texels of the texture (i.e. represent a set of adjacent (or successive) texture data element positions of the texture), [0086]).
Fielding implicitly teaches the term "descriptor" (descriptor tag) (i.e. each cache line of texture data in the first cache is identified (is tagged) using the memory address of at least some of the texture data (e.g. of a given byte of the texture data) that is stored in the cache line, [0063]; the texture data that is stored in the second cache is identified (tagged) using an identifier that is indicative of a position in the graphics texture (that the cached texture data comes from) (in contrast to, e.g.,
using a memory address where the data is stored), [0096]).
Fielding does not clearly state this term.
Guirado teaches this term (i.e. The identifiers could also comprise a combination (e.g. a concatenation) of more than one parameter (field) if desired. For example, in the case of a texture cache for a graphics processor, the identifiers could comprise a concatenation of a descriptor address and texture coordinates and/or other texture parameters, such as the texture ID, surface ID and texel format together with the texture coordinates, [0057]; Other forms of identifier would, of course, be possible, [0058]; As well as the identifiers and the data itself, each cache line in the cache (each cache line tag) may also have other information stored for it and associated with it as desired, [0059]); Thus, for a portion of data in the group other than the first portion of data whose first part of the identifier matches the first part of the identifier for the first portion of data, but whose second part of the identifier does not match any of the cache lines in the cache, a cache line is allocated for the (other) portion of data, and the cache line identifier (tag) is updated by updating the first part of the identifier for the cache line to match the corresponding first part of the identifier for the first one of the portions of data in the group; and updating the second part of the identifier for the cache line to match the corresponding second part of the identifier for the (other) portion of data that the cache line has been allocated to, [0165]).
It would have been obvious to one of ordinary skill of the art having the teaching of Fielding, Guirado before the effective filing date of the claimed invention to modify the system of Fielding to include the limitations as taught by Guirado. One of ordinary skill in the art would be motivated to make this combination in order to determine whether there is a cache line in the cache for the portion of data in question by comparing the identifier for the portion of data to the identifiers for the cache lines in the cache in view of Guirado ([0072]), as doing so would give the added benefit of updating of the identifiers (tags) for the cache lines in the cache can be simplified, e.g. by reducing the number of multiplex operations that need to be performed as taught by Guirado ([0166]).
As per claim 2, Guirado teaches the apparatus of claim 1, wherein the object is in a graphical product (i.e. a cache system arranged between the memory system and the graphics processing unit and operable to transfer texture data stored in the memory system to the graphics processing unit for use by the graphics processing unit when generating a render output, [0027]).
As per claim 3, Guirado teaches the apparatus of claim 1, wherein the descriptor loading block is further to replace an original miscellaneous base value of the original descriptor tag with an updated miscellaneous base value of the original tag with an updated miscellaneous base value of the plurality of updated miscellaneous base values (i.e. Thus, for a portion of data in the group other than the first portion of data whose first part of the identifier matches the first part of the identifier for the first portion of data, but whose second part of the identifier does not match any of the cache lines in the cache, a cache line is allocated for the (other) portion of data, and the cache line identifier (tag) is updated by updating the first part of the identifier for the cache line to match the corresponding first part of the identifier for the first one of the portions of data in the group; and updating the second part of the identifier for the cache line to match the corresponding second part of the identifier for the (other) portion of data that the cache line has been allocated to, [0165]).
As per claim 4, Guirado teaches the apparatus of claim 3, wherein the descriptor loading block is to store an updated descriptor tag in the internal cache memory unit with the descriptor loading block (i.e. In another embodiment, the identifiers comprise all or part of memory addresses for the data in question (i.e. all or part of a memory address where data that is stored in the cache line is stored), [0055]; In another embodiment, the identifiers comprise all or part of “positions” for the data in question, e.g., and in an embodiment within a data array that the data in question belongs to. For example, and in an embodiment, in the case where the cache stores texture data for use by a graphics processor, the identifier for a cache line may, and in an embodiment does, comprise, at least in part, the texture coordinates of a texel or texels that the data in the cache line corresponds to, [0056]).
As per claim 5, Guirado teaches the apparatus of claim 4, wherein the updated descriptor tag includes the updated based value and the updated miscellaneous base value (i.e. Thus, for a portion of data in the group other than the first portion of data whose first part of the identifier matches the first part of the identifier for the first portion of data, but whose second part of the identifier does not match any of the cache lines in the cache, a cache line is allocated for the (other) portion of data, and the cache line identifier (tag) is updated by updating the first part of the identifier for the cache line to match the corresponding first part of the identifier for the first one of the portions of data in the group; and updating the second part of the identifier for the cache line to match the corresponding second part of the identifier for the (other) portion of data that the cache line has been allocated to, [0165]).
As per claim 6, Guirado teaches the apparatus of claim 5, further comprising a first auxiliary processing engine to utilize the updated descriptor tag (i.e. To facilitate this, the cache control circuit in an embodiment comprises an appropriate cache line identifier (tag) update circuit or circuits that is operable to and configured to (and can be activated to) update the identifiers (tags) for the cache lines in the cache, [0159; there is a (first) cache line identifier (tag) update circuit, [0160]).
As per claim 7, Guirado teaches the apparatus of claim 6, further comprising a second auxiliary processing engine to utilize the updated descriptor tag (i.e. a (second) cache line identifier (tag) update circuit that is configured to be able to, for each cache line in the cache, update the remaining part of the identifier (tag) for the cache line with the remaining part of the identifier for any one of the portions of data in a group of plural portions of data (and that can be controlled to apply an update to any selected cache line in the cache in a given cycle), [0161]).
As per claim 10, Fielding teaches the apparatus of claim 1, wherein the remap table database is part of the descriptor loading block (i.e. The texture data can be stored in the first cache (the cache that interfaces with the (main) memory) in any suitable and desired manner and format, [0058]; By arranging and storing the texture data in the second cache in this way, this can facilitate later processing of the texture data for a particular area or sample position of the texture as all of the texture data for an area of the texture is stored together in a cache line, [0093]).
As per claim 11, Fielding teaches the apparatus of claim 10, wherein the internal cache memory is dedicated to the descriptor loading block (i.e. The texture data can be stored in the first cache (the cache that interfaces with the (main) memory) in any suitable and desired manner and format, [0058]; By arranging and storing the texture data in the second cache in this way, this can facilitate later processing of the texture data for a particular area or sample position of the texture as all of the texture data for an area of the texture is stored together in a cache line, [0093]).
As to claims 13, 22, 28, Fielding teaches generating an updated descriptor tag if the original descriptor tag matches one or more of the plurality of descriptor update tags (i.e. each cache line of texture data in the first cache is identified (is tagged) using the memory address of at least some of the texture data (e.g. of a given byte of the texture data) that is stored in the cache line, [0063]; the texture data that is stored in the second cache is identified (tagged) using an identifier that is indicative of a position in the graphics texture (that the cached texture data comes from) (in contrast to, e.g., using a memory address where the data is stored), [0096]).
As to claims 14, 23, Fielding teaches the object is in a graphical product (i.e. a cache system arranged between the memory system and the graphics processing unit and operable to transfer texture data stored in the memory system to the graphics processing unit for use by the graphics processing unit when generating a render output, [0027]).
As to claims 15, 24, 29, Fielding teaches replacing an original miscellaneous base value of the original descriptor tag with an updated miscellaneous base value of a plurality of updated miscellaneous base values (i.e. The second cache of the cache system of the technology described herein (i.e. that interfaces with, and provides texture data to, the graphics processing unit for use when generating a render output) can interface with the graphics processing unit in any suitable and desired manner, [0065]; Thus, in an embodiment, the graphics processing unit comprises a texture mapper (texture mapping circuitry) that is operable to use data stored in (and receive data from) the second cache, and to use that data when performing and to perform a texturing operation, [0067]).
As per claim 16, Fielding teaches the method of claim 15, wherein the plurality of updated base values and the plurality of updated miscellaneous base values are stored in a remap table database within the processing engine (i.e. In an embodiment, this second cache interfaces with, and connects to, the texture mapper of the graphics processing pipeline of the graphics processing unit (which texture mapper is operable to receive (load) texture data from the second cache of the cache system
and use that texture data to perform texturing operations), [0066]).
As per claim 19, Fielding teaches the method of claim 12, wherein the plurality of descriptor update tags is stored in a remap table within the processing engine (i.e. The second cache of the cache system of the technology described herein (i.e. that interfaces with, and provides texture data to, the graphics processing unit for use when generating a render output) can interface with the graphics processing unit in any suitable and desired manner, [0065]; Thus, in an embodiment, the graphics processing unit comprises a texture mapper (texture mapping circuitry) that is operable to use data stored in (and receive data from) the second cache, and to use that data when performing and to perform a texturing operation, [0067]).
As per claim 20, Fielding teaches the method of claim 12, wherein the internal cache memory is dedicated to the processing engine (i.e. The texture data can be stored in the first cache (the cache that interfaces with the (main) memory) in any suitable and desired manner and format, [0058]; By arranging and storing the texture data in the second cache in this way, this can facilitate later processing of the texture data for a particular area or sample position of the texture as all of the texture data for an area of the texture is stored together in a cache line, [0093]).
Response to Arguments
Applicant's arguments with respect to claims 1, 3-8, 10-15, 17, 18 and 20 have been considered but are moot in view of the new ground(s) of rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MIRANDA LE whose telephone number is (571)272-4112. The examiner can normally be reached M-F 7AM-5PM.
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/MIRANDA LE/ Primary Examiner, Art Unit 2153
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