Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. autonum This application has been examined. Claims 1-20 are pending. autonum The Group and/or Art Unit location of your application in the PTO has changed. To aid in correlating any papers for this application, all further correspondence regarding this application should be directed to Group Art Unit 2175. Specification autonum The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. Claim Rejections - 35 USC § 112 The following is a quotation of the second paragraph of 35 U.S.C. 112: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claim 1 recites the limitation " the first set of phase circuits FILLIN "Enter appropriate information" \* MERGEFORMAT " on page 1 . There is insufficient antecedent basis for this limitation in the claim. Claim 1 recites the limitation " the second set of phase circuits FILLIN "Enter appropriate information" \* MERGEFORMAT " on page 1 . There is insufficient antecedent basis for this limitation in the claim. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. autonum Claims 1- 3, 5-6, 8- 9, 13, 15, 19 are rejected under 35 U.S.C. § 102(a)( 1 ) as being anticipated by Adell et al. (US Pub No. 2018/0048232 ). In regard to claim s 1 , 9, 15, Adelle et al. disclose a method, a t least one machine-readable medium comprising a plurality of instructions (see the circuits must have firmware in order to operate) which, when executed on a computing device cause the computing device to : a n apparatus comprising: a first set of power converter phase circuits, the first set of phase circuits including a first reference phase circuit (item 306s of figure 3A) and other first set phase circuits (item 304s of figure 3A) ; and a second set of power converter phase circuits, the second set of phase circuits including a second reference phase circuit and other second set phase circuits (as shown in Fig. 3A , which is reproduced below for ease of reference and convenience, Adell discloses converter 300 comprises a separate comparison (CCG) circuits 306a, 306b, 306c connected to each one of the slave phase circuits 304a, 304b, 304c). Each of the CCG circuits 306a, 306b, 306c . See ¶ 70-73); wherein the first reference phase circuit is electrically coupled to the second reference phase circuit for calibration; wherein the other first set phase circuits are electrically coupled to the first reference phase circuit for calibration and the other second set phase circuits are electrically coupled to the second reference phase circuit for calibration (in Adell, the duty cycle calibration block (DCB) circuits 308a, 308b, and 308c (a separate DCB circuit connected to each one of the CCG circuits 306a, 306b, 306c and each one of the slave circuits 304a, 304b, 304c) . See ¶ 75-78). In regard to claim 2 , Adelle et al. disclose wherein a current level output of the first reference phase circuit is electrically coupled to a calibration input of the second reference phase circuit and a current level output of the second reference phase circuit is electrically coupled to a calibration input of the first reference phase circuit (in Adell, the duty cycle calibration block (DCB) circuits 308a, 308b, and 308c (a separate DCB circuit connected to each one of the CCG circuits 306a, 306b, 306c and each one of the slave circuits 304a, 304b, 304c) . See ¶ 75-78). In regard to claim 3 , Adelle et al. disclose wherein an average current of a current level output of the first reference phase circuit and a current level output of the second reference phase circuit is electrically coupled to a calibration input of the first reference phase circuit and a calibration input of the second reference phase circuit (in Adell, the duty cycle calibration block (DCB) circuits 308a, 308b, and 308c (a separate DCB circuit connected to each one of the CCG circuits 306a, 306b, 306c and each one of the slave circuits 304a, 304b, 304c) . See ¶ 75-78). In regard to claims 5 , 13, 1 9 , Adelle et al. disclose wherein a current level output of the first reference phase circuit is electrically coupled to calibration inputs of the other first set phase circuits and a current level output of the second reference phase circuit is electrically coupled to calibration inputs of the other second set phase circuits (in Adell, the duty cycle calibration block (DCB) circuits 308a, 308b, and 308c (a separate DCB circuit connected to each one of the CCG circuits 306a, 306b, 306c and each one of the slave circuits 304a, 304b, 304c) . See ¶ 75-78). In regard to claim 6 , Adelle et al. disclose wherein a current level output of one phase circuit of the other first set phase circuits is electrically coupled to a calibration input of another phase circuit of the other first set phase circuits (in Adell, the duty cycle calibration block (DCB) circuits 308a, 308b, and 308c (a separate DCB circuit connected to each one of the CCG circuits 306a, 306b, 306c and each one of the slave circuits 304a, 304b, 304c) . See ¶ 75-78). In regard to claim 8 , Adelle et al. disclose further : multiple processing engines; wherein the first set of power converter phase circuits and the second set of power converter phase circuits to supply current to the multiple processing engines (in Adell, a data processing system 2200 comprising the DC/DC converter 100, 300, according to embodiments of the invention, connected 2202 to an application (e.g., computing system including processor(s) 2204) and converting (step up or step down) one or more DC voltages received from a voltage supply 2206 (e.g., power supply) to one or more voltages used by the processor(s) 2204. In one or more embodiments, the DC/DC converter is interfaced to the voltage supply 2206 using an interface such as a serial peripheral interface SPI (however, other bus architectures can be used). In one or more embodiments, an operating system runs on processor(s) 2204 and is used to coordinate and provide control of various components within data processing system 300. See ¶ 145-146). Claim Rejections - 35 USC § 103 autonum The following is a quotation of 35 U.S.C. § 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art t which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. autonum Claim 7 is rejected under AIA 35 U.S.C. § 103 as being unpatentable over Adell et al. In order to expedite and avoid piecemeal prosecution, the following rejection is made to the extent that the claims are understood, by considering those elements which are understood and interpreting their function in a manner which is consistent with the recited goals of the claims, and then applying the best available art. The examiner relies on the entire teachings of Adell reference; the applicant should carefully consider the entire teachings of the above-mentioned references to better understand the examiner’s position. In regard to claim 7 , even though Adell does not disclose wherein the first reference phase circuit and the second reference phase circuit are located centrally on a printed circuit board, the first reference phase circuit surrounded by the other first set phase circuits and the second reference phase circuit surrounded by the other second set phase circuits. However it is merely one of several straightforward possibilities from which the skilled person in the art would position the circuits within the printed circuit board (PCB) in increase the limited PCB area for other components, without the exercise of inventive skill, in order to solve the problem posed. Examiner's note : Examiner has cited particular columns and line numbers in the references applied to the claims above for the convenience of the Applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the Applicant in preparing responses, to fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passages as taught by the prior art or disclosed by the Examiner. Allowable Subject Matter autonum Claim s 4, 10-12, 14, 16-18, 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. autonum The following is an Examiner's statement of reasons for the indication of allowable subject matter: Claim s 4, 10-11, 14 , 16-17, 20 are allowable over the prior art of record because the prior arts, cited in its entirety, or in combination, do not teach wherein the average current of the current level output of the first reference phase circuit and the current level output of the second reference phase circuit is electrically coupled to calibration inputs of the other first set phase circuits and calibration inputs of the other second set phase circuits (claim 4) ; wherein the calibrating the current level output of the first reference phase circuit to the current level output of the second reference phase circuit includes using a closed loop daisy chain, wherein the current level output of the first reference phase circuit is received by a calibration input of the second reference phase circuit and the current level output of the second reference phase circuit is received by a calibration input of the first reference phase circuit (claim s 10 , 16 ); wherein the calibrating the current level output of the first reference phase circuit to the current level output of the second reference phase circuit includes sending an average current of the current level output of the first reference phase circuit and the current level output of the second reference phase circuit to a calibration input of the first reference phase circuit and to a calibration input of the second reference phase circuit (claim s 11 , 17 ); wherein the calibrating the current level outputs of the other first set phase circuits to the current level output of the first reference phase circuit includes using an open loop daisy chain of the current level outputs of the other first set phases (claim s 14 , 20 ). Conclusion autonum C laims 1-3, 5-9, 13, 15, 19 are rejected. Claim s 4, 10-12, 14, 16-18, 20 are objected autonum The prior arts made of record and not relied upon are considered pertinent to applicant's disclosure. Shenoy et al. (US Pub No. 2015/0207400 ) disclose a circuit has a control circuit (16) for providing a set of control signals or values (14-1-14-4) to individually operate DC-DC converter phases (4-1-4-4) to provide an output according to a phase sequence (24) defining an ordered sequence for successive activation of the DC-DC converter phases for increasing load conditions or successive deactivation of the DC-DC converter phases for decreasing load conditions. Salus et al. (US Pub No. 2023/0421040 ) disclose a first phase circuit comprises first cells each has a bridge circuit and a switch circuit. The digital controller is to indicate, to the switch circuit, whether to provide a respective conductive path to enable the cell to conduct a current with a corresponding one of the first contacts. The current is to be generated with the bridge circuit based on the driver signals. Roessig et al. (US P at No. 12,418,239 ) disclose two or more converter phases formed on the semiconductor substrate; two or more programmable components formed on the semiconductor substrate, each of the programmable components connected to a respective one of the two or more converter phases; and an interconnect circuit formed on the semiconductor substrate. The two or more programmable components are programmable to selectively couple the two or more converter phases to the plurality of controllers via the interconnect circuit. Araki et al. (US Pat No. 12,255,665 ) disclose a semiconductor integrated circuit includes a first converter, a second converter, and an adjustment circuit. The first converter is configured to sample an analog signal and convert the sampled analog signal to a first digital value based on a first clock signal. The second converter is configured to sample the analog signal and convert the sampled analog signal to a second digital value based on a second clock signal shifted a first phase from the first clock signal. Mannes Hillesheim et al. (US Pub No. 20 21 /0 167780 ) disclose a first-clock and second-clock inputs configured to receive respective first-clock and second-clock signal having the frequency and respective first and second phases from neighbouring controllers; and wherein the signal generator comprises a phase adjustment circuit configured to adjust the phase of the periodic signal so as to be equidistant from the first and second phase, wherein the phase adjustment circuit determines an error signal in dependence on an offset between the phase and a mid-point between the first phase and the second phase, and a feedback circuit configured to adjust the phase in dependence on the error signal. autonum Any inquiry concerning this communication or earlier communications from the examiner should be directed to examiner Raymond Phan, whose telephone number is (571) 272-3630. The examiner can normally be reached on Monday-Friday from 6:30AM 3:00PM. The Group Fax No. (571) 273-8300. Communications via Internet e-mail regarding this application, other than those under 35 U.S.C. 132 or which otherwise require a signature, may be used by the applicant and should be addressed to [ raymond.phan@uspto.gov ]. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice . If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrew Jung can be reached at (571) 270-3779. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. All Internet e-mail communications will be made of record in the application file. PTO employees do not engage in Internet communications where there exists a possibility that sensitive information could be identified or exchanged unless the record includes a properly signed express waiver of the confidentiality requirements of 35 U.S.C. 122. This is more clearly set forth in the Interim Internet Usage Policy published in the Official Gazette of the Patent and Trademark on February 25, 1997 at 1195 OG 89. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see hop://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). Any inquiry of a general nature or relating to the status of this application should be directed to the TC 2100 central telephone number is (571) 272-2100. /RAYMOND N PHAN/ Primary Examiner, Art Unit 2175