DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 03/09/2026 has been entered.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-6,9-22, 25-30 and 32 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-5, 9-10, 12-21 and 26-28 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tani et al. (JP2005063054A), hereinafter Tani [Previously cited], in view of Schmalzl (US PAT 10,761,135).
(Figure 1 of Tani is provided with annotations below for the applicant’s convenience)
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With respect to claim 1, Tani discloses a method of testing circuitry (See paragraph [0046] of Tani), comprising: testing (See paragraph [0046] of Tani), in a first occasion (See the “self-diagnostic” disclosed in paragraph [0046] of Tani), a first electrical circuit (See the annotated [A] in figure 1 of Tani above), having a first component (See [21] in figure 1 of Tani above), using at least a second component (See [22] in figure 1 of Tani above) of a second electrical circuit (See the annotated [B] in figure 1 of Tani above); testing, in a second occasion (See the “mutual monitoring” disclosed in paragraph [0046] of Tani), the second electrical circuit using at least the first component of the first electrical circuit (See the “mutual monitoring” disclosed in paragraph [0046] in view of the bi-directional arrows between [21] and [22] as shown in figure 1 of Tani above) but fails to disclose monitoring a signal output by a third electrical circuit using the first electrical circuit, the monitoring being based on a comparison of the signal with a reference signal output by the first component. However, Schmalzl does disclose monitoring a signal output by a third electrical circuit (See the “third electrical circuit” [510] in figure 5 of Schmalzl) using the first electrical circuit (See the “first electrical circuit” [530] in figure 5 of Schmalzl), the monitoring being based on a comparison (See the comparator [530] in figure 5 of Schmalzl) of the signal (See the signal output from element [514] in figure 5 of Schmalzl) with a reference signal output by the first component (See the signal output of element [520] in figure 5 of Schmalzl). Furthermore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the device disclosed by Tani to include the features disclosed by Schmalzl because doing so enhances error detection accuracy and redundancy.
With respect to claim 2, the combination of Tani and Schmalzl discloses the method of claim 1, wherein testing the first electrical circuit comprises testing a plurality of operational states associated with the first electrical circuit (See the modes disclosed in paragraph [0047] of Tani).
With respect to claim 3, the combination of Tani and Schmalzl discloses the method of claim 2, wherein each of the plurality of operational states is associated with a different voltage level, a different current level, a different temperature, or a combination thereof (See the output from the test circuit [21] disclosed in paragraph [0047] of Tani).
With respect to claim 4, the combination of Tani and Schmalzl discloses the method of claim 1, wherein testing the first electrical circuit comprises comparing a first voltage output by the first component to a second voltage output by the second component (See paragraph [0024] of Tani).
With respect to claim 5, the combination of Tani and Schmalzl discloses the method of claim 1, wherein testing the first electrical circuit comprises performing a built-in self-test associated with the first electrical circuit (See the “self-diagnostic” disclosed in paragraph [0046] of Tani).
With respect to claim 9, the combination of Tani and Schmalzl discloses the method of claim 1, wherein monitoring the signal comprises monitoring a voltage level of the signal using a comparator of the first electrical circuit (See paragraph [0023] of Tani), the comparator having a first input coupled to the first component and a second input selectively coupled to the second component and an output of the third electrical circuit (See paragraph [0047] of Tani).
With respect to claim 10, the combination of Tani and Schmalzl discloses the method of claim 1, further comprising monitoring a plurality of properties associated with the third electrical circuit (See paragraph [0047] of Tani) through monitoring the signal output by the third electrical circuit (See the output [11] of circuit [14] in figure 1 of Tani) using the first electrical circuit (See [A] in figure 1 of Tani above) and the second electrical circuit (See [B] in figure 1 of Tani above).
With respect to claim 12, the combination of Tani and Schmalzl discloses the method of claim 1, further comprising testing, in a third occasion (See the outputting of the test results to [13] disclosed in paragraph [0046] of Tani), the third electrical circuit using at least the second component of the second electrical circuit or the first component of the first electrical circuit (See the combination of [13], [16] and [17] in paragraph [0046] of Tani).
With respect to claim 13, the combination of Tani and Schmalzl discloses the method of claim 1, further comprising testing, in a third occasion (See the outputting of the test results to [13] disclosed in paragraph [0046] of Tani), the first electrical circuit using at least a third component of a third electrical circuit (See [16] in figure 1 of Tani above).
With respect to claim 14, the combination of Tani and Schmalzl discloses the method of claim 1, wherein testing the first electrical circuit comprises testing the first electrical circuit in compliance with a functional safety standard associated with a vehicle (See paragraph [0045] of Tani).
With respect to claim 15, Tani discloses a method of testing circuitry (See paragraph [0046] of Tani), comprising: testing (See paragraph [0046] of Tani), in a first occasion (See the “self-diagnostic” disclosed in paragraph [0046] of Tani), a first electrical circuit (See the annotated [A] in figure 1 of Tani above), having a first component (See [21] in figure 1 of Tani above), using at least a second component (See [22] in figure 1 of Tani above) of a second electrical circuit (See the annotated [B] in figure 1 of Tani above); but fails to disclose monitoring a signal output by a third electrical circuit using the first electrical circuit in response to detecting a successful test from the testing, wherein monitoring the signal comprises comparing the signal to a reference signal output by the first component. However, Schmalzl does disclose monitoring a signal output by a third electrical circuit (See the “third electrical circuit” [510] in figure 5 of Schmalzl) using the first electrical circuit (See the “first electrical circuit” [530] in figure 5 of Schmalzl) in response to detecting a successful test from the testing (See Col. 9, lines 1-13 of Schmalzl), wherein monitoring the signal comprises comparing (See the comparator [530] in figure 5 of Schmalzl) the signal (See the signal output from element [514] in figure 5 of Schmalzl) to a reference signal output by the first component (See the signal output of element [520] in figure 5 of Schmalzl). Furthermore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the method disclosed by Tani to include the method steps disclosed by Schmalzl because doing so enhances error detection accuracy and redundancy.
With respect to claim 16, the combination of Tani and Schmalzl discloses the method of claim 15, further comprising testing (See paragraph [0046] of Tani), in a second occasion (See the “mutual monitoring” disclosed in paragraph [0046] of Tani), the first electrical circuit (See the annotated [A] in figure 1 of Tani above) using at least a third component (See [16] in figure 1 of Tani) of a fourth electrical circuit (See [D] in figure 1 of Tani above); wherein the monitoring occurs in a third occasion (See the outputting of the test results to [13] disclosed in paragraph [0046] of Tani).
With respect to claim 17, Tani discloses an apparatus for testing circuitry (See paragraph [0046] of Tani), comprising: a first electrical circuit (See the annotated [A] in figure 1 of Tani above) having a first component (See [21] in figure 1 of Tani above); a second electrical circuit (See the annotated [B] in figure 1 of Tani above) having a second component (See [22] in figure 1 of Tani above) selectively (See paragraph [0047] of Tani) coupled to the first electrical circuit (See the annotated [A] in figure 1 of Tani above); a third electrical circuit configured to output a signal (See the output [11] of circuit [14] in figure 1 of Tani); at least one memory (See paragraph [0050] of Tani); and at least one processor (See paragraph [0050] of Tani) coupled to the memory (See paragraph [0050] of Tani), the processor being configured to: test (See paragraph [0046] of Tani), in a first occasion (See the “self-diagnostic” disclosed in paragraph [0046] of Tani), the first electrical circuit (See the annotated [A] in figure 1 of Tani above) using at least the second component (See [22] in figure 1 of Tani above), and test, in a second occasion (See the “mutual monitoring” disclosed in paragraph [0046] of Tani), the second electrical circuit (See the annotated [B] in figure 1 of Tani above) using at least the first component (See [21] in figure 1 of Tani above) but fails to disclose monitor the signal output by the third electrical circuit using the first electrical circuit, based on a comparison of the signal with a reference signal output by the first component. However, Schmalzl does disclose monitor the signal output by the third electrical circuit (See the “third electrical circuit” [510] in figure 5 of Schmalzl) using the first electrical circuit (See the “first electrical circuit” [530] in figure 5 of Schmalzl), based on a comparison (See the comparator [530] in figure 5 of Schmalzl) of the signal (See the signal output from element [514] in figure 5 of Schmalzl) with a reference signal output by the first component (See the signal output of element [520] in figure 5 of Schmalzl). Furthermore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the device disclosed by Tani to include the features disclosed by Schmalzl because doing so enhances error detection accuracy and redundancy.
With respect to claim 18, the combination of Tani and Schmalzl discloses the apparatus of claim 17, wherein to test the first electrical circuit, the processor is further configured to test a plurality of operational states associated with the first electrical circuit (See the modes disclosed in paragraph [0047] of Tani).
With respect to claim 19, the combination of Tani and Schmalzl discloses the apparatus of claim 18, wherein each of the plurality of operational states is associated with a different voltage level, a different current level, a different temperature, or a combination thereof (See the output from the test circuit [21] disclosed in paragraph [0047] of Tani).
With respect to claim 20, the combination of Tani and Schmalzl discloses the apparatus of claim 17, wherein to test the first electrical circuit, the processor is further configured to compare a first voltage output by the first component to a second voltage output by the second component (See paragraph [0024] of Tani).
With respect to claim 21, the combination of Tani and Schmalzl discloses the apparatus of claim 17, wherein to test the first electrical circuit, the processor is further configured to perform a built-in self-test associated with the first electrical circuit (See the “self-diagnostic” disclosed in paragraph [0046] of Tani).
With respect to claim 26, the combination of Tani and Schmalzl discloses the apparatus of claim 17, wherein the processor is further configured to test, in a third occasion (See the outputting of the test results to [13] disclosed in paragraph [0046] of Tani), the third electrical circuit using at least the second component of the second electrical circuit or the first component of the first electrical circuit (See the combination of [13], [16] and [17] in paragraph [0046] of Tani).
With respect to claim 27, the combination of Tani and Schmalzl discloses the apparatus of claim 17, wherein the third electrical circuit has a third component and wherein the processor is further configured to test, in a third occasion (See the outputting of the test results to [13] disclosed in paragraph [0046] of Tani), the first electrical circuit using at least the third component of the third electrical circuit (See [16] in figure 1 of Tani above).
With respect to claim 28, the combination of Tani and Schmalzl discloses the apparatus of claim 17, wherein to test the first electrical circuit, the processor is further configured to test the first electrical circuit in compliance with a functional safety standard associated with a vehicle (See paragraph [0045] of Tani).
Claim(s) 6, 11, 22 and 25 is/are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Tani and Schmalzl, and further in view of Yang et al. (US PAT 7,158,070), hereinafter Yang [Previously cited].
(Figure 2 of Yang is provided with annotations below for the applicant’s convenience)
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With respect to claim 6, the combination of Tani and Schmalzl discloses the method of claim 1, wherein: but fails to disclose the first component includes a first digital-to-analog-converter (DAC); the second component includes a second DAC; and the first electrical circuit includes a comparator having a first input coupled to an output of the first DAC and a second input selectively coupled to an output of the second DAC. However, Yang does disclose the first component includes a first digital-to-analog-converter (See [213] in figure 2 of Yang); the second component includes a second DAC (See [215] in figure 2 of Yang); and the first electrical circuit includes a comparator (See [203] in figure 2 of Yang) having a first input coupled to an output of the first DAC (See [213] in figure 2 of Yang) and a second input selectively (See [225] in figure 2 of Yang) coupled to an output of the second DAC (See [215] in figure 2 of Yang). Furthermore, it would have been obvious to one of ordinary skill in the art before the filing date of the invention to modify the method disclosed by the combination of Tani and Schmalzl to include the method steps disclosed by Yang because doing so allows high precision detection with a minimalization of system error.
With respect to claim 11, the combination of Tani and Schmalzl discloses the method of claim 1, further comprising monitoring another signal (See Col. 9, lines 34-43 which discloses the output signal of [542] which creates another signal output from [510] depending upon the frequency selected) output by the third electrical circuit using the second electrical circuit based on another reference signal output by the second component (See Col. 9, lines 34-43 which discloses the “second electrical circuit” [542] which creates “another reference signal” depending upon the frequency selected).
With respect to claim 22, the combination of Tani and Schmalzl discloses the apparatus of claim 17, but fails to disclose wherein: the first component includes a first digital-to-analog-converter (DAC); the second component includes a second DAC; and the first electrical circuit includes a comparator (See [203] in figure 2 of Yang) having a first input coupled to an output of the first DAC and a second input selectively coupled to an output of the second DAC. However, Yang does disclose wherein: the first component includes a first digital-to-analog-converter (See [213] in figure 2 of Yang); the second component includes a second DAC (See [215] in figure 2 of Yang); and the first electrical circuit includes a comparator (See [203] in figure 2 of Yang) having a first input coupled to an output of the first DAC (See [213] in figure 2 of Yang) and a second input selectively (See [225] in figure 2 of Yang) coupled to an output of the second DAC (See [215] in figure 2 of Yang). Furthermore, it would have been obvious to one of ordinary skill in the art before the filing date of the invention to modify the method disclosed by the combination of Tani and Schmalzl to include the method steps disclosed by Yang because doing so allows high precision detection with a minimalization of system error.
With respect to claim 25, the combination of Tani and Schmalzl discloses the apparatus of claim 17, but fails to disclose further comprising a comparator having a first input coupled to the first component and a second input selectively coupled to the second component and an output of the third electrical circuit, wherein to monitor the signal, the processor is further configured to monitor a voltage level of the signal using the comparator. However, Yang does disclose a comparator (See [203] in figure 2 of Yang) having a first input coupled to the first component (See the input of [203] connected to [213] in figure 2 of Yang) and a second input selectively (See [225] in figure 2 of Yang) coupled to the second component (See [215] in figure 2 of Yang) and an output of the third electrical circuit (See the output [260] of the third electrical circuit [201] in figure 2 of Yang), wherein to monitor the signal (See the feedback relationship between the output [260] and the input of [203] in figure 2 of Yang), the processor is further configured to monitor a voltage level of the signal using the comparator (See claim 1 of Yang). Furthermore, it would have been obvious to one of ordinary skill in the art before the filing date of the invention to modify the device disclosed by Tani to include the features disclosed by Yang because doing so allows high precision detection with a minimalization of system error.
Allowable Subject Matter
Claim 32 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
With respect to claim 32, the prior art of record neither shows nor suggests the combination of structural elements wherein monitoring the signal comprises monitoring a voltage level of the signal using a comparator of the first electrical circuit, the comparator having a first input coupled to the first component and a second input selectively coupled to the second component and an output of the third electrical circuit.
Claims 29 and 30 are allowed.
The following is a statement of reasons for the indication of allowable subject matter:
With respect to claim 29, the prior art of record neither shows nor suggests the combination of structural elements comprising a first electrical circuit having a first digital-to-analog converter (DAC) and a first comparator, wherein the first DAC is coupled to a first input of the first comparator; a second electrical circuit having a second DAC selectively coupled to a second input of the first comparator; and a third electrical circuit having an output selectively coupled to the second input of the first comparator, wherein the first electrical circuit further comprises a multiplexer having a first input coupled to the output of the third electrical circuit, a second input coupled to an output of the second DAC, and an output coupled to the second input of the first comparator.
Claim 30 depends from allowed claim 29 and is therefore also allowed.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US PUB 2009/0121738 discloses a semiconductor test device.
US PUB 2008/0288197 discloses a calibration of multi-metric sensitive delay measurement circuits
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TEMILADE S RHODES-VIVOUR whose telephone number is (571)270-5814. The examiner can normally be reached M-F (flex schedule).
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/TEMILADE S RHODES-VIVOUR/Examiner, Art Unit 2858
/HUY Q PHAN/Supervisory Patent Examiner, Art Unit 2858