DETAILED ACTION
Claims 1-18 are presented for examination.
This office action is in response to submission of application on 03/02/2023.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 03/02/2023 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Allowable Subject Matter
Claims 3, 9, and 15 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112 set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Claim Objections
Claims 1, 7, and 13 are objected to because of the following informalities: “thresholded” should be “limited by a threshold”. Appropriate correction is required.
Claim 2, 8, and 14 are objected to because of the following informalities: “...the latency, the runtime memory and the size are exponential are added as a combined weighted exponential function…” should be “...the latency, the runtime memory and the size are exponential and are added together as a combined weighted exponential function…”. For examination purposes, the examiner is interpreting “..the latency, the runtime memory and the size are exponential are added as a combined weighted exponential function…” to be “...the latency, the runtime memory and the size are exponential and are added together as a combined weighted exponential function…”. Appropriate correction is required.
Specification
The disclosure is objected to because of the following informalities:
From ¶[006] onward, all instances of “thresholded” should be “limited by a threshold”.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-18 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation "… wherein an EA agent of the FAST EA NAS model generates a plurality of child Neural Network (NN) architectures for the fine-grained NAS space from the NAS space…". There is insufficient antecedent basis for “the fine-grained NAS space”. Claims 7 and 13 are substantially similar and are rejected on the same basis. Dependent claims 2-6, 8-12, and 14-18 inherit the deficiency and therefore are rejected on the same basis.
Claim 1 recites the limitation "… wherein an EA agent of the FAST EA NAS model generates a plurality of child Neural Network (NN) architectures for the fine-grained NAS space from the NAS space…". It is unclear whether “the NAS space” refers to “a Neural Architecture Search (NAS) space(SO×C)” or “a refined NAS space (S'O'×C')” recited in claim 1. There is insufficient antecedent basis for “the NAS space”. Claims 7 and 13 are substantially similar and are rejected on the same basis. Dependent claims 2-6, 8-12, and 14-18 inherit the deficiency and therefore are rejected on the same basis.
Claim 5 recites the equation
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, where the terms “ NA” and “NM” appear in the equation. The terms “ NA” and “NM” have not been defined in the claims or the specification sufficiently for one of ordinary skill to ascertain its scope. Therefore the meaning is uncertain and the term is indefinite. Claims 11 and 17 are substantially similar and are rejected on the same basis.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 4, 6, 7, 10, 12, 13, 16, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Liberis et al. (“μNAS: Constrained Neural Architecture Search for Microcontrollers”) hereafter Liberis, in view of Qin et al. ("GQNAS: Graph Q Network for Neural Architecture Search"), hereafter Qin.
Regarding claim 1, Liberis discloses:
A processor implemented method for automated creation of tiny Deep Learning (DL) models, the method comprising: receiving, via one or more hardware processors, a plurality of hardware specification parameters (page 1, right column, paragraph 1, lines 7-8 “we consider “mid-tier” IoT-sized MCUs with up to 64KB of SRAM and 64KB of persistent storage available” and page 2, right column, paragraph 4, lines 3-4 “we follow the execution strategy imposed by the TensorFlow Lite Micro” teaches a processor implemented method where a plurality of hardware specifications, such as SRAM and available storage, are received),
defining a plurality of performance metrics with relative metric weightages for creating a tiny model to be deployed on a platform having a set of hardware constraints (page 4, right column, final paragraph “
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” teaches a plurality of performance metrics with relative metric weightages, i.e. scalar term λ, for creating a tiny model to be deployed on a platform having a set of hardware constraints),
the plurality of performance metrics comprising an accuracy, a latency, a runtime memory usage, and a size of the tiny model (page 3, left column, first paragraph, lines 2-4 “We include four objectives, three of which are resource constraints: (1) top-1 validation set accuracy, (2) peak memory usage, (3) model size and (4) latency”),
formulating, via the one or more hardware processors, a multi-objective reward function (R) as a function of the plurality of performance metrics, wherein each of the plurality of performance metrics is individually modulated, prioritized and thresholded based on the relative metric weightage assigned to each of the plurality of performance metric in accordance of requirements of a target application to be executed on the platform via the tiny model, wherein the multi-objective reward function (R) is updated by iteratively profiling the platform to acquire the plurality of performance metrics (Table 3, page 4, right column, final paragraph “
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”
and page 5, left column, first paragraph “
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” teaches a multiple objective target function as a multi-objective reward function where each performance metric is assigned relative metric weightage by the scalar terms in accordance of requirements of a target application on a platform in the MCU via the tiny model, and that this function is updated iteratively in rounds),
creating, via the one or more hardware processors, a Neural Architecture Search (NAS) space(SO×C) comprising of a plurality of operations and configurations of Neural Network (NN) architectures in accordance with the target application (Table 1 and page 3, left column, final paragraph, lines 1-3 “ Thus an MCU-tailored search space should consist of small models, with few restrictions on layer connectivity and granular hyperparameters (see Table 1)”),
applying, via the one or more hardware processors, a coarse-grained search on the NAS space using a Fast Evolutionary Algorithm (EA) NAS model to find relevant operations and configurations from the plurality of operations and configurations that narrows the NAS space to a refined NAS space (S'O'×C') by identifying a set of Neural Network (NN) architectures from the NAS space that performs better than a reward threshold, wherein an EA agent of the FAST EA NAS model generates a plurality of child Neural Network (NN) architectures for the fine-grained NAS space from the NAS space based on the multi-objective reward function (R) (page 5, left column, paragraph 2, lines 1-6 “ We use aging evolution (AE) as a search algorithm for NAS [29] which optimises the goal function by repeatedly evolving a set of candidate points. AE keeps a population of architectures and, at each search round, samples architectures and chooses the one that gives the smallest value of ℒt (α)” teaches an evolutionary algorithm that narrows the NAS space to a refined NAS space that performs better than an objective reward threshold based on the multi-objective reward function and generates child neural networks for the population of architectures),
performing, via the one or more hardware processors, a fine-grained search on the refined NAS space to identify a customized and optimized architecture for the tiny model, wherein the fine-grained search … utilizes the multi-objective reward function (R) to identify the customized and optimized architecture for the tiny model (page 5, left column, final 2 paragraphs “This makes the search and the pruning share the task of determining the model’s hyperparameters: the search produces a base network, which is then adjusted by pruning in a more informed way by discarding channels/units that were deemed unimportant during training. µNAS uses the norm of channels/units to discard weight groups until the desired proportion is removed [23]. The network is gradually pruned during training until the target “sparsity” proportion (set by µNAS) is reached.” Teaches a fine grained search on the refined search space produced by the evolutionary algorithm to identify a customized and optimized architecture for the tiny model while utilizing the multi-objective reward function ℒ during training).
Liberis discloses performing, via the one or more hardware processors, a fine-grained search on the refined NAS space to identify a customized and optimized architecture for the tiny model, wherein the fine-grained search … utilizes the multi-objective reward function (R) to identify the customized and optimized architecture for the tiny model, but does not disclose the fine-grained search to utilize a Deep Q-Learning Network (DQN) NAS model, and wherein a DQN agent of the DQN NAS model utilizes … reward function (R).
Qin discloses:
the fine-grained search utilizes a Deep Q-Learning Network (DQN) NAS model, and wherein a DQN agent of the DQN NAS model utilizes … reward function … (Fig. 1 and equations 1 and 2 discloses a Deep Q-Learning Network (DQN) NAS model which utilizes a reward function).
Liberis and Qin are analogous art because they are from the same field of endeavor, Neural Architecture Search.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the teachings of Liberis to include the fine-grained search utilizes a Deep Q-Learning Network (DQN) NAS model, and wherein a DQN agent of the DQN NAS model utilizes … reward function, based on the teachings of Qin. One of ordinary skill in the art would have been motivated to make this modification in order to use less time to design an architecture and have higher efficiency on using knowledge learning from different architectures, as suggested by Qin (page 1292, right column, paragraph 1, lines 4-7 “GQNAS uses less than half of its searching time to design an architecture, showing that our framework has higher efficiency on using knowledge learning from different architectures”).
Regarding claim 4, Liberis, in view of Qin, discloses the method of claim 1 (and thus the rejection of claim 1 is incorporated). Liberis further discloses:
wherein an actual latency performance metric required by the multi-objective reward function (R) is predicted using a prediction function (P), without actually profiling the Neural Network (NN) architectures on a platform to enable faster NAS search (Figure 2 and page 4, right column, second paragraph, lines 1-2 “We settle on using a number of multiply-accumulate operations (MACs) as a proxy for model latency.” Teaches MAC operations as prediction functions that calculate actual latency without profiling the NN architecture).
Regarding claim 6, Liberis, in view of Qin, discloses the method of claim 1 (and thus the rejection of claim 1 is incorporated). Liberis further discloses:
wherein the relative metric weightages assigned to each of the performance metric are tunable, enabling dynamic changing of the multi-objective reward function (R) without requiring rebuilding and retraining of the Fast Evolutionary Algorithm (EA) NAS and the DQN architecture to align to changing requirements of the target application to be executed on the platform (page 5, left column, first paragraph “
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” discloses a tunable λ as tunable relative metric weightage).
Claims 7 and 13 are substantially similar to claim 1, and thus are rejected on the same basis as claim 1.
Claims 10 and 16 are substantially similar to claim 4, and thus are rejected on the same basis as claim 4.
Claims 12 and 18 are substantially similar to claim 6, and thus are rejected on the same basis as claim 6.
Claims 2, 8, and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Liberis et al. (“μNAS: Constrained Neural Architecture Search for Microcontrollers”) hereafter Liberis, in view of Qin et al. ("GQNAS: Graph Q Network for Neural Architecture Search"), hereafter Qin, in further view of Zhang et al. ("AS-NAS: Adaptive Scalable Neural Architecture Search With Reinforced Evolutionary Algorithm for Deep Learning"), as cited in the IDS dated 03/02/2023, hereafter Zhang.
Regarding claim 2, Liberis, in view of Qin, discloses the method of claim 1 (and thus the rejection of claim 1 is incorporated). Liberis further discloses:
wherein a weighted relation of the multi-objective reward function (R) with the accuracy is linear (Equation 1 discloses the weighted relation of the target reward function to be linear with the accuracy), and
the latency, the runtime memory and the size …are added as a combined weighted … function … based on the hardware constraints for each of the latency, the runtime memory, and the size among the plurality of performance metrics (Equation 1, page 4, right column, final paragraph, lines 2-3 “…to combine multiple objectives into a single goal (the target function for optimization…” and Table 2 discloses the latency, the runtime memory and the size to be combined as a weighted function based on the hardware constraints for each of the latency, the runtime memory, and the size among the plurality of performance metrics).
While Liberis discloses the latency, the runtime memory and the size … are added as a combined weighted … function … based on the hardware constraints for each of the latency, the runtime memory, and the size among the plurality of performance metrics, they do not disclose these metrics to be exponential and combining them as an exponential function of a difference between one or more actual values and one or more target values.
Zhang discloses:
performance metrics are exponential are added as a combined weighted exponential function of a difference between one or more actual values and one or more target values (page 835, equations 7-10 and right column, fourth paragraph, lines 4-7 “ri(t) is simply formulated as a function related to the difference between the current and previous fitness values, and the difference between the current and previous best fitness values” teaches exponential metrics, prefixed by “exp” and “ln” in particular, which are added as a combined weighted exponential function of a difference between one or more actual values and one or more target values).
Liberis, Qin, and Zhang are analogous art because they are from the same field of endeavor, Neural Architecture Search.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the teachings of Liberis, in view of Qin, to include performance metrics are exponential are added as a combined weighted exponential function of a difference between one or more actual values and one or more target values, based on the teachings of Zhang. One of ordinary skill in the art would have been motivated to make this modification in order to improve the search efficacy, as suggested by Zhang (page 835, left column, paragraph 2, line 1).
Claims 8 and 14 are substantially similar to claim 2, and thus are rejected on the same basis as claim 2.
Claims 5, 11, and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Liberis et al. (“μNAS: Constrained Neural Architecture Search for Microcontrollers”) hereafter Liberis, in view of Qin et al. ("GQNAS: Graph Q Network for Neural Architecture Search"), hereafter Qin, in further view of Li Lyna Zhang et al. ("nn-Meter: Towards Accurate Latency Prediction of Deep-Learning Model Inference on Diverse Edge Devices "), hereafter Lyna Zhang, in further view of Asperti et al. (“Dissecting FLOPs along input dimensions for GreenAI cost estimations”), hereafter Asperti.
Regarding claim 5, Liberis, in view of Qin, discloses the method of claim 4 (and thus the rejection of claim 4 is incorporated). Liberis further discloses:
the prediction function (P) is mathematically expressed … platform dependent effective execution time for multiplication and addition (Examiner’s Note: BRI of multiplication and addition includes floating point operations) (Figure 2 discloses a reproduced mathematical model of FLOPs, i.e. floating point operations, that denote platform dependent effective execution time for multiplication and addition, for latency prediction).
While Liberis discloses the prediction function (P) is mathematically expressed … platform dependent effective execution time for multiplication and addition, they do not disclose:
wherein the prediction function (P) is mathematically expressed as
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, wherein ETM and ETA indicate a platform dependent effective execution time for multiplication and addition respectively, and βi is a platform dependent memory overhead.
Lyna Zhang discloses:
wherein the prediction function (P) is mathematically expressed …, wherein ETM and ETA indicate a platform dependent effective execution … for multiplication and addition respectively, and βi is a platform dependent memory overhead (page 81, right column, first footnote “The definition of FLOPs follows [35], i.e., the number of multiply-adds.” and page 89, left column, paragraph 3, lines 6-7 “we use the FLOPs and memory access cost (i.e., MAC) to estimate model latency” teaches prediction of latency to be computed from platform dependent effective execution for multiplication and addition through FLOPs, and platform dependent memory overhead through memory access cost).
Liberis, Qin, and Lyna Zhang are analogous art because they are from the same field of endeavor, Deep Learning.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the teachings of Liberis, in view of Qin, to include wherein the prediction function (P) is mathematically expressed …, wherein ETM and ETA indicate a platform dependent effective execution … for multiplication and addition respectively, and βi is a platform dependent memory overhead, based on the teachings of Lyna Zhang. One of ordinary skill in the art would have been motivated to make this modification in order to achieve better prediction accuracy, as suggested by Lyna Zhang (page 82, right column, fourth point).
While Lyna Zhang discloses wherein the prediction function (P) is mathematically expressed …, wherein ETM and ETA indicate a platform dependent effective execution … for multiplication and addition respectively, and βi is a platform dependent memory overhead, they do not explicitly disclose a summation of the discussed metrics and an effective execution time.
Asperti discloses:
a summation wherein ETM and ETA indicate a … execution time for multiplication and addition respectively (Equations 1-4 and Fig. 1 discloses calculation of a prediction to comprise a summation of metrics indicating execution times for multiplication and addition in FLOPs).
Liberis, Qin, Lyna Zhang, and Asperti are analogous art because they are from the same field of endeavor, Deep Learning.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the teachings of Liberis, in view of Qin, in further view of Lyna Zhang, to include a summation wherein ETM and ETA indicate a … execution time for multiplication and addition respectively, based on the teachings of Asperti. One of ordinary skill in the art would have been motivated to make this modification in order to provide better estimation for actual costs, as suggested by Asperti (page 2, paragraph 5, lines 2-3).
Claims 11 and 17 are substantially similar to claim 5, and thus are rejected on the same basis as claim 5.
Regarding claim 3, none of the prior art of record, alone or in combination, fairly teaches or suggest the limitation of claim 3, in the specific combination as recited in the claim. Claims 9 and 15 are substantially similar, and thus the same rationale applies for claims 9 and 15..
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's
disclosure.
U.S. Pub No. 2022/0035878 A1: Sarah et al. teaches deep q learning and NAS.
Tan et al. (“MnasNet: Platform-Aware Neural Architecture Search for Mobile”) teaches NAS and reward.
Zoph et al. (“NEURAL ARCHITECTURE SEARCH WITH REINFORCEMENT LEARNING”) teaches NAS.
Lin et al. (“MCUNet: Tiny Deep Learning on IoT Devices”) teaches NAS and tiny deep learning.
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/H.Z.M./Examiner, Art Unit 2141
/MATTHEW ELL/Supervisory Patent Examiner, Art Unit 2141
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