Prosecution Insights
Last updated: July 17, 2026
Application No. 18/177,766

DYNAMIC RANDOM ACCESS MEMORY DEVICE AND METHOD FOR FORMING THE SAME

Non-Final OA §102
Filed
Mar 03, 2023
Priority
Jan 04, 2023 — TW 112100177
Examiner
HARRISON, MONICA D
Art Unit
2815
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Powerchip Semiconductor Manufacturing Corporation
OA Round
1 (Non-Final)
92%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
94%
With Interview

Examiner Intelligence

Grants 92% — above average
92%
Career Allowance Rate
873 granted / 952 resolved
+23.7% vs TC avg
Minimal +3% lift
Without
With
+2.7%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 2m
Avg Prosecution
17 currently pending
Career history
969
Total Applications
across all art units

Statute-Specific Performance

§101
0.2%
-39.8% vs TC avg
§103
51.6%
+11.6% vs TC avg
§102
32.0%
-8.0% vs TC avg
§112
1.5%
-38.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 952 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election without traverse of Group I, claims 1-6, in the reply filed on 5/8/26 is acknowledged. Claims 7-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Group II, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 5/8/26. Priority Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1-6 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Bonart (US 2004/0135187 A1). Regarding claim 1, Bonart discloses a dynamic random access memory device (Figure 1, reference 10; Figures 4A and 4B), comprising: a substrate (Figure 1, reference 14) ; a plurality of word lines, extending toward a first direction (Figure 1, references 14c and 14d); a plurality of bit tines, extending toward a second direction (Figure 1, reference 22), wherein the second direction is orthogonal to the first direction (Figure 1); and a plurality of memory device layers, disposed on the substrate and stacked in a normal direction of the substrate, wherein each of the memory device layers comprises: a plurality of memory cells (Figure 1, reference 12), comprising a thin film transistor (Figure 1, reference 18) and a capacitor (Figure 1, reference 16), wherein each of the memory cells is electrically connected to a corresponding word line (Figure 1, reference 14D) and a corresponding bit line (Figure 1, reference 22); and a capacitor voltage transmission line (Figure 1, reference 16a and 16b; paragraph 0034), electrically connected to the capacitor (Figure 1, reference 16), wherein the word lines (Figure 1, references 14c and 14d) or the bit lines extends in a same direction as the capacitor voltage transmission line (Figure 1, reference 16a and 16b; paragraph 0034). Regarding claim 2, Bonart discloses wherein a material of a channel layer of the thin film transistor comprises an oxide semiconductor (Figure 1, reference 18e). Regarding claim 3, Bonart discloses wherein the channel layer (Figure 1, reference 18e) extends toward the normal direction of the substrate (Figure 1, reference 14). Regarding claim 4, Bonart discloses wherein the bit lines (Figure 1, reference 22) extend in the normal direction of the substrate (Figure 1, reference 14). Regarding claim 5, Bonart discloses wherein the word lines (Figure 1, references 14c and 14D) extend toward the normal direction of the substrate (Figure 1, reference 14). Regarding claim 6, Bonart discloses wherein a drain of the thin film transistor and the bit line belong to the same layer (Figure 4A, references 52b and 58). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to MONICA D HARRISON whose telephone number is (571)272-1959. The examiner can normally be reached M-F 7-4:30pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Joshua Benitez can be reached at 571-270-1435. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /MONICA D HARRISON/Primary Examiner, Art Unit 2815 mdh May 19, 2026
Read full office action

Prosecution Timeline

Mar 03, 2023
Application Filed
May 22, 2026
Non-Final Rejection mailed — §102 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
92%
Grant Probability
94%
With Interview (+2.7%)
2y 2m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 952 resolved cases by this examiner. Grant probability derived from career allowance rate.

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