Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Machida (US20180107559A1).
Machida discloses:
1. A control apparatus comprising:
a plurality of processor cores connected to: (fig 1)
a monitor that monitors whether a first processor core, the first processor core being any processor core among the plurality of processor cores, is operating normally; and (par 12-13; fig 3a, 3b)
a memory having a plurality of storage areas pre-associated with each of the plurality of processor cores, wherein: (par 19-20; fig 1)
each of the plurality of processor cores periodically writes and updates information to the corresponding storage area in the memory, the information indicating that each of the processor cores is operating normally; and (par 19-20, 23; fig 1)
the first processor core determines whether the information in each of the storage areas in the memory has been updated by each of the plurality of processor cores, and controls the monitor on a basis of a result of the determination. (fig 3a, 3b; par 23)
2. The control apparatus according to claim 1, wherein a timing at which the first processor core determines the presence or absence of an update of the information is different from a timing at which each of the plurality of processor cores updates the information. (fig 3a, 3b; par 23)
3. The control apparatus according to claim 2, wherein the first processor core determines the presence or absence of the update of the information between one update and a next update of the information. (par 23, 27-28, 33)
4. The control apparatus according to claim 1, wherein:
the memory has a plurality of the storage areas for each of the plurality of processor cores; (par 19-20; fig 1)
each of the plurality of processor cores periodically writes the information sequentially to the corresponding plurality of storage areas in the memory; and (par 19-20; fig 1)
the first processor determines that the information has been updated if the information has been updated in either or both of the plurality of storage areas. (fig 3a, 3b; par 23)
5. The control apparatus according to claim 4, wherein the first processor determines that the information has not been updated if the information has been updated in none of the plurality of storage areas. (par 33-34)
6. The control apparatus according to claim 1, wherein if the information has been updated for each of the plurality of processor cores, the first processor core instructs the monitor to clear a count. (par 29-32)
7. The control apparatus according to claim 6, wherein if the information has not been updated for one or more of the plurality of processor cores, the first processor core determines that an abnormality has occurred and instructs the monitor to reset all of the plurality of processor cores. (par 36-37)
8. The control apparatus according to claim 6, wherein if the information has not been updated for one or more of the plurality of processor cores, the first processor core determines that an abnormality has occurred and instructs the monitor to reset only the processor core in which the abnormality has occurred from among the plurality of processor cores. (par 36-37)
9. The control apparatus according to claim 1, wherein if there is no instruction for a fixed time or longer from the first processor core, the monitor outputs a reset signal that resets all of the plurality of processor cores. (par 36-37)
10. The control apparatus according to claim 9, further comprising:
an interrupt unit that receives the reset signal from the monitor and performs, according to the received reset signal, an interrupt process that substitutes the first processor core with a predetermined different processor core. (par 36-37; fig 1)
11. An image processing apparatus comprising: the control apparatus according to claim 1; and an image processor controlled by the control apparatus. (fig 1; par 15)
12. An image processing apparatus comprising: the control apparatus according to claim 2; and an image processor controlled by the control apparatus. (fig 1; par 15)
13. An image processing apparatus comprising: the control apparatus according to claim 3; and an image processor controlled by the control apparatus. (fig 1; par 15)
14. An image processing apparatus comprising: the control apparatus according to claim 4; and an image processor controlled by the control apparatus. (fig 1; par 15)
15. An image processing apparatus comprising: the control apparatus according to claim 5; and an image processor controlled by the control apparatus. (fig 1; par 15)
16. An image processing apparatus comprising: the control apparatus according to claim 6; and an image processor controlled by the control apparatus. (fig 1; par 15)
17. An image processing apparatus comprising: the control apparatus according to claim 7; and an image processor controlled by the control apparatus. (fig 1; par 15)
18. An image processing apparatus comprising: the control apparatus according to claim 8; and an image processor controlled by the control apparatus. (fig 1; par 15)
Claim(s) 19 is/are rejected as being the method implemented by the apparatus of claim(s) 1, and is/are rejected on the same grounds.
Claim(s) 20 is/are rejected as being the medium implemented by the apparatus of claim(s) 1, and is/are rejected on the same grounds.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KATHERINE LIN whose telephone number is (571)431-0706. The examiner can normally be reached Monday-Friday; 8 a.m. - 5 p.m. EST.
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/KATHERINE LIN/Primary Examiner, Art Unit 2113