DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5, 7-10, 12-20 are rejected under 35 U.S.C. 103 as being unpatentable over Dalli et al. (US 2022/0198254 A1), hereinafter “Dalli”, and in view of Zhao et al. (2025/0238897 A1), hereinafter “Zhao”.
As per claim 1, Dalli teaches a method for acceleration of explainable machine learning techniques comprising:
“receiving, by one or more processors, a plurality of input-output data pairs associated with a target machine learning (ML) model” at [0121], [0169];
(Dalli teaches obtaining a 3-tuple dataset <I, O, E>, where I may refer to the input, O may refer to the output and E may refer to the explanation between the input I and the output O)
“generating, by the one or more processors, a plurality of data slices for each input-output data pair, distributing, by the one or more processors, the plurality of data slices for each input-output data pair across a plurality of processing cores associated with one or more accelerated hardware elements” at [0185]-[0190] and Fig. 11;
(Dalli teaches the XTTs maybe used in conjunction with a suitable Distributed Explainable Architecture (DEA) to increase the performance of the defined models. A Distributed Explainable Architecture DEA contains multiple explainable architecture DEAm. The DEA splits the dataset into multiple subset 2600 (i.e., “data slices”) of data in order to train the explainable architectures DEAm. The Distributed explainable architecture DEA may be useful for large datasets where the training data cannot fit in the CPU/GPU memory (i.e., “processing cores associated with one or more accelerated hardware elements”) of a single machine)
“generating, by the one or more processors, an explainable artificial intelligence (XAI) model for the target ML model based at least in part on a plurality of parameters of a solved matrix determined based at least in part on a performance of at least a Fourier transform operation on each data slice at each processing core of the one or more accelerated hardware elements in a parallel or near-parallel manner” at [0151]-[0155] and Figs. 11, 15;
(Dalli teaches generating the XAI model 1524 based on the input dataset 1502 denoted by X. X is a matrix with m dimension. Each dimension (m) represents the input features of X and each output represents the number of classes (n). The input matrix Xp is divided into K matrices. XT may be calculated by finding a transformation of XLP 1518, such that XT=Transform(XLP), wherein the transform function may be Fourier transforms.
wherein the XAI model is used to provide explainability data associated with the target ML model” at [0136], [0190]-[0199] and Fig. 11.
(Dalli teaches the XTT architecture may construct an Explanation Scaffolding from the output produced by the explainable architecture of the XTT and use it to illustrate the results to the interpreter to assist in understanding such hao the model arrived at such prediction. Dalli also teaches the XTTs may contain feature transformations of the training dataset. The XTT transform function may be a pipeline of transformations, including Fourier transformation)
Dalli does not explicitly teach “the Fourier transform operation comprise solving a convolutional regression based on an input-output data pair of the plurality of input-output data pairs to determine the plurality of parameters of the solved matrix” as claimed. However, Zhao teaches an image processing method based on a convolution algorithm by performing Fourier transformation operation, wherein “the Fourier transform operation comprise solving a convolutional regression based on an input-output data pair of the plurality of input-output data pairs to determine the plurality of parameters of the solved matrix” at [0018]-[0019]. Thus, it would have been obvious to one of ordinary skill in the art to combine Zhao with Dalli’s teaching to obtain convolution result by performing fast Fourier transform because “the present invention successively uses fast Fourier transform and fast Fourier invers transform to accelerate the convolution process of the image to be processed and the image template, so as to speed up the acquisition of pixel points that need to be reassigned in the corresponding image area, thereby speeding up the process of image expansion calculation and reducing the number of calculations”, as suggested by Zhao at [0021].
As per claim 2, Dalli and Zhao teach the method of claim 1 discussed above. Dalli also teaches: wherein “the XAI model is configured as at least one of a distilled model, a Shapley value analysis-based model, or an integrated gradient-based model, and wherein the XAI model is configured to be transformed into at least one matrix representation” at [0136], [0190]-[0199] and Fig. 11.
As per claim 3, Dalli and Zhao teach the method of claim 2 discussed above. Dalli also teaches: wherein “the XAI model is configured as a distilled model, and wherein the distilled model is generated based at least in part on assembling distributed outputs generated by the plurality of processing cores via the performance of at least the Fourier transform operation for each data slice” at [0136], [0190]-[0199] and Fig. 11.
As per claim 4, Dalli and Zhao teach the method of claim 3 discussed above. Dalli also teaches: wherein “the distributed outputs generated by the plurality of processing cores are assembled according to an internal table configured to describe the distribution of the data slice across the plurality of processing cores” at [0136], [0190]-[0199] and Fig. 11.
As per claim 5, Dalli and Zhao teach the method of claim 1 discussed above. Dalli also teaches: wherein “the plurality of data slices comprises individual rows of an input matrix and an output matrix of each input-output data pair” at [0151]-[0155], [0169].
As per claim 7, Dalli and Zhao teach the method of claim 1 discussed above. Dalli also teaches: wherein “the explainability data is provided based at least in part on comparing a XAI model output responsive to an ML model input with a ML model output generated by the target ML model” at [0155], [0210].
As per claim 8, Dalli and Zhao teach the method of claim 7 discussed above. Dalli also teaches: wherein “the explainability data comprises a contribution factor for each input feature of the ML model input” at [0155], [0210].
As per claim 9, Dalli and Zhao teach the method of claim 2 discussed above. Dalli also teaches: wherein “the XAI model is configured as a distilled model, and wherein the distilled model is a linear regression representation of the target ML model” at [0155]
As per claim 10, Dalli and Zhao teach the method of claim 1 discussed above. Dalli also teaches: wherein “the one or more accelerated hardware elements comprises one or more graphics processing unit (GPU) configured for efficiently performing matrix multiplication operations in parallel” at [0187].
As per claim 12, Dalli and Zhao teach the method of claim 1 discussed above. Dalli also teaches: wherein “the one or more accelerated hardware elements comprises one or more field programable gate array (FPGAs)” at [0226].
As per claim 13, Dalli and Zhao teach the method of claim 1 discussed above. Dalli also teaches: wherein “the one or more processors are in electronic communication with the one or more accelerated hardware element via a bus” at [0231]
Claims 14-20 recite similar limitations as in claims 1-13 and are therefore rejected by the same reasons.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Dalli and Zhao as applied to claims 1-5, 7-10, 12-20 above, and further in view of Kim et al. (US 2019/0155217 A1), hereafter “Kim”.
As per claim 6, Dalli and Zhao teach the method of claim 1 discussed above. Dalli does not teach: “each processing core is caused to perform a row-wise Fourier transform operation followed by a column-wise Fourier transform operation for each data slice” as claimed. However, Kim teaches a similar method for performing Fourier transform using a plurality of cores in parallel, wherein “each processing core is caused to perform a row-wise Fourier transform operation followed by a column-wise Fourier transform operation for each data slice” at [0030]-[0031]. Thus, it would have been obvious to one of ordinary skill in the art to combine Kim with Dalli’s teaching in order to “reduce the number of computations and the computation time when image processing apparatus perform Fourier transform”, as suggested by Kim at [0006].
Claims 11 are rejected under 35 U.S.C. 103 as being unpatentable over Dalli and Zhao as applied to claims 1-5, 7-10, 12-20 above, and further in view of Luo et al. (US 2023/0103753 A1), hereinafter “Luo”.
As per claim 11, Dalli and Zhao teach the method of claim 1 discussed above. Dalli does not explicitly teach: “the one or more accelerated hardware elements comprise one or more tensor processing unit (TPU) configured for rapid matrix multiplication operations” as claimed. However, Luo teaches a similar distributed Explainable machine learning which is implemented using tensor processing unit (TPU) at [0032]-[0033]. Thus, it would have been obvious to one of ordinary skill in the art to combine Luo with Dalli’s teaching to “accelerate the training, and the post-training deployment, of the machine-learning and artificial-intelligence process” because “tensor processing unit (TPE) capable of processing hundreds of thousand of operations (e.g., matrix operations) in a single clock cycle”, as suggested by Luo at [0032]-[0033].
Response to Arguments
Applicant’s arguments with respect to claims 1-5, 7-10, 12-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHANH B PHAM whose telephone number is (571)272-4116. The examiner can normally be reached Monday - Friday, 8am to 4pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sanjiv Shah can be reached at (571)272-4098. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/KHANH B PHAM/Primary Examiner, Art Unit 2166
April 3, 2026
Prosecution Insights